JP3607186B2 - Active matrix display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for improving the reliability and characteristics of an integrated circuit in which a number of thin-film insulating gate type semiconductor devices (thin film transistors or TFTs) are formed on an insulating surface. The semiconductor device according to the present invention is used for an active matrix such as a liquid crystal display or a drive circuit such as an image sensor, or an SOI integrated circuit or a conventional semiconductor integrated circuit (microprocessor, microcontroller, microcomputer, semiconductor memory, etc.). Is. Particularly, the present invention relates to a monolithic thin film integrated circuit in which an active matrix circuit for driving an electro-optical device and a driver circuit for driving the same, or a memory circuit and a central processing circuit (CPU) are formed on the same substrate, and It relates to a manufacturing method thereof.
[0002]
[Prior art]
2. Description of the Related Art In recent years, research on forming an insulated gate semiconductor device (MISFET) on an insulating substrate or a surface (insulating surface) separated from a semiconductor substrate by a thick insulating film even on a semiconductor substrate has been actively conducted. . In particular, a semiconductor device in which a semiconductor layer (active layer) is a thin film is called a thin film transistor (TFT). In such a semiconductor device, it is difficult to obtain an element having good crystallinity, such as a single crystal semiconductor, and a non-single crystal semiconductor that has crystallinity but is not single crystal is usually used.
[0003]
Such a non-single-crystal semiconductor has poor characteristics as compared with a single-crystal semiconductor, and in particular, a reverse voltage (that is, negative for an N-channel TFT and positive for a P-channel TFT) is applied to the gate electrode. When the voltage is applied, there is a problem that the leakage current between the source and the drain increases. In addition, there has been a problem of deterioration that the mobility of the TFT is lowered by application of a voltage. In order to solve such a problem, it is known that an intrinsic or weak N-type or P-type high resistance region needs to be provided between the source / drain region and the gate electrode.
In particular, when producing a high resistance region, the gate electrode is anodized, and at least the side surface is oxidized by other methods, and this oxide or oxide trace is used to perform doping in a self-aligned manner. A high resistance region having a uniform width was obtained.
[0004]
[Problems to be solved by the invention]
However, since such a high resistance region also functions as a resistor inserted in series between the source / drain, for example, when high speed operation is required, it is unnecessary. This is particularly a problem when TFTs that require different characteristics are formed on the same insulating surface. For example, when considering a monolithic circuit having an active matrix circuit for driving an electro-optic element and a driver circuit for driving the circuit on the same substrate, it is desirable that the leakage current be lower in the active matrix circuit. Therefore, a TFT having a wide high resistance region is desired.
[0005]
However, in a decoder circuit, a driver circuit, a CPU, a memory circuit, and the like, it is desired that the width of the high resistance region is small because of the necessity for high-speed operation. However, in TFTs formed on the same substrate by the same process, the width of the high resistance region is the same, and it is difficult to change the width of the high resistance region according to the circuit and purpose as described above. It was. For this reason, it has been difficult to produce a monolithic active matrix circuit or a monolithic integrated circuit which is a further development. The present invention relates to a semiconductor integrated circuit in which such a difficulty is solved and the width of a high resistance region is changed in accordance with characteristics and reliability required for a TFT and a circuit, and a manufacturing method thereof.
[0006]
[Means for Solving the Problems]
The first aspect of the present invention is to change the width of the obtained high resistance region by changing the anodic oxidation time in accordance with the TFT in the anodic oxidation step of the gate electrode. The second aspect of the present invention is that in the monolithic active matrix circuit, the width of the high resistance region of the TFT in the active matrix circuit for low off-current and low-frequency operation is set to a driver circuit for high-current drive and high-frequency operation, and low power consumption. This is larger than that of the TFT in the decoder circuit for power and high frequency operation. The third aspect of the present invention is to make the width of the high resistance region of the N-channel TFT larger than that of the P-channel TFT.
[0007]
For example, in a monolithic active matrix circuit, the width of the high resistance region of the TFT in the active matrix circuit is 0.4 to 1 μm, and in the driver circuit, an N-channel TFT (hereinafter referred to as NTFT) is 0.2. In a P-channel TFT (hereinafter referred to as PTFT), it is set to 0 to 0.2 μm. Further, in the decoder used for the central processing circuit (CPU) and other logic operation elements / circuits, the thickness is set to 0.3 to 0.4 μm for the N-channel TFT and 0 to 0.2 μm for the P-channel TFT. Thus, in the present invention, the width of the high resistance region of the TFT of the active matrix circuit is larger than that of the TFT of the driver / decoder, and the width of the high resistance region of the N channel type TFT is that of the P channel type TFT. It is large.In the present invention, the width in the channel width direction of the high resistance region in the N channel type TFT and the P channel type TFT of the driver circuit is larger than the width in the channel width direction of the high resistance region in the N channel type TFT of the active matrix circuit. Shall. The channel widths of the N-channel TFT and the P-channel TFT of the driver circuit and the width of the high resistance region in the channel width direction are equal to each other. A high resistance region is not necessarily provided in the P channel type TFT of the driver circuit. In the case of this P channel type TFT, the channel formation region is in contact with the source region and the drain region.
[0008]
As described above, the reason why the width of the high resistance region of the TFT of the active matrix circuit is larger than the width of the TFT of the driver or decoder is that the required TFT characteristics are the low leakage current and the latter high speed operation. This is because they are different from each other. On the other hand, changing the width of the high resistance region between the N-channel TFT and the P-channel TFT in the same driver or decoder is as follows.
[0009]
In particular, in an N-channel TFT, when a weak N-type high resistance region is provided, the electric field in the vicinity of the drain can be relaxed and deterioration due to the hot carrier effect can be suppressed. Therefore, it is desired that the high resistance region of the N-channel TFT in this case is a weak N-type. On the other hand, in a P-channel TFT, since deterioration due to hot carriers is small, it is not particularly necessary to provide such a high resistance region. On the contrary, the presence of the high resistance region causes a reduction in the operation speed of the TFT. Since the mobility of the P-channel TFT is inferior to that of the N-channel TFT, the width of the high resistance region is preferably as small as possible. As a result, as described above, the width of the high resistance region of the N-channel TFT is larger than that of the P-channel TFT.
[0010]
【Example】
Embodiment 1 FIGS. 1 and 2 show an example of manufacturing an integrated circuit having different kinds of TFTs according to the present invention. 2A, 2B, and 2C are plan views substantially corresponding to FIGS. 1A, 1C, and 1E, respectively. Moreover, FIG. 1 is a cross section of the part shown by the dashed-dotted line in FIG. First, a silicon oxide film 102 having a thickness of 1000 to 3000 mm was deposited on a substrate (Corning 7059, 300 mm × 300 mm or 100 mm × 100 mm) 101 by a sputtering method. This may be formed by plasma CVD.
[0011]
Thereafter, an amorphous silicon film was deposited in an amount of 300 to 1500, preferably 500 to 1000 by plasma CVD or LPCVD, and patterned to form island silicon regions 103 and 104. Then, silicon oxide having a thickness of 200 to 1500 mm, preferably 500 to 1000 mm, was formed by sputtering or plasma CVD. Since this silicon oxide film also functions as a gate insulating film, sufficient care is required for its production. For example, when the plasma CVD method is used, TEOS is used as a raw material, and RF discharge is performed at a substrate temperature of 150 to 400 ° C., preferably 200 to 250 ° C. together with oxygen, to decompose and deposit the raw material gas. The pressure ratio between TEOS and oxygen was 1: 1 to 1: 3, the pressure was 0.05 to 0.5 torr, and the RF power was 100 to 250 W. Alternatively, the substrate temperature may be set to 150 to 400 ° C., preferably 200 to 250 ° C. by TEOS as a raw material together with ozone gas by a low pressure CVD method or an atmospheric pressure CVD method.
[0012]
Then, KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to crystallize only the silicon region 103. Laser energy density is 200-400mJ / cm²  , Preferably 250-300 mJ / cm²  In addition, the substrate was heated to 300 to 500 ° C. during the laser irradiation. As the laser, a XeCl excimer laser (wavelength 308 nm) or other may be used. The silicon region 104 remained amorphous.
[0013]
Thereafter, an aluminum film having a thickness of 2000 to 5 μm, for example, 6000 mm was formed by an electron beam evaporation method, and this was patterned to form gate electrodes 106, 107, 109 and wirings 108. When aluminum was doped with scandium (Sc) in an amount of 0.05 to 0.3% by weight, generation of hillocks due to heating was suppressed. This state is shown in FIGS. 1 (A) and 2 (A). As is apparent from FIG. 2A, the gate electrode 109 and the wiring 108 are electrically connected, and the gate electrodes 106 and 107 and the gate electrode 109 and the wiring 108 are electrically independent. . Hereinafter, the former will be referred to as A series and the latter as B series.
Next, the substrate was immersed in an ethylene glycol solution of tartaric acid having a pH of approximately 7 to 1%, and anodic oxidation was performed using platinum as a cathode and the aluminum gate electrode as an anode. An anodic oxide obtained by using such a neutral solution is called a barrier type anodic oxide and is dense and has a high withstand voltage.
[0014]
At the time of anodizing, two types of anode power supply terminals that can be controlled independently were prepared and connected to terminals different from the A series and B series. In anodization, first, a constant current is continuously applied to both the A series and the B series, and the first voltage, V₁The voltage was raised to and maintained in that state for 1 hour. After that, A series voltage V₁The constant voltage is continuously applied to the B series while maintaining the second voltage V₂Increased the voltage up to. Since the two-step anodic oxidation is performed in this way, the thickness of the anodic oxide formed on the side surface and the upper surface of the gate electrode differs between the A series and the B series, and the latter is thicker. V₁Is preferably 50 to 150 V, and is 100 V here. V₂Is preferably 100 to 250 V, and is 200 V here. In this example, in the constant current state, the voltage increase rate was suitably 2 to 5 V / min. Naturally, V₁<V₂It is. As a result, anodic oxides 110 and 111 having a thickness of about 1200 mm are formed on the gate electrodes 106 and 107 of the A series, and anodic oxides 112 and 113 having a thickness of 2400 mm are formed on the gate electrode 109 and the wiring 108, respectively. It was done. (Fig. 1 (B))
[0015]
Thereafter, impurity ions (phosphorus, boron) were implanted into the island-like silicon film of each TFT by ion doping (also referred to as plasma doping) using a known CMOS technique or self-aligned impurity implantation technique. As a doping gas, phosphine (PH₃  ) And diborane (B₂  H₆  ) Was used. Dose amount is 2-8x10¹⁵cm^-2It was. As a result, N-type impurity (phosphorus) regions 114 and 116 and P-type impurity (boron) region 115 were formed. This is because NTFTs 126 and 128 and PTFT 127 are formed in the drawing.
[0016]
Further, irradiation with a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed to improve the crystallinity of the portion where the crystallinity was deteriorated by the introduction of the impurity region. Laser energy density is 150-400mJ / cm², Preferably 200 to 250 mJ / cm²  Met. Thus, the N-type impurity regions 114 and 116 and the P-type impurity region 115 are activated. The sheet resistance in these regions was 200 to 800 Ω / □. This step may be performed by RTA (rapid thermal annealing). (Fig. 1 (C), Fig. 2 (B))
[0017]
Through the above steps, the width of the offset region (high resistance region) of each TFT was determined. That is, in the two TFTs on the left side of FIG. 1, since the thickness of the anodic oxides 110 and 111 is about 1200 mm, the offset width x₁  , X₃  Is about 1000 mm in consideration of wraparound during ion doping, and in the right TFT, the thickness of the anodic oxide 113 is about 2400 mm, so the offset width x₂  Was about 2000 mm. (See Fig. 1 (D))
Offset width x of TFTs 126 and 127 for high frequency operation₁  , X₃  Is the offset width x of the NTFT 128 that requires a low off-state current.₂  Must be smaller. However, NTFT is more likely to be deteriorated by hot carriers due to reverse bias of the drain. Therefore, it is preferable to make the offset width larger than that of PTFT. That is, x₃  > X₁  It is. Further, since the NTFT 128 to which an off current is small and a high drain current is applied has a large offset width, x₂  > X₃  It is.
[0018]
Thereafter, the gate electrode and the wiring (130 in FIG. 2C) were divided to have a length necessary for the circuit. Then, a silicon oxide film having a thickness of 3000 to 10000 mm, for example, 6000 mm is formed as an interlayer insulator 117 on the entire surface by TEOS as a raw material and a plasma CVD method with oxygen, a low pressure CVD method with ozone, or an atmospheric pressure CVD method. Formed. At this time, fluorine is converted to dicarbon hexafluoride (C₂  F₆  Step coverage can be improved by adding it into silicon oxide. The substrate temperature was 150 to 400 ° C., preferably 200 to 300 ° C. Furthermore, an ITO film was deposited by sputtering, and this was patterned to form a pixel electrode 118. Then, the interlayer insulator 117 and the anodic oxide 112 of the wiring 108 were etched to form a contact hole 119. (Figure 1 (D))
[0019]
Thereafter, the interlayer insulator and the gate insulating film 105 were etched to form contact holes in the source / drain of the TFT. Although not shown in FIG. 1, when the contact holes are formed, the anodic oxides 110 and 111 are simultaneously etched to form contact holes in the gate electrodes 106 and 107. (See Fig. 2 (C))
And the wiring 120-125 of the multilayer film of titanium nitride and aluminum was formed. The wiring 124 was connected to the pixel electrode 118. A wiring 125 is connected to the gate electrodes 106 and 107 through the contact holes formed previously. Finally, silicon was hydrogenated by annealing in hydrogen at 200-300 ° C. for 0.1-2 hours. In this way, an integrated circuit was completed. (Fig. 1 (E), Fig. 2 (C))
[0020]
In this example, the step of forming the contact hole by etching the thick anodic oxide 113 and the step of forming the other contact hole were performed separately. Of course, it may be performed at the same time, but in the present example, at the expense of mass productivity, this was done because the former thickness was different from the latter in the thickness of the anodic oxide, and the thickness of 1200 mm. This is because the etching rate of the barrier type anodic oxide obtained in this example is extremely small compared to silicon oxide or the like. This is because the contact hole to the broken source and drain is significantly etched, and there is a hole in the source and drain.
[0021]
In this way, different kinds of TFTs were formed on the same substrate. That is, the two TFTs 126 and 127 on the left side of FIGS. 1 and 2 are suitable for high-speed operation because the active layer is crystalline silicon and the width of the high resistance region (offset region) is small, and the right TFT 129 has an active layer as the active layer. A TFT with a large width of the high resistance region (offset region) made of amorphous silicon and characterized by low leakage current. The same effect can be obtained even if the active layer of the TFT 128 is crystalline silicon having a lower degree of crystallization than the TFTs 127 and 128. When a monolithic active matrix is manufactured using the same process, it goes without saying that the former may be used for the driver circuit and the latter for the active matrix circuit.
[0022]
Degradation due to hot carriers is often seen in NTFT, but a driver TFT with a large channel width (this offset width is x₄  ) Is not observed so much. In addition, NTFTs of decoder circuits that require high-frequency operation, particularly shift registers, CPUs, memories, and other correction circuits (the offset width is x₃  Since the channel width must be small and the channel must be too small, the TFT 128 in the active matrix circuit (its offset width is x₂  The drain voltage is lower than that of the For this reason, x₄  <X₃  <X₂  It is required to be. PTFT offset width x₁  Since there is almost no deterioration in the driver TFT or the auxiliary circuit outside it, x₁  ≦ x₄  It is allowed to be.
[0023]
[Embodiment 2] FIGS. 3 and 4 show this embodiment. 3 is a cross-sectional view of the portion indicated by the alternate long and short dash line in FIG. First, a silicon oxide film having a thickness of 1000 to 3000 mm, for example, 2000 mm, was formed as a base oxide film 202 on a substrate (Corning 7059, 300 mm × 400 mm or 100 mm × 100 mm) 201. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further increase mass productivity, a film obtained by decomposing and depositing TEOS by plasma CVD may be used.
[0024]
Thereafter, an amorphous silicon film was deposited in an amount of 300 to 5000, preferably 500 to 1000 by plasma CVD or LPCVD, and allowed to stand in a reducing atmosphere at 550 to 600 ° C. for 24 hours for crystallization. This step may be performed by laser irradiation. Then, the silicon film crystallized in this way was patterned to form island-shaped active layer regions 203 and 204. Further, a silicon oxide film 205 having a thickness of 700 to 1500 mm was formed thereon by sputtering.
[0025]
Thereafter, an aluminum film (containing 1 wt% Si or 0.1 to 0.3 wt% Sc) having a thickness of 1000 to 3 μm, for example, 6000 mm was formed by electron beam evaporation or sputtering. A photoresist (for example, OFPR 800/30 cp, manufactured by Tokyo Ohka) was formed by spin coating. If an aluminum oxide film having a thickness of 100 to 1000 mm is formed on the entire surface of the aluminum film by anodic oxidation before the formation of the photoresist, the adhesion with the photoresist is good, By suppressing the leakage of current, it was effective in forming the porous anodic oxide only on the side surface in the subsequent anodic oxidation step. Thereafter, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form wiring portions 206 and 209 and gate electrode portions 207, 208 and 210. (Fig. 3 (A))
[0026]
The photoresist is left on these wiring and gate electrodes, and this functions as a mask for preventing anodization in the subsequent anodizing step. FIG. 4 shows how this state is viewed from above. Also in this case, as in the first embodiment, the gate electrodes 207 and 208 and the wiring 209, and the wiring 206 and the gate electrode 210 are electrically independent, and the former is referred to as A series and the latter as B series. (Fig. 4 (A))
[0027]
Of the above-described wiring and gate electrodes, only the B series is anodized through current in an electrolytic solution, and anodic oxides 211 and 212 having a thickness of 3000 to 25 μm, for example, 0.5 μm, are connected to the wiring and gate electrodes. Formed on the sides. Anodization was performed using 3 to 20% citric acid or an acidic aqueous solution such as succinic acid, phosphoric acid, chromic acid, sulfuric acid, etc., and a constant current of 5 to 30 V, for example, 8 V was applied to the gate electrode. The anodic oxide thus formed was porous. In this example, the voltage was set to 8 V in an oxalic acid solution (30 to 80 ° C.), and anodization was performed for 20 to 240 minutes. The anodic oxide thickness was controlled by anodic oxidation time and temperature. At this time, since no current was passed through the A series, no anodic oxide was formed on the gate electrodes 207 and 208 and the wiring 209. (Fig. 3 (B), Fig. 4 (B))
[0028]
Next, the mask was removed, and current was again applied to the gate electrode / wiring in the electrolytic solution. This time, an ethylene glycol solution having a pH of about 7 containing 3 to 10% tartaric acid solution, boric acid and nitric acid was used, and both the A series and B series were energized. A better oxide film was obtained when the temperature of the solution was lower than room temperature of around 10 ° C. Therefore, barrier type anodic oxides 213 to 217 were formed on the upper and side surfaces of the gate electrodes / wirings 206 to 210. The thickness of the anodic oxides 213 to 217 was proportional to the applied voltage. For example, an anodic oxide of 1200 で was formed at an applied voltage of 100V. In this example, since the voltage was increased to 100 V, the thickness of the obtained anodic oxide was 1200 mm. The thickness of the barrier type anodic oxide is arbitrary, but if it is too thin, there is a risk that aluminum will be eluted when the porous anodic oxide is etched later. .
[0029]
It should be noted that although the barrier type anodic oxide is obtained in a later step, the barrier type anodic oxide is not formed outside the porous anodic oxide. A barrier type anodic oxide is formed between the gate electrodes. (Figure 3 (C))
Thereafter, by ion doping, impurities are implanted into the TFT active layers 203 and 204 in a self-aligned manner using the gate electrode portion (that is, the gate electrode and its surrounding anodic oxide film) and the gate insulating film as a mask. / Drain) regions 218, 219, and 220 were formed. As a doping gas, phosphine (PH₃  ) And diborane (B₂  H₆  ) Was used. Dose amount is 5 × 10¹⁴~ 5x10¹⁵cm^-2The acceleration energy was 50 to 90 keV. Impurities were introduced so that the regions 218 and 220 were N-type and the region 219 was P-type. NTFT 228 is formed by region 218, PTFT 229 is formed by region 219, and NTFT 230 is formed by region 220.
[0030]
As a result, in the two TFTs 228 and 229 on the left side of the figure (these are complementary TFTs) 228 and 229, the thickness of the anodic oxides 214 and 215 on the side surfaces of the gate electrode is about 1200 mm. Width x of non-overlapping area (offset area)₁  , X₃  Was about 1000 mm in consideration of wraparound during ion doping. On the other hand, in the TFT 230 on the right side, the total thickness of the anodic oxides 212 and 217 is about 6200 mm, so the offset width x₂  Was about 6000 kg.
[0031]
Thereafter, the porous anodic oxides 211 and 213 were etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxides 211 and 213 were etched, and the etching rate was about 600 cm / min. The barrier type anodic oxides 213 to 217 and the silicon oxide film 205 remained as they were. Thereafter, irradiation with KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was performed to activate the impurity ions introduced into the active layer. (Figure 3 (E))
[0032]
Then, the gate electrode / wiring was divided into the required size and shape. (FIG. 4C).
Further, a silicon oxide film having a thickness of 6000 mm was formed as an interlayer insulator 221 over the entire surface by a CVD method. Next, an ITO film having a thickness of 800 mm was formed by sputtering, and this was patterned to form a pixel electrode 222. Then, the interlayer insulator 221 and the gate insulating film 205 are etched to form contact holes in the source / drain of the TFT, and at the same time, the interlayer insulator 221 and the anodic oxides 213 to 217 are etched to form gate electrodes / wirings. A contact hole was formed. In this embodiment, unlike the first embodiment, since the anodic oxide has almost the same thickness in both the A series and the B series, they can be etched at the same time. Therefore, the photolithography process is performed in the first embodiment. One less than the case of. Finally, aluminum wiring / electrodes 223 to 226 were formed, and hydrogen annealing was performed at 200 to 400 ° C.
[0033]
Note that the wiring 223 connects the wiring 206 and the source of the N-channel TFT of the complementary TFT, and the wiring 225 connects the source of the P-channel TFT of the complementary TFT and the wiring 209. The wiring 224 (that is, 226) connects the output terminal of the complementary TFT (that is, the drain of the N-channel TFT and the P-channel TFT) and the drain of the right TFT. Further, the wiring 227 connects the drain of the right TFT and the pixel electrode 222. Thus, an integrated circuit having TFTs was completed. (Fig. 3 (F))
[0034]
In particular, in the A series, as shown in the embodiment, the driver is driven with a large current, so that PTFT (high resistance region width x₁  ), NTFT (high resistance region width x₄  )) With little deterioration. In addition, the decoder, CPU, shift register, memory and other driving circuits have low power consumption and high frequency operation, so that the channel width and channel length are both small, and deterioration due to hot carriers is likely to occur. The width x of the high resistance region of the NTFT used in these circuits₃  Is the width x of the high resistance region of the PTFT₁  Needs to be greater than. Also, NTFT (high resistance region width x₂  )), Since the required mobility is small, deterioration is very likely to occur. As a result, in order to improve reliability, x₂  > X₃  > X₄  ≧ x₁  It is required to be. For example, x₂  Is 0.5-1 μm, x₃  Is 0.2 to 0.3 μm, x₄  0 to 0.2 μm, x₁  Is 0 to 0.1 μm. In this way, the shift register could be operated at 1 to 50 MHz.
In the present embodiment, the effect of suppressing the leakage current when the offset width of the TFT for controlling the pixel electrode (right TFT) is sufficiently larger than that of the first embodiment is great.
[0035]
[Reference exampleFigure 5 shows the bookreferenceAn example is shown. BookreferenceThe example relates to a monolithic active matrix liquid crystal display. The left side of the figure shows the complementary TFT of the driver circuit, and the right side shows the pixel control TFT of the active matrix circuit. First, a silicon oxide film having a thickness of 2000 mm was formed as a base oxide film 302 on a substrate (Corning 7059, 300 mm × 400 mm) 301. As a method for forming this oxide film, a film decomposed and deposited by sputtering or plasma CVD in an oxygen atmosphere may be used.
[0036]
Thereafter, an amorphous silicon film was deposited by plasma CVD or LPCVD to a thickness of 300 to 5000, preferably 500 to 1000, and left in a reducing atmosphere at 550 to 600 ° C. for 24 hours for crystallization. Then, the silicon film crystallized in this way was patterned to form island-like active layer regions 303 and 304. Further, a silicon oxide film 205 having a thickness of 700 to 1500 mm was formed thereon by sputtering.
[0037]
Thereafter, an aluminum (containing 0.1 to 0.3 wt% Sc) film having a thickness of 1000 to 3 μm, for example, 6000 mm was formed by a sputtering method. Then, a photoresist was formed on the aluminum film by a spin coating method in the same manner as in Example 2 (see FIGS. 3A to 3C). Before the formation of the photoresist, an aluminum oxide film having a thickness of 100 to 1000 mm was formed on the aluminum surface by an anodic oxidation method. Thereafter, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form gate electrodes 306, 307, 308 and wirings 309. The gate electrode 306, the gate electrode 307, and the gate electrode 308 are electrically independent, and the gate electrode 308 and the wiring 309 are electrically connected.
[0038]
Further, this was anodized through an electric current in the electrolytic solution to form an anodic oxide having a thickness of 3000 to 25 μm. Anodization was performed using an acidic aqueous solution of 3 to 20% citric acid or succinic acid, phosphoric acid, chromic acid, sulfuric acid or the like, and a constant current of 5 to 30 V was applied to the gate electrode. The anodic oxide thus obtained is porous. BookreferenceIn the example, the voltage was set to 8 V in an oxalic acid solution (30 ° C.) and anodization was performed for 20 to 140 minutes. The thickness of the anodic oxide is controlled by the anodic oxidation time. The gate electrodes 306 and 307 are formed with a thin anodic oxide of 500 to 2000 mm, for example 1000 mm, and the gate electrode 308 and the wiring 309 are formed with 3000 to 9000 mm, For example, a thick anodic oxide of 5000 mm was formed.
[0039]
Next, the mask was removed, and a current was applied to the gate electrode again in the electrolytic solution. This time, an ethylene glycol solution having a pH of about 7 containing 3 to 10% tartaric acid, boric acid and nitric acid was used. Also this timeIsElectrode306, 308·wiring309The same voltage was applied to. For this reason,Electrode306, 308·wiring309A barrier type anodic oxide was formed on the top and side surfaces of the film. BookreferenceIn the example, the thickness of the barrier type anodic oxide was 1000 mm. (Fig. 5 (A))
[0040]
Thereafter, the silicon oxide film 305 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selection ratio between silicon and silicon oxide. For example, CF as an etching gas₄  , The anodic oxide is not etched, that is, the gate electrodes 306, 307, 308 and the silicon oxide film 305 existing below the wiring 313 are not etched, and the gate insulating films 310, 311, 312, The insulating film 313 remained. (Fig. 5 (B))
[0041]
Thereafter, the porous anodic oxide was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. Then, by ion doping, impurities were implanted into the TFT active layers 303 and 304 in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film as a mask. At this time, various combinations of impurity regions are conceivable depending on the acceleration voltage and dose of ions. For example, the acceleration voltage is set as high as 50 to 90 kV, and the dose amount is set to 1 × 10¹³~ 5x10¹⁴cm^-2In the regions 314 to 316, most impurity ions pass through the active layer and show the maximum concentration in the base film. Therefore, the regions 314 to 316 are extremely low concentration impurity regions. On the other hand, in the regions 317 to 319 where the gate insulating films 310 to 312 are present, high-speed ions are decelerated by the gate insulating film, so that the impurity concentration is maximized and a low-concentration impurity region can be formed. .
[0042]
Conversely, the acceleration voltage is set to a low value of 5 to 30 kV, and the dose amount is set to 5 × 10.¹⁴~ 5x10¹⁵cm^-2If so, a large amount of impurity ions are implanted into the regions 314 to 316 to become high-concentration impurity regions. On the other hand, in the regions 317 to 319 where the gate insulating films 310 to 312 are present, low-speed ions are prevented by the gate insulating film, and the amount of impurity ions implanted is low, so that a low concentration impurity region can be formed. . Thus, regardless of which method is used, the regions 317 to 319 become low-concentration impurity regions.referenceIn the example, any method may be adopted.
In this way, ion doping is performed to form N-type low-concentration impurity regions 317 and 319 and a P-type low-concentration impurity region 318, and then irradiation with a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is performed. The impurity ions introduced into the active layer were activated. For this step, RTP (rapid thermal process) may be used. (Fig. 5 (C))
[0043]
As a result, the width of the high resistance region (that is, the low concentration region and the offset region) was different in each TFT. That is, in the N-channel TFT of the driver circuit, the width x of the high resistance region₁  Is 2000 mm obtained by adding the offset width of 1000 mm to the width of the low-concentration region of 1000 mm.₂  Is 1000 mm, which is only the width of the low-concentration region. In a pixel-controlled TFT, x₃  Was 6000 mm obtained by adding the width of 5000 mm in the low concentration region to the offset width of 1000 mm.
[0044]
Further, an appropriate metal such as titanium, nickel, molybdenum, tungsten, platinum, palladium, or the like, for example, a titanium film 320 having a thickness of 50 to 500 mm was formed on the entire surface by sputtering. As a result, the metal film (here, titanium film) 320 was formed in close contact with the high concentration (or extremely low concentration) impurity regions 314 to 316. (Fig. 5 (D))
[0045]
Then, irradiation with KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) causes the metal film (here, titanium) and the active layer silicon to react to form regions 330 to 332 of metal silicide (here, titanium silicide). did. Laser energy density is 200-400mJ / cm², Preferably 250-300 mJ / cm²Was appropriate. Further, when the substrate was heated to 200 to 500 ° C. during laser irradiation, it was possible to suppress the peeling of the titanium film.
BookreferenceIn the example, an excimer laser is used as described above, but it goes without saying that other lasers may be used. However, when using a laser, a pulsed laser is preferable. Since the continuous wave laser has a long irradiation time, there is a danger that the irradiated object is peeled off due to the expansion of the irradiated object due to the heat.
[0046]
As for the pulse laser, various ultraviolet light lasers using infrared light such as Nd: YAG laser (preferably Q switch pulse oscillation) and excimers such as visible light such as KrF, XeCl and ArF are used. Although it can be used, when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Moreover, you may irradiate a laser beam from the board | substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.
[0047]
The annealing may be performed by lamp annealing by irradiation with visible light or near infrared light. When lamp annealing is performed, lamp irradiation is performed for several minutes at 600 ° C. and for several tens of seconds at 1000 ° C. so that the surface to be irradiated has a temperature of about 600 to 1000 ° C. Annealing with near-infrared (for example, 1.2 μm infrared) selectively absorbs near-infrared light into the silicon semiconductor, does not heat the glass substrate so much, and shortens the irradiation time for one time. It is convenient in use because it can suppress heating.
[0048]
Thereafter, the unreacted titanium film was etched with an etching solution in which hydrogen peroxide solution, ammonia and water were mixed at a ratio of 5: 2: 2. The titanium film other than the part in contact with the exposed active layer (for example, the titanium film existing on the gate insulating film or the anodic oxide film) remains in the metal state as it is, but can be removed by this etching. On the other hand, titanium silicides 330 to 332, which are metal silicides, were not etched and could remain. BookreferenceIn the example, the sheet resistance of the silicide regions 330 to 332 was 10 to 50Ω / □. On the other hand, in the low concentration impurity regions 317 to 319, it was 10 to 100 kΩ / □.
[0049]
Then, a silicon nitride film 332 having a thickness of 500 to 3000 mm, for example, 1000 mm, was formed on the NTFT 337 of the active matrix circuit. In general, a silicon nitride film has a property of capturing holes. Therefore, the silicon nitride film 322 is effective in preventing electrons from being charged up by hot electrons in the gate insulating film due to hot carrier injection, particularly in applications where hot carriers are likely to be generated, such as TFTs in active matrix circuits. It was. However, in the case of PTFT, the reverse effect is obtained, so it is preferable not to form a silicon nitride film in the portion where the complementary circuit exists. BookreferenceIn the example, the silicon nitride film is left only in the active matrix circuit (on the right side of the figure) for the above reason.
[0050]
Further, a silicon oxide film having a thickness of 2000 to 1 μm, for example, 5000 μm, was formed as an interlayer insulator 321 on the entire surface by a CVD method. Then, a hole 324 was formed in the wiring 309 and the silicon nitride film 322 was exposed. Then, an ITO film was formed by sputtering, and this was patterned and etched to form a pixel electrode 323. The pixel electrode 323 forms a capacitance with the wiring 309 in the hole 324 with the barrier type anodic oxide (1000 Å) and the silicon nitride film (1000 Å) interposed therebetween. At this time, both the anodic oxide and silicon nitride have a large dielectric constant and are thin, so that a large capacity can be obtained with a small area. This capacitor is used as a so-called holding capacitor inserted in parallel with a capacitor formed by the pixels of the active matrix and the counter electrode. That is, the wiring 309 is kept at the same potential as the counter electrode.
[0051]
Thereafter, the interlayer insulating film 321 is etched to form contact holes in the source / drain and gate electrodes of the TFT. Formed. (Fig. 5 (E))
BookreferenceIn the example, the NTFT 337 constituting the active matrix circuit, the decoder, the CPU, the memory, the other high frequency, low power consumption NTFT, the high power driver NTFT, and the PTFT high resistance region width values are the same as in the second embodiment. It was. Thus, it has been shown that in a thin film integrated circuit having a monolithic type electro-optical device, the width of the high resistance region is optimized by the N-channel TFT and the P-channel TFT. FIG. 6 shows a block diagram of an electro-optical system using an integrated circuit in which a display, a CPU, and a memory are mounted on a single glass substrate. Example 1And 2 and reference examplesOnly the active matrix circuit and the X and Y decoder / driver portions are mainly shown.And 2 and reference examplesIt can be easily imagined that it is possible to construct more advanced circuits and systems by developing the above.
[0052]
Here, the input port reads an externally input signal and converts it into an image signal, and the correction memory is a memory specific to the panel for correcting the input signal etc. in accordance with the characteristics of the active matrix panel. is there. In particular, this correction memory has information specific to each pixel as a non-volatile memory, and is used for individual correction. That is, if a pixel of the electro-optical device has a point defect, a signal corrected accordingly is sent to the pixels around the point to cover the point defect and make the defect inconspicuous. Alternatively, when a pixel is darker than surrounding pixels, a larger signal is sent to the pixel so that the surrounding pixels have the same brightness.
The CPU and the memory are the same as those of an ordinary computer. In particular, the memory has an image memory corresponding to each pixel as a RAM. Moreover, the backlight which irradiates a board | substrate from a back surface can also be changed according to image information.
[0053]
Then, in order to obtain the width of the high resistance region suitable for each of these circuits, it is only necessary to form 3 to 10 lines of wiring and individually change the anodizing conditions. Typically, in an active matrix circuit, the channel length is 10 μm, and the width of the high resistance region is 0.4 to 1 μm, for example, 0.6 μm. In the driver, the channel length is 8 μm, the channel width is 200 μm, and the high resistance region has a width of 0.2 to 0.3 μm, for example, 0.25 μm. Similarly, in the P-channel TFT, the channel length is 5 μm, the channel width is 500 μm, and the width of the high resistance region is 0 to 0.2 μm, for example, 0.1 μm. In the decoder, the channel length is 8 μm, the channel width is 10 μm, and the width of the high resistance region is 0.3 to 0.4 μm, for example, 0.35 μm. Similarly, in the P-channel TFT, the channel length is 5 μm, the channel width is 10 μm, and the width of the high resistance region is 0 to 0.2 μm, for example, 0.1 μm. Further, the width of the high resistance region may be optimized for the CPU, input port, correction memory, NTFT and PTFT of the memory in FIG. 6 in the same manner as the decoder for high frequency operation and low power consumption. Thus, the electro-optical device 64 can be formed on the same substrate having an insulating surface.
[0054]
The present invention is characterized in that the width of the high resistance region can be varied to 2 to 4 types or more depending on the application. Further, this region does not have to be the same material and the same conductivity type as the channel formation region. That is, it is also possible to form a high resistance region by adding a small amount of N-type impurity in NTFT, a small amount of P-type impurity in PTFT, and selectively adding carbon, oxygen, nitrogen, or the like. This is effective in eliminating the trade-off between deterioration and reliability, frequency characteristics, and off current.
[0055]
【The invention's effect】
According to the present invention, a TFT having a high resistance region having an optimum width according to characteristics and reliability required for each TFT can be manufactured on the same substrate. As a result, an unprecedented degree of freedom can be obtained, and a more highly integrated circuit can be configured. As described above, the present invention has a great industrial value. Particularly, a TFT group is formed on a large-area substrate, and this is used as an active matrix, a driver circuit, a CPU, and a memory to form an electro-optical system. In the case of a board ultra-thin personal computer or portable terminal, the field of use can be expanded without limit. In addition, the electro-optic system is intelligent and has enough qualities to form a new industry by combining with other single crystal semiconductor CPUs, computer systems, and image processing systems.
[Brief description of the drawings]
FIG. 1 shows a method for manufacturing a TFT circuit. (Cross section, Example 1)
FIG. 2 illustrates a method for manufacturing a TFT circuit. (Top view, Example 1)
FIG. 3 illustrates a method for manufacturing a TFT circuit. (Cross section, Example 2)
FIG. 4 illustrates a method for manufacturing a TFT circuit. (Top view, Example 2)
FIG. 5 illustrates a method for manufacturing a TFT circuit. (Cross section,Reference example)
FIG. 6 shows an example of a block diagram of an integrated circuit.
[Explanation of symbols]
101 substrate
102 Underlying insulating film
103, 104 Island-like semiconductor region (silicon)
105 Gate insulating film (silicon oxide)
106-109 Gate electrode / wiring (aluminum)
110-113 Anodic oxide (aluminum oxide)
114, 116 N-type impurity region
115 P-type impurity region
117 Interlayer insulator (silicon oxide)
118 Pixel electrode (ITO)
119 Contact hole
120-124 Metal wiring (titanium nitride / aluminum)

Claims (5)

An active matrix circuit having an N-type first thin film transistor connected to the pixel electrode;
An active matrix for driving the first thin film transistor, wherein a driver circuit having an N-type second thin film transistor and a P-type third thin film transistor constituting a complementary thin film transistor is provided on the same substrate. Type display device,
The first to third thin film transistors are respectively
Includes a semiconductor film, and the semiconductor film gate insulating contact with the film, a gate electrode in contact on the gate insulating film,
Wherein the semiconductor film, a source region, a drain region, a channel forming region between the source region and the drain region, the offset between between and the drain region and the channel forming region between the source region and the channel forming region A high resistance region is provided,
The widths of the high resistance regions of the second and third thin film transistors in the channel width direction are equal to each other and larger than the width of the high resistance regions of the first thin film transistors in the channel width direction,
The width of the high resistance region of the first and second thin film transistors in the channel length direction is larger than the width of the high resistance region of the third thin film transistor in the channel length direction, and the height of the first thin film transistor is high. An active matrix display device, wherein the width of the resistance region in the channel length direction is larger than the width of the high resistance region of the second thin film transistor in the channel length direction. An active matrix circuit having an N-type first thin film transistor connected to the pixel electrode;
An active matrix for driving the first thin film transistor, wherein a driver circuit having an N-type second thin film transistor and a P-type third thin film transistor constituting a complementary thin film transistor is provided on the same substrate. Type display device,
The first to third thin film transistors are respectively
Includes a semiconductor film, and the semiconductor film gate insulating contact with the film, a gate electrode in contact on the gate insulating film,
Wherein the semiconductor film, a source region, a drain region, a channel forming region between the source region and the drain region are provided,
Wherein the first and the semiconductor film of the second thin film transistor, the high resistance region consisting of an offset region between and between the drain region and the channel forming region between the source region and the channel forming region is provided, and wherein The width in the channel length direction of the high resistance region of the first thin film transistor is larger than the width in the channel length direction of the high resistance region of the second thin film transistor,
The channel widths of the second and third thin film transistors are equal to each other,
The width in the channel width direction of the high resistance region of the second thin film transistor is larger than the width in the channel width direction of the high resistance region of the first thin film transistor,
An active matrix display device , wherein the third thin film transistor is not provided with a high-resistance region, so that the channel formation region is in contact with the source region and the drain region in the third thin film transistor. . 3. The active matrix display device according to claim 1, wherein a width in a channel length direction of the high resistance region of the first thin film transistor is 0.4 to 1 μm. 4. The active matrix display device according to claim 1, wherein a width of the high resistance region of the second thin film transistor in a channel length direction is 0.2 to 0.3 μm. 5. In any one of Claims 1 thru | or 4,
An active matrix display device, wherein the semiconductor film of the first to third thin film transistors is a crystalline silicon film.

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