JP2002050637A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, having an N-channel type thin-film transistor and a P-channel type thin-film transistor, which is connected to the N-channel type thin-film transistor. SOLUTION: This semiconductor device has the N-channel type thin-film transistor and the P-channel type thin-film transistor connected to the N-channel type thin-film transistor. In this case, the N-channel type thin-film transistor is to have a lightly doped region of a dose of 1×1013 to 5×1014 atoms/cm2 between a channel-formatting region, and source and drain regions, and the P-channel type thin-film transistor is to not have the lightly doped region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating substrate (referred to herein as an entire object having an insulating surface, and unless otherwise specified, not only insulating materials such as glass but also materials such as semiconductors and metals). Which also means that an insulating layer is formed on the surface)
The present invention relates to an integrated circuit in which a thin-film insulated gate semiconductor device (also referred to as a thin film transistor or TFT) is formed and a method for forming the integrated circuit. The semiconductor integrated circuit according to the present invention includes an active matrix circuit such as a liquid crystal display, a peripheral drive circuit thereof, a drive circuit such as an image sensor, or an SOI integrated circuit or a conventional semiconductor integrated circuit (a microprocessor, a microcontroller, a microcomputer, or a semiconductor). Memory, etc.).

[0002]

2. Description of the Related Art Conventionally, when circuits such as an active matrix type liquid crystal display device and an image sensor are formed on a glass substrate, a thin film transistor (TF) is used.
A configuration in which T) is integrated and used is widely known. In this case, a method of forming a first-layer wiring including a gate electrode first, forming an interlayer insulator, and then forming a second-layer wiring is generally used. In some cases, third and fourth wiring layers may be formed.

[0003]

The biggest problem in such an integrated circuit of the thin film transistor is that the wiring on the extension of the gate electrode (gate wiring) and the wiring at the intersection of the wiring of the second layer (crossover portion) are not the same. The wiring of the layer was disconnected (also called step disconnection). This is because it is difficult to form an interlayer insulator on the gate electrode and wiring with good step coverage and to further planarize it.

FIG. 4 shows a state of a disconnection failure often seen in a conventional TFT integrated circuit. TF on the substrate
A T region 401 and a gate wiring 402 are provided, and an interlayer insulator 403 is formed to cover them. However, if the edge of the gate wiring 402 is steep, the interlayer insulator 403 cannot sufficiently cover the gate wiring. Then, when the second-layer wirings 404 and 405 are formed in such a state, the second-layer wiring is disconnected (stepped off) as shown in the drawing at the crossover portion 406 of the gate wiring.

In order to prevent such disconnection, it is necessary to increase the thickness of the second-layer wiring. For example, it has been desired to make the thickness about twice as large as the gate wiring. However, this means that the concavities and convexities of the integrated circuit are further increased, and when it is necessary to further overlap the wiring thereon, the disconnection due to the thickness of the second layer wiring has to be considered. . In addition, when a circuit such as a liquid crystal display in which unevenness of an integrated circuit is not preferred is formed, it has been practically impossible to increase the thickness of the second layer wiring. In an integrated circuit, if even one step is present, the entire circuit becomes defective. Therefore, how to reduce the step is an important issue. An object of the present invention is to provide a method for reducing such a disconnection failure, and to increase the yield of integrated circuits.

[0006]

In the present invention, an oxide film is formed by oxidizing a gate electrode on at least the upper surface of the gate electrode / wiring by an anodic oxidation method, and furthermore, on the side surface of the gate electrode / wiring. After a substantially triangular insulator (sidewall) is formed by anisotropic etching, an interlayer insulator is deposited, and a second-layer wiring is formed. The oxide film formed by the anodic oxidation method needs to be harder to be etched than the material forming the sidewall formed later, and when the sidewall is formed of silicon oxide, aluminum oxide is used. , Tantalum oxide, titanium oxide, molybdenum oxide, tungsten oxide and the like are preferable. These materials have an extremely low etching rate under conditions for etching silicon oxide by a dry etching method, that is, etching using a fluorine-based etching gas (for example, NF ₃ or SF ₆ ).

A first method of practicing the present invention is as follows. First, an island-shaped semiconductor layer is formed. Further, a film serving as a gate insulating film is formed thereon. Further, a gate electrode and a wiring are formed. At this time, it is necessary that the gate electrode and the wiring are formed of a material to be anodized, and that a film obtained as a result of the anodization is harder to be etched than the side wall as described above. Thereafter, a positive voltage is applied to the gate electrode / wiring in a substantially neutral electrolytic solution to form an anodic oxide film on at least the upper surface of the gate electrode / wiring. This step may be performed by a vapor phase anodic oxidation method. This is the first stage.

Thereafter, an insulating film is formed to cover the gate electrode / wiring and the anodic oxide film around the gate electrode / wiring. In this film formation, the coatability is important, and the thickness is preferably 1/3 to 2 times the height of the gate electrode / wiring. For this purpose, plasma CVD, low pressure CVD,
A chemical vapor deposition (CVD) method such as an atmospheric pressure CVD method is preferable. Then, the insulator thus formed is preferentially etched in a direction substantially perpendicular to the substrate by anisotropic etching. The end of the etching is such that the insulating film in the flat portion is etched, and the etching may be further advanced to such an extent that the gate insulating film thereunder is etched. As a result, the gate electrode
At the stepped portion such as the side surface of the wiring, the insulator film is originally thick, so that the insulator (sidewall) of the substantially triangular castle is left behind. This is the second stage.

Then, after forming an interlayer insulator, TF
A contact hole is formed in one or both of the source / drain of T, and a second-layer wiring is formed. This is the third stage. In the above steps, there are various cases in which doping is performed to form the source / drain of the TFT. For example, when only an N-channel TFT is formed on a substrate, a relatively high concentration of N-type impurity is applied between the gate electrode and the anodic oxide film around the gate electrode between the first and second steps. May be introduced into the semiconductor layer in a self-aligned manner. In this case, if the anodic oxide coating was on the side of the gate electrode,
It is a so-called offset gate type in which the source / drain and the gate electrode are separated by the thickness of the anodic oxide. However, in the following description, such a case will be referred to as a normal TFT.

Similarly, when an N-channel TFT is formed, a TF having a low concentration drain (LDD) is used.
In the case of forming a T (LDD type TFT), a relatively low concentration impurity is introduced into the semiconductor layer between the first and second stages, and then between the second and third stages. High-concentration N-type impurities may be introduced into the semiconductor layer in a self-aligned manner using the gate electrode and the sidewalls as a mask. In this case, the width of the LDD is substantially the same as the width of the sidewall. The same applies to the case where only a P-channel TFT is formed on a substrate.

A so-called complementary circuit (CMOS) in which an N-channel TFT and a P-channel TFT are mixed on a substrate.
The formation of the circuit) can be similarly performed using the above-described method. N-channel TFT and P-channel TF
In the case where both T are composed of normal TFTs or both are composed of LDD type TFTs, the impurity is introduced by the method of forming only one of the above-mentioned N-channel type or P-channel type TFT on the substrate. The impurity may be introduced for each of the N-type impurity and the P-type impurity.

For example, when an N-channel TFT requiring hot carrier countermeasures is an LDD type and a P-channel TFT which does not require such a countermeasure is a normal TFT, the step of introducing impurities is somewhat special. In that case, the first
Between the stage and the second stage, a relatively low concentration of N-type impurities is introduced into the semiconductor layer. This is the first impurity introduction. In this case, an N-type impurity may be introduced into the semiconductor layer of the P-channel TFT. Further, a high-concentration P-type impurity is introduced only into the semiconductor layer of the P-channel TFT by masking the semiconductor layer of the N-channel TFT. This is the second impurity introduction. By introducing the impurity, even if the N-type impurity is present in the semiconductor layer of the P-channel TFT by the introduction of the N-type impurity, a higher concentration of the P-channel type impurity is introduced. Is P-type. Naturally, as compared with the impurity concentration introduced in the first impurity introduction, that of the second impurity introduction is higher, preferably 1 to 3 orders of magnitude.

Finally, a relatively high concentration of N-type impurities is introduced between the second and third stages to form the source / drain of the N-channel TFT. This is the third impurity introduction. In this case, a P-channel TFT
In order to prevent the introduction of N-type impurities into the mask, impurities may be introduced by masking, or masking may not be particularly performed. However, in the latter case, the concentration of the N-type impurity to be introduced needs to be lower than the concentration of the P-type impurity introduced by the introduction of the second impurity.
Is 1/10 to 2/3 of the concentration of the P-type impurity for impurity introduction. As a result, the N-type impurity is also introduced into the region of the P-channel TFT, but the P-type is maintained because the impurity concentration is lower than the concentration of the P-type impurity introduced before.

[Operation] In the present invention, the step coverage of the interlayer insulating material at the portion where the gate wiring runs over is improved due to the presence of the sidewall, and the disconnection of the second wiring can be reduced. Further, as described above, an LDD structure can be obtained by using the sidewall. In the present invention, the presence of the anodic oxide coating is important. In the second stage, anisotropic etching is performed to form a sidewall. However, it is difficult to control the plasma on the insulating surface, and variations in etching in the substrate have been inevitable. If no anodic oxide is formed on the upper surface of the gate electrode, the gate electrode may be severely etched in some places even in the same substrate. If an anodic oxide coating is present, the etching stops and the gate electrode is protected. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0015]

[Embodiment 1] FIG. 1 shows this embodiment. First, a substrate (Corning 7059, 300 mm × 400 m
m or 100 mm × 100 mm) 101 as a base oxide film 102 with a thickness of 1000 to 5000
A silicon oxide film of 2000 mm was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further improve mass productivity, TEOS may be formed by decomposition and deposition by plasma CVD. Also,
The silicon oxide film thus formed may be annealed at 400 to 650 ° C.

Thereafter, an amorphous silicon film is formed in a thickness of 300 to 500 by plasma CVD or LPCVD.
0 °, preferably 400-1000 °, for example 500
Å Deposit and put it in a reducing atmosphere at 550-600 ° C for 8
It was left to crystallize for 24 hours. In that case, crystallization may be promoted by adding a trace amount of a metal element such as nickel which promotes crystallization. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner was etched to form the island-shaped region 103. Further, a thickness of 700 to 1500 °, for example, 1200 ° is formed thereon by a plasma CVD method.
Of silicon oxide film 104 was formed.

Thereafter, an aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc (scandium)) film having a thickness of 1000 to 3 μm, for example, 5000 ° is formed by a sputtering method. By etching, a gate electrode 105 and a gate wiring 106 were formed. (FIG. 1 (A)) Then, anodization was performed on the gate electrode 105 and the gate electrode 106 through an electric current in an electrolytic solution to form anodic oxides 107 and 108 having a thickness of 500 to 2500 °, for example, 2000 °. The electrolytic solution used was prepared by diluting L-tartaric acid with ethylene glycol at a concentration of 5%, and adjusting the pH to 7.0 ± 0.2 using ammonia. The substrate 101 is immersed in the solution, the + side of the constant current source is connected to the gate wiring on the substrate, the platinum electrode is connected to the-side, and a voltage is applied at a constant current of 20 mA, and reaches 150 V. Oxidation was continued until complete. further,
Oxidation was continued at a constant voltage of 150 V until 0.1 mA or less was applied. As a result, an aluminum oxide film having a thickness of 2000 mm was obtained.

Thereafter, impurities (here, phosphorus) are implanted into the island-like silicon film 103 in a self-aligned manner by using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) as a mask by ion doping. As shown in FIG. 1B, a low-concentration impurity region (LDD) 109 was formed.
The dose is 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² , the acceleration voltage is 10 to 90 kV, for example, the dose is 5 × 10
¹³ atoms / cm ² and the acceleration voltage were 80 kV. (Figure 1
(B))

Then, a silicon oxide film 110 was deposited by a plasma CVD method. Here, the source gas is TEO
S and oxygen, or monosilane and nitrous oxide were used.
The optimum value of the thickness of the silicon oxide film 110 varies depending on the height of the gate electrode and the wiring. For example, as in this embodiment, the height of the gate electrode / wiring is about 60 including the anodic oxide film.
In the case of 00Å, 1/3 to 2 times that of 2000Å
1.2 μm is preferable, and here, it was 6000 °.
In this film forming process, it is required that both the uniformity of the film thickness in the flat portion and the step coverage be good. As a result, the thickness of the silicon oxide film on the side surface of the gate electrode / wiring is increased by the amount indicated by the dotted line in FIG. (Fig. 1 (C))

Next, this silicon oxide film 1 is subjected to anisotropic dry etching by a known RIE method.
08 was performed. This etching is completed when the etching reaches the gate insulating film 105. Regarding the end point of such etching, for example,
The etching rate of the gate insulating film 105 can be controlled by making it smaller than that of the silicon oxide film 110. Through the above steps, substantially triangular insulators (sidewalls) 111 and 112 remain on the side surfaces of the gate electrode and wiring. (Fig. 1 (D))

Thereafter, phosphorus was introduced again by the ion doping method. The dose in this case is shown in FIG.
Is preferably 1 to 3 digits larger than the dose in the step. In this embodiment, the dose is set to 2 × 10 ¹⁵ atoms / cm ^{2, which} is 40 times the dose of the first phosphorus doping. Acceleration voltage is 80kV
And As a result, a region (source / drain) 114 into which a high concentration of phosphorus was introduced was formed, and a low concentration region (LDD) 113 was left below the sidewall.
(FIG. 1 (E))

Further, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) activated the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , and preferably 250 to 300 mJ / cm ² . In this embodiment, since aluminum is used for the gate electrode and wiring, there is a problem in terms of heat resistance, and it is difficult to carry out the process. However, thermal annealing may be performed instead of laser irradiation.

Finally, as an interlayer insulator 115 on the entire surface,
A silicon oxide film was formed to a thickness of 5000 ° by the CVD method. Then, contact holes are formed in the source / drain of the TFT, and the aluminum wiring / electrode 11 of the second layer is formed.
6, 117 were formed. The thickness of the aluminum wiring was 4000 to 6000 °, almost the same as the gate electrode and wiring. Through the above steps, a TFT having an N-channel LDD was completed. To activate the impurity region,
Further, hydrogen annealing may be performed at 200 to 400 ° C. In the second-layer wiring 117, the step at the portion over the gate wiring 106 is moderated by the presence of the sidewall 112, so that the thickness of the second-layer wiring is almost the same as that of the gate electrode / wiring. Nevertheless, almost no break was observed. (FIG. 1 (F))

As for the thickness of the second-layer wiring, the thickness of the gate electrode / wiring was determined to be x
[Å] When y ≧ x-1000 [Å] where y is the thickness of the second layer wiring, there was no noticeable disconnection. The smaller the value of y is, the more preferable it is. In particular, in the case of a circuit which is required to have less unevenness on the substrate surface such as an active matrix circuit of a liquid crystal display, x-1000 [Å] ≦ y ≦ x + 1000 [Å] Was found to be appropriate.

Embodiment 2 FIG. 2 shows this embodiment. The present embodiment relates to a so-called monolithic type active matrix circuit in which an active matrix circuit and its driving circuit are simultaneously manufactured on the same substrate. In this embodiment, a P-channel TFT is used as a switching element of the active optics circuit, and a complementary circuit composed of an N-channel TFT and a P-channel TFT is used as a driving circuit. The left side of FIG. 2 shows N
A manufacturing process cross-sectional view of a channel TFT is shown, and a manufacturing process cross-sectional view of a P-channel TFT used for a drive circuit and an active matrix circuit is shown on the right side of the drawing. P for switching element of active matrix circuit
The reason why a channel type TFT is used is that leakage current (also referred to as off-state current) is small.

First, a substrate (Corning 7059) 201
As in the first embodiment, the base oxide film 202, the island-shaped silicon semiconductor region, and the silicon oxide film 2 functioning as the gate oxide film
03 was formed, and gate electrodes 204 and 205 were formed using an aluminum film (thickness 5000 °). Thereafter, anodic oxide having a thickness of 2000 ° was formed around the gate electrode (side surface and upper surface) by anodic oxidation in the same manner as in Example 1.
Then, phosphorus was implanted by ion doping using the gate electrode portion as a mask to form low-concentration N-type impurity regions 206 and 207. The dose was 1 × 10 ¹³ atoms / cm ² .

Further, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) activated the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , and preferably 250 to 300 mJ / cm ² . (FIG. 2A) Thereafter, the region of the N-channel TFT is formed by photoresist 2
08, and in this state, high concentration boron was doped by an ion doping method. The dose was 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 65 kV. As a result, the impurity region 207 which became weak N-type by the doping with phosphorus was inverted to a strong P-type, and became a P-type impurity region 209. Thereafter, the impurity was activated again by laser irradiation. (Figure 2
(B) In the present embodiment, high-concentration boron partial selective doping is performed after low-concentration phosphorus overall doping, but this step may be reversed.

After removing the photoresist mask 208, the thickness is 4000 to 8000 by plasma CVD.
The silicon oxide film 210 of Å was deposited. (FIG. 2 (C)) Then, similarly to the first embodiment, by anisotropic etching,
Silicon oxide sidewalls 211 on the side surfaces of the gate electrode,
212 was formed. (FIG. 2D) Thereafter, phosphorus was introduced again by an ion doping method. In this case, the dose is preferably 1 to 3 digits larger than the dose in the step of FIG. 2A, and 1/10 to 2/3 of the dose in the step of FIG. In this embodiment, 2 × 10 ¹⁵ , which is 200 times the dose of the first phosphorus doping, is used.
Atoms / cm ² . However, this is 40% of the boron dose in the step of FIG. Acceleration voltage is 80k
V. As a result, a region (source / drain) 213 into which high-concentration phosphorus was introduced was formed, and a low-concentration impurity region (LDD) 214 was left under the sidewall.

Further, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) activated the doped impurities. The energy density of the laser was 200 to 400 mJ / cm ² , and preferably 250 to 300 mJ / cm ² . On the other hand, the region of the P-channel TFT (the right side in the figure) was also doped with phosphorus, but remained P-type because the concentration of boron previously doped was 2.5 times that of phosphorus. Apparently, there appear to be two types of P-type regions of the P-channel TFT, a region 216 below the sidewall and a region 215 outside the region 216 (opposite to the channel forming region), but from the viewpoint of electrical characteristics. There was no significant difference between the two. (FIG. 2 (E))

Finally, as shown in FIG. 2F, a silicon oxide film having a thickness of 3000 .ANG. Is formed on the entire surface as an interlayer insulator 217 by a CVD method, contact holes are formed in the source / drain of the TFT, and aluminum is formed. Wiring / electrode 2
18, 219, 220 and 221 were formed. Through the above steps, a semiconductor integrated circuit in which the N-channel TFT is an LDD type is completed. Although not shown in the figure, almost no disconnection was observed at the portion where the second-layer wiring crossed the gate wiring, as in Example 1, even though the interlayer insulator was not so thick.

As in this embodiment, the N-channel TFT is set to L
The DD structure is used to prevent deterioration due to hot carriers. However, since the LDD region is a parasitic resistance inserted in series with the source / drain, there is a problem that the operation speed is reduced. Therefore, in a P-channel TFT having small mobility and little deterioration due to hot carriers, it is desirable that no LDD be present as in this embodiment. In this embodiment, the doping impurities are activated by laser irradiation for each doping step. However, the doping steps may be collectively performed immediately after all the doping steps are completed and immediately before the formation of the interlayer insulator.

Embodiment 3 This embodiment will be described with reference to FIG. This embodiment shows an example in which the degree of etching for forming the sidewall is variously changed in the first embodiment. Instead, what is shown in FIG. 3A will be described. In the figure, a TFT region 301 and a gate wiring 302 are shown. The manufacturing process for obtaining such a structure is the same as that described in Embodiment 1 with reference to FIG. However, in the present embodiment, the side wall 30
In the step of anisotropic etching for forming 4,
Since the etching was slightly over-etched, the sidewall 304 is located slightly below the upper surface of the gate electrode / wiring. Also, the gate insulating film 303
Until it was etched.

In this embodiment, the etching rate of the material forming the sidewall 304 is about twice that of the gate insulating film 303. Therefore, even under the same etching conditions, the etching depth of the gate insulating film was about half of the side wall. In this example, the gate insulating film was etched to about half of the initial thickness. On the other hand, the thickness of the gate insulating film 303 'existing below the sidewall 304 and the gate electrode / wiring is the same as the initial thickness. Further, since the gate electrode and the wiring were covered with the anodic oxide, the gate electrode and the wiring were hardly damaged in the step of anisotropic etching for forming the sidewall.

In such a state, the interlayer insulator 30
5 was formed on the entire surface. Example 1 of sidewall 304
However, unlike the conventional case, the step near the gate wiring 302 is gentle, so that the interlayer insulator is not sufficiently covered by the gate wiring overpass 308.
Was coated. Then, the second-layer wirings 306 and 307
However, since the undulation of the interlayer insulator 305 at the gate crossover portion 308 was gentle, there was no disconnection at the portion.

FIG. 3B shows a case where the etching rate of the material forming the side wall 354 is almost the same as that of the gate insulating film 353. Therefore, under the same etching conditions, the gate insulating film and the sidewalls were almost similarly etched. In this example, the gate insulating film was completely etched, and the TFT active layer was exposed.
Also in this case, the undulation of the interlayer insulating material 355 at the crossing portion of the gate is gentle, so that the second-layer wiring 35
6, 357, there was no disconnection in this part. In general, it is difficult to leave only half of the gate insulating film as shown in FIG. 3A, and it is easier to leave either completely or not at all as shown in FIG. 1 or FIG. 3B. It is.

Embodiment 4 Using the present invention, an active matrix circuit and its peripheral driving circuit,
An example is shown in which circuits such as U are also formed on the same glass substrate.
FIG. 6 shows a block diagram of the entire circuit. All the TFTs constituting these circuits are formed on the same substrate 14.
In FIG. 6, reference numeral 11 denotes a TFT provided in one pixel of the active matrix circuit, and 12 denotes a pixel electrode, 1
3 is an auxiliary capacitor. In the configuration shown in FIG. 6, T is formed in each pixel of the active matrix circuit.
In addition to the FT11, a TF that constitutes a circuit of an input port, a correction memory, a memory, a CPU, an XY branch, an X decoder / driver, and a Y decoder / driver
T is formed on the same substrate. (FIG. 6)

In FIG. 6, an input port reads a signal inputted from the outside and converts it into an image signal. A correction memory is provided on a panel for correcting an input signal or the like in accordance with the characteristics of the active matrix panel. Specific memory. In particular, this correction memory has information unique to each pixel as a non-volatile memory, and is used for individual correction. That is, if a pixel of the electro-optical device has a point defect, a signal corrected in accordance therewith is sent to pixels around the point to cover the point defect and make the defect inconspicuous. Alternatively, when a pixel is darker than the surrounding pixels, a larger signal is sent to the pixel so as to have the same brightness as the surrounding pixels.

The functions of the CPU and the memory are the same as those of an ordinary computer. In particular, the memory has an image memory corresponding to each pixel as a RAM. Further, the backlight that irradiates the substrate from the back surface can be changed according to the image information. FIG. 5 shows a schematic cross section of such a circuit. The circuit is roughly divided into an area of an active matrix circuit (pixel circuit) and an area of a peripheral drive circuit, a CPU, a memory, and the like other than the active matrix circuit. In this embodiment, a complementary circuit including an N-channel TFT 15 and a P-channel TFT 16 is used in a region other than the active matrix circuit. The fabrication method is the same as that shown in Example 2 and FIG. In an active matrix circuit, TF
As the T, a P-channel type TFT 11 was used, and its production was performed simultaneously with the production of the P-channel type TFT in the above-mentioned complementary circuit. (Fig. 5)

Embodiment 5 FIG. 7 shows this embodiment. This embodiment is an example in which an LDD N-channel TFT and a normal P-channel TFT are formed on the same substrate as in the second embodiment. The left side of FIG. 7 is a cross-sectional view of a manufacturing process of an N-channel TFT, and the right side of FIG.
FIG. First, the substrate (Corning 70
59) A silicon oxide film 703 functioning as a base oxide film 702, an island-shaped silicon semiconductor region, and a gate oxide film on 701
Are formed, and gate electrodes 704 and 70 made of an aluminum film (thickness 5000 °) whose surface is covered with anodic oxide are formed.
5 was formed.

Further, the gate oxide film in the portion of the N-channel type TFT was selectively removed by using the gate electrode 704 as a mask to expose the semiconductor layer. Then, phosphorus was implanted by ion doping using the gate electrode portion as a mask to form a low-concentration N-type impurity region 706.
The dose is 1 × 10 ¹³ atoms / cm ² and the acceleration voltage is 20 k
eV. In this doping step, phosphorus was not doped into the island region 707 of the P-channel TFT covered with the gate oxide film 703 because the acceleration voltage was low. (FIG. 7 (A))

Thereafter, the region of the N-channel TFT was masked with a photoresist 708, and in this state, high-concentration boron was doped by ion doping. The dose was 5 × 10 ¹⁴ atoms / cm ² and the acceleration voltage was 65 kV. As a result, a P-type impurity region 709 was formed in the island region 707. (FIG. 7 (B)) In this embodiment, the partial doping of high concentration boron is performed after the entire doping of low concentration phosphorus, but this step may be reversed. After removing the photoresist mask 708, a 4000 to 8000 ° thick silicon oxide film 710 was deposited by a plasma CVD method.
(FIG. 7 (C))

Then, silicon oxide sidewalls 711 and 712 were formed on the side surfaces of the gate electrode by anisotropic etching in the same manner as in Example 2. (FIG. 7D) Thereafter, phosphorus was introduced again by an ion doping method. The dose in this case is preferably one to three orders of magnitude greater than the dose in the step of FIG. In this embodiment, 2 × of 200 times the dose amount of the first phosphorus doping is used.
It was 10 ¹⁵ atoms / cm ² . The acceleration voltage was 20 kV. As a result, the region (source /
Drain) 713 was formed, and a low-concentration impurity region (LDD) 714 was left below the sidewall. On the other hand, phosphorus ions were not implanted in the P-channel type region due to the presence of the gate oxide film. In the second embodiment, both the phosphorus and boron are implanted at a high concentration in the P-channel TFT, so that the dose amount is limited, but in the present embodiment, there is no restriction on the dose amount. However, regarding the accelerating voltage, as described above, it is necessary to lower the phosphorus and increase the boron. (FIG. 7E)

After the doping step, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to activate the doped impurities. Laser energy density is 200-400mJ /
cm ² , preferably 250 to 300 mJ / cm ² was suitable. Finally, as shown in FIG. 7F, a 5000-nm thick silicon oxide film is formed as an interlayer insulator 715 by CVD on the entire surface, contact holes are formed in the source / drain of the TFT, and aluminum wiring and electrodes are formed. 71
6, 717, 718 and 719 were formed. Through the above steps, a semiconductor integrated circuit in which the N-channel TFT is an LDD type is completed.

In this embodiment, compared to the second embodiment, N
In order to remove the gate oxide film in the portion of the channel type TFT, one extra photolithography step and one etching step are required. However, since N-type impurities are not substantially introduced into the P-channel TFT,
There is also an advantage that the dose of each of the impurity of the type and the P-type can be relatively arbitrarily changed. Further, the phosphorus implanted in the vicinity of the surface of the gate oxide film 703 of the P-channel type TFT is effective in forming phosphorus glass in a later laser irradiation step and preventing mobile ions such as sodium from entering.

Embodiment 6 FIG. 8 shows this embodiment. This embodiment relates to a method for manufacturing an active matrix liquid crystal display and is described with reference to FIGS. T on the left side of FIG.
The two FTs are respectively LDD-type N-channel type TFs.
T is a normal P-channel TFT, and represents a logic circuit used for peripheral circuits and the like. The TFT on the right is a switching transistor used in an active matrix array, and is an offset P-channel TFT. First, a base oxide film and an island-like silicon semiconductor region (an island-like region 8 for a peripheral circuit) are formed on a substrate (Corning 7059).
01, island region 80 for active matrix circuit
2) A silicon oxide film 803 functioning as a gate oxide film is formed, and a gate electrode 80 of an aluminum film (thickness 5000 mm) whose surface is covered with anodic oxide.
4, 805 (for peripheral circuits) and 806 (for active matrix circuits) were formed.

Further, the gate oxide film in the portion of the P-channel TFT for the peripheral circuit and the active matrix circuit was selectively removed by using the gate electrodes 804 and 806 as masks to expose the semiconductor layer. Further, the active matrix circuit region was masked with a photoresist 807. Then, boron was implanted by an ion doping method using the gate electrode portion as a mask to form a high-concentration P-type impurity region 808. The dose was 1 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 20 keV. In this doping step, since the acceleration voltage was low, the region of the N-channel TFT covered with the gate oxide film 803 was not doped with boron. (FIG. 8A)

Thereafter, low-concentration phosphorus was doped by an ion doping method. Dose amount is 1 × 10
¹³ atoms / cm ² and the acceleration voltage were 80 kV. As a result, a low-concentration N-type impurity region 809 was formed in the N-channel TFT region. (FIG. 8B) In the drawings, the photoresist mask 806 is removed to perform doping. However, the doping may be performed while the photoresist is still attached. Since the accelerating voltage of phosphorus is high, if doping is performed while leaving the photoresist, phosphorus is not implanted into the active matrix circuit region, so that an ideal offset-type P-channel TFT can be obtained. The resist may be carbonized and it may take time to remove it.

Even when the photoresist is removed, the concentration of phosphorus has a peak below the island-shaped semiconductor region because the acceleration voltage of phosphorus is high. However, there is no guarantee that phosphorus is not completely doped, and a trace amount of phosphorus is formed in the semiconductor region. However, even if phosphorus is doped in this case, its concentration is slight, and P ⁺ (source) / N ⁻ / I (channel) / N ⁻ / P ⁺ (drain)
This structure is suitable for a TFT for an active matrix circuit that needs to reduce leakage current. Thereafter, a silicon oxide film 710 having a thickness of 4000 to 8000 ° is deposited by a plasma CVD method, and sidewalls 810 and 81 of silicon oxide are formed on the side surfaces of the gate electrode by anisotropic etching as in the second embodiment.
1, 812 were formed. (FIG. 8 (C))

Thereafter, boron was introduced again by the ion doping method. The dose in this case is shown in FIG.
It is desirable that the dose is approximately equal to the dose in the step (A). In this embodiment, the dose is 1 × 10 ¹⁵ atoms / c.
m ² and the acceleration voltage were 20 keV. Since the acceleration voltage is low, the N-channel type TFT having the gate oxide film 803 exists.
Region is not doped with boron, and mainly the P-channel type T of the peripheral circuit and the active matrix circuit.
The source / drain of FT was doped. As a result, the source / drain 813 of the TFT of the active matrix circuit was formed. This TFT has an offset structure in which a gate electrode is separated from a source / drain.
(FIG. 8 (D))

Next, doping of phosphorus was performed. In this case, the first phosphorus doping step, FIG.
It is preferable that the dose amount is 1 to 3 digits larger than the dose amount of (B). In this embodiment, the dose is set to 5 × 10 ¹⁴ atoms / cm ^{2, which} is 50 times the dose of the first phosphorus doping. Acceleration voltage is 8
0 kV. As a result, a region (source / drain) 814 into which high-concentration phosphorus is introduced is formed, and a low-concentration impurity region (LDD) 815 is formed under the sidewall.
Was left. On the other hand, in the P-channel type TFT region, most of the phosphorus ions were implanted into the underlying film, and did not significantly affect the conductivity type. (FIG. 8 (E))

After the doping step, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to activate the doped impurities. Laser energy density is 200-400mJ /
cm ² , preferably 250 to 300 mJ / cm ² was suitable.

Then, a 5000 nm thick silicon nitride film is formed as a first interlayer insulator 816 on the entire surface by a CVD method, contact holes are formed in the source / drain of the TFT, and aluminum wiring / electrodes 817, 818, 81 are formed.
9, 820 were formed. Through the above steps, a peripheral circuit region was formed. (FIG. 8F) Further, as the second interlayer insulator 821, a silicon oxide film having a thickness of 3000 .ANG. Is formed by a CVD method, and is etched to form a contact hole. The pixel electrode 8 is formed by the conductive film.
No. 22 was formed. Thus, an active matrix type liquid crystal display substrate was manufactured. (FIG. 8 (G))

[0053]

As described above, according to the present invention, it is possible to reduce the disconnection of the second layer wiring at the gate wiring crossing portion. In particular, an integrated circuit is composed of a large number of elements and wirings. If any one of them has a defect, the entire circuit may be unusable. It is needless to say that the fact that the number of such defects can be significantly reduced by the present invention has a very large effect in increasing the yield of integrated circuits.

Further, according to the present invention, the thickness of the second layer wiring can be set to the same level as the gate electrode / wiring, specifically, ± 1000 [Å]. This has a great effect, which is suitable for an active matrix circuit of a liquid crystal display which requires a small amount of unevenness on the substrate surface. The other advantage obtained by using the present invention is "action".
As described in the section. Thus, the present invention provides a TFT
It is significantly useful in improving the yield of integrated circuits.

[Brief description of the drawings]

FIG. 1 shows a method for manufacturing a TFT circuit according to Example 1.

FIG. 2 shows a method for manufacturing a TFT circuit according to a second embodiment.

FIG. 3 shows a method for manufacturing a TFT circuit according to a third embodiment.

FIG. 4 shows a method for manufacturing a TFT according to a conventional method.

FIG. 5 shows a cross section of a TFT circuit according to a fourth embodiment.

FIG. 6 is a block diagram of a TFT circuit according to a fourth embodiment.

FIG. 7 shows a method for manufacturing a TFT circuit according to a fifth embodiment.

FIG. 8 shows a method for manufacturing a TFT circuit according to Example 6.

[Explanation of symbols]

 Reference Signs List 101 glass substrate 102 base oxide film (silicon oxide) 103 island-like silicon region (active layer) 104 gate insulating film 105, 106 gate electrode (aluminum) 107, 108 anodic oxide (aluminum oxide) 109 weak N-type impurity region 110 insulation Object film (silicon oxide) 111, 112 Side wall 113 LDD (low concentration impurity region) 114 Source / drain 115 Interlayer insulating film (silicon oxide) 116, 117 Metal wiring / electrode (aluminum)

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 27, 2001 (2001.6.2
7)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/3205 H01L 29/78 616A 21/768 27/08 321E 21/8238 321F 27/08 331 21/88 K 27/092 21/90 W 29/786 29/78 613A F term (reference) 2H092 JA24 JA34 JA37 JA41 KA10 KB25 MA08 MA17 MA24 MA27 MA30 NA29 5C094 AA32 AA42 AA43 AA44 BA03 BA43 CA19 DA15 EA04 EA07 JA07 5F033 HJ01 H08 KK01 PP15 QQ08 QQ09 QQ16 QQ35 QQ37 QQ65 QQ73 QQ83 RR03 RR04 SS15 SS26 TT08 VV06 VV15 WW04 XX02 5F048 AA00 AB10 AC04 BA16 BB04 BC06 BF02 DA00 DA25 5F110 AA14 AA26 BB02 EE03 DD02 BB04 BB03 BB04 BB03 GG25 GG45 GG47 HJ01 HJ04 HJ11 HJ23 HL03 HM15 NN03 NN04 NN23 NN35 NN78 PP01 PP03 PP10 PP34 QQ04 QQ11

Claims (1)

[Claims] 1. A semiconductor device having an N-channel thin film transistor and a P-channel thin film transistor connected to the N-channel thin film transistor, wherein the N-channel thin film transistor is formed over a substrate having an insulating surface; A source region and a drain region having N-type conductivity, a channel formation region, and a dose of 1 × 10 ^{13 to} 5 × 10 5 between the channel formation region and the source region and the drain region.
^A first semiconductor film having a low-concentration impurity region of ¹⁴ atoms / cm ^2, a first gate insulating film in contact with the channel forming region, and a first gate insulating film on the channel forming region with the first gate insulating film interposed therebetween; A gate electrode, the P-channel type thin film transistor is formed on the substrate,
Source and drain regions having the same conductivity type,
A second semiconductor film having a channel forming region between the source region and the drain region, a second gate insulating film in contact with the channel forming region, and the channel formed through the second gate insulating film. A semiconductor device having a gate electrode over a formation region, wherein the P-channel thin film transistor does not have a low-concentration impurity region.