JP3527113B2 - Memory self-test device and semiconductor integrated circuit incorporating this memory self-test device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory self-test device and a semiconductor integrated circuit incorporating the memory self-test device, and more particularly to a technique for detecting a failure in a mode in which an error occurs depending on a memory reading speed. Regarding

[0002]

2. Description of the Related Art Heretofore, there are known some methods for storing data in a memory cell. One of such methods is a transistor that constitutes a memory cell (hereinafter,
There is a method of storing the logic "0" or "1" by changing the threshold value of "cell transistor".
For example, in the case of a flash memory, the gate of the cell transistor is composed of two types, a floating gate and a control gate.

By controlling the amount of electrons accumulated in the floating gate of the cell transistor,
The threshold value of the cell transistor is changed so that the logic "0" or "1" is stored. V _tm0 the threshold voltage of the cell transistor to store the logic "0", the threshold voltage of the cell transistor to store the logic "1" and V _tm1, if the voltage applied to the gate of the cell transistor at the time of reading and V _r, For example, each voltage V so as to satisfy the following equation (1)
_tm0, by determining the V _r and V _tm1, can be realized reading logic "0" and "1". V _tm0 > V _r > V _tm1 ... Equation (1)

That is, even if the read voltage V _r is applied to the gate of the cell transistor in which the logic "0" is stored, the cell transistor remains off. Therefore, a current does not flow in the sense amplifier connected through the bit line, so that it is determined as a logic "0". When the read voltage V _r is applied to the gate of the cell transistor storing the logic “1”, the cell transistor is turned on. Therefore, the on-current flows into the sense amplifier connected through the bit line, and it is determined as logic "1".

By the way, when the flash memory is operated at a high temperature for a long time, there is a case where a failure occurs in a mode in which the threshold voltage V _tm1 rises for some reason. In this case, since the difference between the read voltage V _r and the threshold voltage V _tm1 becomes small, the on-current decreases and the operation of the sense amplifier becomes slow. Therefore, when reading at a speed sufficiently slower than the standard speed, correct data can be obtained, but when reading at the standard speed, incorrect data can be obtained.

In order to eliminate a flash memory having such a mode failure, an evaluation device such as a dedicated tester has been conventionally used. In this evaluation device,
Whether the flash memory operates according to the standard, that is, by reading the contents of the flash memory at the standard speed and comparing the read data with the expected value data prepared in advance to check if they match We are checking if it is a good product.

[0007]

However, in such a test method, it is necessary to prepare a dedicated evaluation device for testing the flash memory, which causes a problem that the cost required for the test becomes high. In addition, in the test using this evaluation device, each flash memory must be mounted on the evaluation device, which requires a long time for the test, resulting in an increase in the number of steps.

As a technique for solving such a problem, for example, Japanese Unexamined Patent Publication No. 3-269900 discloses a "semiconductor integrated circuit". In this semiconductor integrated circuit, a circuit including a rewritable memory (memory under test) to be tested is formed on one semiconductor chip. During a test operation, this semiconductor integrated circuit is set to a test mode in which a signal line for exchanging signals between the memory under test and another circuit during an actual operation is electrically disconnected.

Then, the test data from the ROM inside the semiconductor integrated circuit for storing the data used for the test or the test data supplied from the outside of the semiconductor integrated circuit is
Write to the memory under test according to the test clock input from the outside, and then compare the data from the memory under test with the test data from the ROM or external,
The comparison result is output to the outside of the semiconductor integrated circuit. In this way, the individual test of the memory under test contained in the semiconductor integrated circuit is performed by the semiconductor integrated circuit itself.

However, this semiconductor integrated circuit cannot detect a mode failure such as a slow reading speed when the flash memory is operated at a high temperature for a long time as described above. Further, this semiconductor integrated circuit requires a ROM for storing test data for testing the memory under test, or a circuit for inputting test data from the outside, which complicates the circuit and increases integration. The conversion rate decreases. In addition, the number of man-hours for testing increases because it is necessary to create test data.

Further, Japanese Unexamined Patent Publication No. 9-219099 discloses a "self-burn-in circuit for semiconductor memory". The self-burn-in circuit includes a burn-in sensing unit that generates a predetermined control signal for burn-in test, an address signal, and test data when a predetermined self-burn-in test condition is satisfied, and the address signal by controlling the control signal. Memory cell array in which a burn-in test is performed by writing / reading the test data in a memory cell selected according to the above.

According to this burn-in circuit, since various control signals and test data necessary for the burn-in test operation are generated inside the chip, the applied external voltage exceeds a predetermined level and a normal burn-in test is performed from the outside. If the signal for notifying is not input, the burn-in operation is performed by itself. However, even with this burn-in circuit, it is not possible to detect a mode failure such that the read speed becomes slow when the flash memory is operated at a high temperature for a long time.

The present invention has been made in order to solve the above-mentioned problems, and is a memory self-test capable of reducing the test cost, time, and man-hours as compared with the conventional test using an evaluation device such as a tester. An object of the present invention is to provide a device and a semiconductor integrated circuit incorporating the memory self-test device.

[0014]

According to a first aspect of the present invention
The memory self-test device that uses
Includes configured memory and memory self-test circuit
ing.

A memory self-test according to the first aspect of the present invention
In the storage device, the memory stores the first clock signal.
The product is tested and judged as good. Previous
The memory self-test circuit outputs the first clock signal.
The data read from the memory and the first clock
Using the second clock signal slower than the lock signal, the memo
By comparing the data read from the
Has the threshold voltage of the cell transistor of the memory changed?
Perform a retest to see if it does.

A memory self-test according to the first aspect of the present invention
In the storage device, the memory self-test circuit
Equipped with a projection circuit, a temporary storage means, and a comparison circuit
It The read circuit is configured to output the first clock signal or the previous clock signal.
Read data from the memory using the second clock signal
To stick out. The temporary storage means is the read circuit.
Temporarily record the data read using the second clock signal
I remember. The comparison circuit is the read circuit and is the first circuit.
The data read using the clock signal and the temporary recording
The data read from the memory is compared and the comparison result is
Output the signal that represents.

A memory self-test according to the first aspect of the present invention
In the storage device, the memory self-test circuit
It has a circuit. The frequency divider circuit has a first clock signal.
The second clock signal is generated by dividing the signal.

A memory self-test according to the first aspect of the present invention
In the storage device, the memory may be a non-volatile memory, particularly a flash memory that stores information by changing the threshold voltage of a cell transistor. This memory can be composed of a synchronous memory that operates in synchronization with a clock signal.

A memory self-test according to the second aspect of the present invention
The strike device is composed of a plurality of cell transistors.
It has a memory and a memory self-test circuit. The above
The memory and the memory self-test circuit are one semiconductor
It is formed on the substrate.

A memory self-test according to the second aspect of the present invention
In the storage device, the memory stores the first clock signal.
The product is tested and judged as good. Previous
The memory self-test circuit retests the memory.
It The memory self-test circuit uses the first clock signal
The data read from the memory and the first
The second clock signal, which is slower than the clock signal, is used to
By comparing the data read from the memory
Whether or not the threshold voltage of the cell transistor has changed.
Find out.

A memory self-test according to the second aspect of the present invention
In the storage device, the memory self-test circuit
Equipped with a projection circuit, a temporary storage means, and a comparison circuit
It The read circuit is configured to output the first clock signal or the previous clock signal.
Read data from the memory using the second clock signal
To stick out. The temporary storage means is the read circuit.
Temporarily record the data read using the second clock signal
I remember. The comparison circuit is the read circuit and is the first circuit.
The data read using the clock signal and the temporary recording
The data read from the memory is compared and the comparison result is
Output the signal that represents.

A memory self-test according to the second aspect of the present invention
In the storage device, the memory self-test circuit
It has a circuit. The frequency divider circuit includes the first clock
A second clock signal is generated by dividing the frequency signal
It

A memory self-test according to the second aspect of the present invention
In the storage device, the memory may be a non-volatile memory, particularly a flash memory that stores information by changing the threshold voltage of a cell transistor. This memory can be composed of a synchronous memory that operates in synchronization with a clock signal.

The above semiconductor substrate (the memory and the memory
Re-self test circuit and the semiconductor substrate on which it is formed)
For example , the self-test can be realized without using an evaluation device such as a tester.

The present invention is premised on testing a memory in which correct data can be read at a speed sufficiently slower than the standard speed. That is, even if the threshold voltages V _{tm 0} and V _tm1 fluctuate for some reason, the test target is a memory in which the relationship of V _tm0 > V _r > V _tm1 is maintained, that is, a memory having a certain quality or more. Therefore, the present invention provides
Rather than being used for the initial selection of the memory, it is preferably used for a test to be performed on the memory that has undergone a series of selections, such as a reliability evaluation test and confirmation of the final stage of product shipment.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a microcomputer 11 as an example of a semiconductor integrated circuit according to the present invention. The microcomputer 11 is composed of a flash EEPROM 12, which is a non-volatile memory, a self-test circuit 13, and a logic circuit 14. The logic circuit 14 includes a central processing unit (CPU), peripheral circuits and the like. The memory self-test device of the present invention is a flash EEPROM.
It is composed of an M12 and a self-test circuit 13.

The microcomputer 11 operates in synchronization with a first clock signal CK1 given from the outside. In order to realize this synchronous operation, the flash EEP
The first clock signal CK1 is supplied to each of the ROM 12, the self-test circuit 13, and the logic circuit 14.

The flash EEPROM 12 is a synchronous memory in which writing and reading are performed in synchronization with the first clock signal CK1. In addition, the self-test circuit 13
Will be described in detail later, but the first clock signal C from the outside
A second clock signal CK2 is generated based on K1, and the first clock signal CK1 and the second clock signal CK2 are generated.
The flash EEPROM 12 is tested by using the microcomputer and the result is used as a match / mismatch signal for the microcomputer 1
1 to the outside.

Next, the operation of testing the flash EEPROM 12 in the microcomputer 11 configured as described above will be described. When the microcomputer 11 operates normally, the flash EEPROM 12 is electrically connected to the logic circuit 14. On the other hand, when the microcomputer 11 is set to the test mode by activating a predetermined signal line (not shown), the flash EEPROM 12 is electrically connected to the self-test circuit 1 as shown in FIG.
3 is connected.

When the microcomputer 11 is set to the test mode, the self-test circuit 13 first causes the flash EEPROM 12 to use the second clock signal CK2 having a frequency sufficiently lower than the first clock signal CK1 used in the normal operation. Read the data. The read data is stored in a RAM 25 (details described later) provided in the self-test circuit 13.

Then, data is read from the flash EEPROM 12 using the first clock signal CK1. Then, the read data is compared with the data previously read and stored in the RAM 25, and the comparison result is output to the outside of the microcomputer 11 as a match / mismatch signal. If this match / mismatch signal indicates a match, the flash EEPROM 12
Is judged to be normal. On the other hand, if they do not match, it is recognized that the data differs due to the difference in read speed, and this flash EEPROM 12 is determined to be in failure.

Next, the structure of the memory self-test device including the flash EEPROM 12 and the self-test circuit 13 will be described with reference to the block diagram shown in FIG.
The self-test circuit 13 included in this memory self-test device includes a frequency divider circuit 20, a multiplexer 21, a read circuit 22, a demultiplexer 23, and a write circuit 2.
4, a RAM 25, a read circuit 26, and a comparison circuit 27.

The frequency dividing circuit 20 divides the first clock signal CK1 having a frequency f input from the outside by a factor of N to generate a second clock signal CK2 having a frequency f / N. The second clock signal CK2 generated by the frequency dividing circuit 20 is supplied to the multiplexer 21. This frequency f / N is
The number of frequency division steps is determined so that the frequency is sufficiently smaller than the frequency f.

The multiplexer 21 receives a first clock signal CK1 from the outside or a second clock signal CK from the frequency dividing circuit 20 in response to a selection signal from a control circuit (not shown).
Pass either of the two. That is, the multiplexer 21
When the data is read from the flash EEPROM 12 at the frequency f, the first clock signal CK1 from the outside is passed, and the flash EEPROM 12 at the frequency f / N.
When the data is read from, the second clock signal CK2 from the frequency dividing circuit 20 is passed. This multiplexer 2
The clock signal output from 1 is the flash EEPR.
It is supplied to the OM 12 and the read circuit 22.

The flash EEPROM 12 has a frequency f
Alternatively, it operates with a clock signal having a frequency f / N obtained by dividing the frequency. It should be noted that description of data writing to the flash EEPROM 12 is omitted.

The read circuit 22 includes a multiplexer 21.
Flash EEPROM 1 using the clock signal from
Controls the reading of data from 2. Therefore, the read circuit 22 reads data from the flash EEPROM 12 using either the clock signal of frequency f or the clock signal of frequency f / N according to the selection signal. The data read by the read circuit 22 is supplied to the demultiplexer 23.

The demultiplexer 23 supplies the data from the read circuit 22 to either the write circuit 24 or the comparison circuit 27 according to the selection signal. That is,
The demultiplexer 23 uses the flash E at the frequency f / N.
When the data is read from the EPROM 12, the data is supplied to the writing circuit 24, and when the data is read from the flash EEPROM 12 at the frequency f,
The data is supplied to the comparison circuit 27.

The write circuit 24 uses the first clock signal C
The control for writing the data from the demultiplexer 23 to the RAM 25 is performed in synchronization with K1. RAM
25 corresponds to the temporary storage means of the present invention, and temporarily stores the data read from the flash EEPROM 12 by using the clock signal of the frequency f / N. The read circuit 26 synchronizes with the first clock signal CK1 in synchronization with R
Control for reading data from the AM 25 is performed.

The comparison circuit 27 compares the data from the demultiplexer 23 with the data from the RAM 25. The comparison result by the comparison circuit 27 is output to the outside as a match / mismatch signal. When the operating speed is lowered due to the fluctuation of the threshold voltage of the cell transistor of the flash EEPROM 12, a mismatch signal is output here.

Next, the operation of the semiconductor integrated circuit having the above-described structure and incorporating the memory self-test device will be described with reference to the flow chart shown in FIG.

When the semiconductor integrated circuit incorporating this memory self-test device is set to the test mode, the control circuit (not shown) supplies a selection signal to the multiplexer 21 and the demultiplexer 23. This causes the multiplexer 21 to pass the first clock signal CK1 from the outside, and the demultiplexer 23 is initialized to supply the data from the read circuit 22 to the write circuit 24.

In this state, first, the flash EEPRO
The data stored in M12 is read (step S1). Therefore, the data is read from the flash EEPROM 12 using the clock signal of the frequency f / N from the frequency dividing circuit 20. Next, the read data is written in the RAM 25 (step S
2). By the above, all the data in the flash EEPROM 12 is written in the RAM 25. Thereafter, although not shown, a control circuit (not shown) supplies a selection signal to the multiplexer 21 and the demultiplexer 23.
As a result, the multiplexer 21 passes the second clock signal CK2 from the frequency dividing circuit 20, and the demultiplexer 23 is set to supply the data from the reading circuit 22 to the comparison circuit 27.

In this state, the flash EEPROM 12
The data stored in is sequentially read (step S3). Therefore, the data is read from the flash EEPROM 12 by using the first clock signal CK1 having the frequency f from the outside. Next, the data read from the flash EEPROM 12 and the RAM first
It is sequentially checked whether or not it matches the data stored in 25 (step S4). This is the read circuit 22
The data read from the flash EEPROM 12 and the data read from the RAM 25 by the read circuit 26 are sequentially supplied to the comparison circuit 27.

When it is determined that they match, the flash EEPROM 12 is recognized as a non-defective product (step S5), and when it is determined that they do not match, it is recognized as a defective product (step S6). ).

When the capacity of the flash EEPROM 12 is larger than that of the RAM 25 and all the data in the flash EEPROM 12 cannot be written in the RAM 25 at one time, it is divided into a plurality of times as shown in FIG. The processing may be the same as the processing. That is, in addition to the steps shown in FIG. 3, a step (step S7) for checking whether the test of the entire area of the flash EEPROM 12 is completed is provided, and if there is an untested area, the test may be sequentially repeated. Good.

According to the semiconductor integrated circuit in which the memory self-test device constructed as described above is incorporated, it is checked whether the operation speed is decreased due to the threshold voltage fluctuation of the cell transistor of the flash EEPROM 12 by a tester or the like. It can be easily identified by a self-test that does not use an evaluation device.

The microcomputer 11 is usually equipped with a RAM. In this case, the self test described above can be performed using the RAM provided in the microcomputer 11 without providing the RAM 25 inside the self test circuit 13. In this case, the RAM 25 of the self-test circuit 13 is not necessary, so that the area overhead due to the provision of the self-test circuit can be reduced.

[0049]

As described in detail above, according to the present invention,
Compared with a test using a conventional tester or other evaluation device,
It is possible to provide a memory self-test device that can reduce the cost, time, and man-hours required for a test, and a semiconductor integrated circuit incorporating this memory self-test device.

That is, first, since the semiconductor integrated circuit has the function of testing the memory contents, an evaluation device such as a tester is unnecessary, and the cost for the test can be reduced. Secondly, since a large number of semiconductor integrated circuits can be tested at the same time, the total test time can be shortened. Thirdly, it is not necessary to prepare the expected value data separately, so the test man-hour can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory self-test device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a microcomputer as a semiconductor integrated circuit including a memory self-test device according to an embodiment of the present invention.

FIG. 3 is a flowchart showing an operation example of the memory self-test device according to the embodiment of the present invention.

FIG. 4 is a flowchart showing another operation example of the memory self-test device according to the embodiment of the present invention.

[Explanation of symbols]

11 Microcomputer 12 flash EEPROM 13 Self-test circuit 14 logic circuits 20 frequency divider 21 Multiplexer 22 Read circuit 23 Demultiplexer 24 Writing circuit 25 RAM 26 Read circuit 27 Comparison circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 29/00

Claims (8)

(57) [Claims] 1. A memory comprising a cell transistor, which has been tested and judged to be non-defective by using a first clock signal, data read from the memory using the first clock signal, and the first clock. A memory self-test circuit that performs a retest to determine if the threshold voltage of a cell transistor of the memory has changed by comparing the data read from the memory with a second clock signal that is slower than the signal; And a memory self-test device having. 2. The memory self-test circuit includes a read circuit that reads data from the memory using the first clock signal or the second clock signal, and a read circuit that uses the second clock signal in the read circuit. Temporary storage means for temporarily storing the stored data, and a signal indicating a comparison result by comparing the data read by the read circuit using the first clock signal with the data read from the temporary storage means. The memory self-test device according to claim 1, further comprising: 3. The memory self-test device according to claim 1, wherein the memory self-test circuit includes a frequency divider circuit that generates a second clock signal by dividing the first clock signal. 4. The memory self-test device according to claim 1, wherein the memory is a flash memory. 5. A structure comprising a plurality of cell transistors,
A memory that is non-defective judgment tested by using the first clock signal, comprising: a memory self-test circuit for retest the memory, formed in the memory and said memory self-test circuit one semiconductor substrate And the memory self-test circuit compares the data read from the memory with a first clock signal and the data read from the memory with a second clock signal slower than the first clock signal. The semiconductor integrated circuit is characterized by checking whether or not the threshold voltage of the cell transistor has changed. 6. The memory self-test circuit comprises: a read circuit for reading data from the memory using the first clock signal or the second clock signal; and a read circuit for reading data using the second clock signal in the read circuit. Temporary storage means for temporarily storing the stored data, and a signal indicating a comparison result by comparing the data read by the read circuit using the first clock signal with the data read from the temporary storage means. The semiconductor integrated circuit according to claim 5, further comprising: 7. The semiconductor integrated circuit according to claim 5, wherein the memory self-test circuit includes a frequency dividing circuit that generates a second clock signal by dividing the first clock signal. 8. The semiconductor integrated circuit according to claim 5, wherein the memory is a flash memory.