JP3512781B2 - Thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (Thin film) using a semiconductor film (semiconductor layer) formed on a substrate.
in Film Transistor, hereinafter referred to as TFT), a semiconductor device using the same, and a manufacturing method thereof.
Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and a semiconductor device manufactured by the present invention is a display device typified by a liquid crystal display device or an EL display device having a built-in TFT. , A semiconductor integrated circuit (microprocessor, signal processing circuit, high-frequency circuit, or the like) is included in the category.

[0002]

2. Description of the Related Art With the development of information communication technology, a display device as a means for receiving information has been replaced with a flat panel display from a CRT. CR has been used to display televisions that have provided a lot of information.
T (Cathode Ray Tube) has a problem in that it cannot sufficiently cope with the amount of information in recent years (for example, high image quality of images). In addition to the high resolution for displaying a high-quality image, there is also a problem that it cannot sufficiently cope with a large screen. For example, when trying to increase the screen size, the weight of the CRT itself becomes considerably large, making it difficult to carry. In addition, even if the screen size is the same, if the resolution is increased, the brightness is reduced and the depth must be increased, so that the installation at home is considerably limited.

Therefore, as a candidate for a display device which can meet the demand for high resolution and large screen, a flat panel display characterized by small size, light weight and space saving has been attracting attention. Among them, liquid crystal display devices have been particularly attracting attention, and large-scale research and development have been promoted.

In order to deal with the increased amount of information, it must be possible to write data in a short time.
In addition, it is required to incorporate a drive circuit in the display device in order to save space and reduce the price. In order to realize such a display device, the TFT forming a switching element of a pixel or a driving circuit is required to operate at high speed.

As a method for realizing a high-speed operation of a TFT, for example, a semiconductor layer is changed from amorphous to polycrystal, or a dual gate (dual gate) which sandwiches a semiconductor layer with a pair of gate electrodes described in Japanese Patent No. 2737780. Gate) structures are being considered.

However, even if a TFT is formed using polycrystalline silicon, for example, the field effect mobility is 1/10 or less of that of single crystal silicon, and its electrical characteristics are after all formed on a single crystal silicon substrate. It is not comparable to the characteristics of MOS transistors. In addition, there is a new problem that the off current becomes high due to the defects formed at the crystal grain boundaries.

Further, when forming an integrated circuit using TFTs, it is necessary to control the threshold voltage (Vth) in order to obtain a desired switching operation. Threshold voltage (Vt
h) is an important parameter that represents the switching characteristics of the TFT, and if this value deviates from the desired value, the circuit operation will be hindered. Therefore, in order to control the threshold value, for example, in the case of an n-channel type TFT, it shifts to the negative side and becomes normally on (state in which the gate voltage is not applied). Is a problem. In order to prevent this, a measure is taken to add an impurity (acceptor) imparting p-type to the channel region (channel formation region) to shift the threshold voltage to the positive side.

Further, the data line side driving circuit is required to have high driving ability (ON current, I _on ), prevent deterioration due to hot carrier effect and improve reliability. On the other hand, a low off current (I _off ) is required for the switching element in the pixel section in order to obtain high quality image. As described above, in order to satisfy the requirements for the liquid crystal display device, it is important to realize the TFT having the characteristics required for each circuit.

[0009]

Conventionally, a low concentration impurity element was added to the channel region to control the threshold value. However, in the case of a structure in which a semiconductor layer is sandwiched between a pair of gate electrodes, the semiconductor layer is There is a high probability that carriers are generated at the interface of the insulating film, carriers are injected into the insulating film or the interface between the insulating film and the semiconductor layer, and the threshold value increases. Further, according to the energy band structure of the channel region, the path of carriers is only in the vicinity of the interface between the semiconductor layer and the insulating film. For this reason, the hot carriers accelerated by the voltage applied to the drain are injected into the interface between the insulating film and the semiconductor layer or into the insulating film, resulting in a decrease in mobility and drain current.

Therefore, in the present invention, in view of the above-mentioned problems,
It is an object to realize a highly reliable semiconductor device by realizing high drain current and field effect mobility.

[0011]

According to the present invention, regions having the same conductivity type are provided in the upper and lower portions of a channel region, and the region between the upper and lower portions is an intrinsic region or the same region added at a low concentration. A feature is that a region having a conductivity type is provided and a region where carriers flow is provided widely. That is, an impurity region imparting p-type conductivity is provided above and below the channel region of the n-channel thin film transistor, and an impurity region imparting n-type conductivity is provided above and below the channel region of the p-channel thin film transistor. Is characterized by.

Specifically, the present invention provides a first gate electrode, a first gate insulating film provided on the first gate electrode, and a first gate insulating film provided on the first gate insulating film. A first semiconductor film, a second semiconductor film provided on the first semiconductor film, a third semiconductor film provided on the second semiconductor film, and a third semiconductor film provided on the third semiconductor film. A thin film transistor having a second gate insulating film provided and a second gate electrode provided on the second gate insulating film, comprising: a channel forming region of the first semiconductor film; The channel formation region of the semiconductor film of 3 is 1 × 1
The channel forming region of the second semiconductor film contains an impurity element imparting the same conductivity type at a concentration of 0 ¹⁵ to 1 × 10 ¹⁷ / cm ³ , and the channel forming region of the second semiconductor film is intrinsic or at a concentration of 1 × 10 ¹⁵ / cm ³ or less. A thin film transistor including an impurity element imparting a conductivity type is featured.

The present invention also includes a first gate electrode and
A first gate insulating film provided on the first gate electrode
And a first semiconductor provided on the first gate insulating film.
A body film and a second semiconductor provided on the first semiconductor film.
A body film and a third semiconductor provided on the second semiconductor film.
The body film and the second gate provided on the third semiconductor film.
A gate insulating film and a first gate insulating film provided on the second gate insulating film.
N-channel thin film having two gate electrodes, respectively
A transistor and a p-channel thin film transistor
Therefore, in the n-channel thin film transistor,
The channel formation region of the first semiconductor film and the third half
The channel formation region of the conductor film is 1 × 10 ¹⁵~ 1 x 10¹⁷/ c
m³An impurity element imparting p-type at a concentration of
The channel formation region of the second semiconductor film is intrinsic or 1 × 1
0¹⁵/cm³An impurity element that imparts p-type is contained at the following concentration.
The p-channel thin film transistor
Channel forming region of the semiconductor film of No. 1 and the third semiconductor
The channel formation region of the body membrane is 1 × 10¹⁵~ 1 x 10¹⁷/cm³
The impurity element imparting n-type at a concentration of
The channel formation region of the second semiconductor film is intrinsic or 1 × 1
0¹⁵/cm³Containing an impurity element that imparts n-type at the following concentrations
It features a thin film transistor.

When a voltage higher than a threshold voltage that causes an inversion state is applied to the TFT of the present invention, the first semiconductor layer and the third semiconductor layer to which the impurity element imparting one conductivity type, which serves as a potential barrier, is added. Since the inversion layer is widely formed in the intrinsic second semiconductor layer formed between the semiconductor layers,
The region in which carriers flow becomes wider, the drain current becomes larger, and the subthreshold coefficient (S value) becomes smaller.
It can be said that an element having a small S value is an ideal switch having a sharp rising edge. Note that one conductivity type impurity added to the first and third semiconductor layers may be added to the channel region of the second semiconductor layer at a concentration of 1 × 10 ¹⁵ / cm ³ or less.

Further, since the main inversion layer is formed in the second semiconductor layer, carriers generated in this region are not scattered at the interface between the insulating film and the semiconductor layer, and the conventional structure of the channel region is formed. The value of the field effect mobility is improved as compared with the TFT having the. Further, the second semiconductor layer is the first
Is surrounded by a potential generated by a difference in Fermi energy between the second semiconductor layer and the second semiconductor layer or the second semiconductor layer and the third semiconductor layer. Prevents scattering injection into the insulating film. Therefore, the structure of the channel region of the present invention can reduce the influence of hot carrier deterioration on the drain current.

The channel region is a region of the semiconductor layer in which carriers flow, which is in an inverted state (has an inversion layer), and each of the first to third semiconductor layers has a channel region.

[0017]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device disclosed in the present invention is shown in FIG.

The structure shown in FIG. 1A has a structure in which a first gate electrode 11, a first gate insulating film 12,
It has a first semiconductor layer 13, a second semiconductor layer 14, a third semiconductor layer 15, a second gate insulating film 18, and a second gate electrode 19. The structure shown in FIG. 1B has a channel region and source or drain regions 16b and 1b.
7b, a low-concentration impurity region (also referred to as an LDD region) 16 in which an impurity element imparting a conductivity type is added at a low concentration.
a and 17a.

In this specification, the electrode formed between the substrate and the semiconductor layer is referred to as a first gate electrode, and the electrode formed between the semiconductor layer and the pixel electrode is referred to as a second gate electrode. The insulating film formed in contact with the first gate electrode is referred to as a first gate insulating film, and the insulating film formed between the semiconductor layer and the second gate electrode is referred to as a second gate insulating film.

A first semiconductor layer 13 is formed in contact with the first gate insulating film 12. In the channel region of the first semiconductor layer, an impurity element imparting one conductivity type (for example,
If it is an impurity element imparting p-type, boron) is 1 ×
It is added at a concentration of 10 ¹⁵ to 1 × 10 ¹⁷ / cm ³ .

A second semiconductor layer 14 is formed in contact with the first semiconductor layer 13. The impurity element is not added to the channel formation region of the second semiconductor layer 14, which is substantially intrinsic.

A third semiconductor layer 15 is formed in contact with the second semiconductor layer 14. In the channel formation region of the third semiconductor layer 15, an impurity element imparting one conductivity type (as long as it has the same conductivity type as the impurity element added to the first semiconductor layer) is 1 × 10 ¹⁵ to. It is added at a concentration of 1 × 10 ¹⁷ / cm ³ .

In the region to be the source region or drain region 16 or 17 (16b, 17b) of the semiconductor layer, 1 × 10 6 of n-type impurity element is used in the case of an n-channel TFT.
It is added at a concentration of ¹⁹ to 1 × 10 ²¹ / cm ³ . Also, p
In the case of a channel type TFT, the p-type impurity element is 1
It is added at a concentration of × 10 ¹⁹ to 1 × 10 ²¹ / cm ³ . Further, in the regions to be the low-concentration impurity regions (LDD regions) 16a and 17a, the impurity element imparting the conductivity type is 1 × 10.
It is added at a concentration of ¹⁸ to 1 × 10 ²⁰ / cm ³ .

TF having a structure of a channel region as shown in FIG. 1 (a plurality of semiconductor layers having different conductivity types are laminated)
A band structure in the case where a voltage higher than the threshold voltage is applied to T is shown in FIG. As a comparison, FIG.
-2) shows a band structure when a voltage equal to or higher than the threshold voltage is applied to the TFT having the structure of the channel formation region of the conventional TFT.

According to the present invention, the conduction band in the intrinsic region is close to the Fermi level, and the inversion layer is formed. Figure 2 (A-
As shown in 2), carriers exist (can move)
The area is formed in a wide range. In the case of the conventional channel structure, the inversion layer is formed at the interface between the semiconductor layer and the insulating film.

Further, in the TFT of the present invention, an inversion layer is formed at the interface between the semiconductor layer and the insulating film as in the conventional structure, but hot carriers are generated and the insulating film and the semiconductor layer and the insulating film are formed. Even if injected into the interface, since the main inversion layer is the region formed in the intrinsic second semiconductor layer, it is possible to suppress deterioration such as a decrease in drain current or an increase in S value. . Further, since the inversion layer is widely formed in the second semiconductor layer, the drain current becomes large and the S value becomes small. Further, since the concentration of the impurity element contained in the first semiconductor layer and the third semiconductor layer can be changed in association with the thickness of the insulating film,
The degree of freedom in controlling the threshold value can be improved.

Next, when a voltage that causes an accumulation state (off state) is applied to the TFT, the Fermi level of the TFT of the present invention approaches the midgap, the inversion layer is not formed, and current does not flow.

As described above, the TFT of the present invention can perform switching operation like a TFT having a normal structure, and further has characteristics such as field effect mobility, S value and threshold voltage. Can be improved.

[0029]

EXAMPLE 1 An example of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. Note that the shape of the semiconductor device manufactured here is merely an example, and the shape and manufacturing steps of the semiconductor device shown in this embodiment are not limited.

In FIG. 3A, the substrate 101 can be a glass substrate, a quartz substrate, a ceramic substrate, or the like. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

Wirings 102 to 108 to be the first gate electrodes are formed on the insulating surface of the substrate 101. The first gate electrode is formed of a conductive material composed of one kind or a plurality of kinds selected from W, Mo, Ti, and Ta. FIG. 7A shows a top view of them in the pixel portion. Here, wiring 1
05 is used as a data line.

After forming the first gate electrode, the first gate insulating film 109 is formed. First gate insulating film 10
Reference numeral 9 may be a laminated structure in which a silicon oxynitride film is formed to a thickness of 10 to 50 nm and a silicon oxide film or a silicon oxynitride film is formed to a thickness of 0.5 to 1 μm.

The surface of the first gate insulating film may be flattened. CMP may be used as a planarization method. In addition, the polishing agent (slurry) for CMP includes, for example,
The fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in a KOH-added aqueous solution.
The surface of the gate insulating film 109 may be flattened by removing about 0.1 to 0.5 μm.

Next, a semiconductor film is formed on the first gate insulating film 109. An amorphous silicon film is formed as the first semiconductor layer 110 and is crystallized by a known method (for example, heat treatment using a furnace) to make the first semiconductor layer a crystalline semiconductor layer. In this embodiment, the thickness of the first semiconductor layer is 20 nm. Then, an impurity element imparting one conductivity type is added to the channel region. An impurity element which imparts p-type conductivity using a mask 111 (hereinafter referred to as a p-type impurity element) is provided in a region to be an n-channel TFT later.
To form the regions 112a to 112c added with (see FIG.
(B)) Next, using the mask 113, a region 114 to which an impurity element imparting n-type conductivity is added is formed in a region to be a p-channel TFT later (FIG. 3C).

Next, a second semiconductor layer 115 is formed on the first semiconductor layer 110 (FIG. 4A). After forming the amorphous semiconductor layer, the second semiconductor layer is subjected to heat treatment to be crystallized to be a crystalline semiconductor layer. Note that crystallization of the second semiconductor layer is preferably performed with a laser in order to prevent diffusion of the impurity element of the first semiconductor layer.
In this embodiment, the thickness of the second semiconductor layer is 50 nm.
And

Subsequently, the third semiconductor layer 116 is formed on the second semiconductor layer 115. The third semiconductor layer 116 is
Similar to the first semiconductor layer 110, an amorphous semiconductor layer is formed and then crystallized by a known method (for example, heat treatment using a furnace) to make the third semiconductor layer a crystalline semiconductor layer. In this embodiment, the thickness of the third semiconductor layer is 20 n.
m. Then, an impurity element imparting one conductivity type is added to the channel region. Regions 118a to 118c to which a p-type impurity element is added are formed using a mask 117 in a region to be an n-channel TFT later (FIG. 4B).
A region 120 to which an n-type impurity element is added is formed using a mask 119 in a region to be a p-channel TFT later (FIG. 4C).

In this embodiment, the film thickness of each semiconductor layer is determined as described above, but the film thickness is not limited to this, and the film thickness of each semiconductor layer can be appropriately set by the practitioner. Just decide.

Although the third semiconductor layer is newly formed in this embodiment, the second semiconductor layer is formed to have a film thickness including the third semiconductor layer, and the third semiconductor layer is formed. An impurity element imparting one conductivity type may be added to the channel region up to the depth of the thickness assumed to be a layer.

As a method for adding an impurity element imparting one conductivity type to the first semiconductor layer, an ion implantation method for mass separation, a method for doping by setting an acceleration voltage to a low value by an ion doping method, and plasma If the practitioner appropriately determines and uses any method such as a doping method or a method of depositing an impurity element on the third semiconductor layer and then heat-treating it to diffuse it into the third semiconductor layer (thermal diffusion method). Good.

As a method of adding an impurity element imparting one conductivity type to the third semiconductor layer, a method of doping by setting the acceleration voltage to a low value by an ion implantation method for mass separation or an ion doping method. The practitioner may appropriately determine and use any one of the plasma doping method and the like. The practitioner may also appropriately determine the film thickness of the semiconductor layer.

When using a circuit having an NMOS structure or a PMOS structure, a doped-poly silicon film (crystalline silicon film, polysilicon film) formed in a state where an impurity element imparting one conductivity type is added. ) Is formed, a poly silicon film containing no impurities is stacked, and an impurity element imparting one conductivity type is further added to form a dope film.
The channel structure of the present invention can be formed by stacking d-poly silicon films.

When a circuit having a CMOS structure is used, a doped-poly silicon film is formed in a state where an impurity element imparting one conductivity type is added, and a mask is used in a portion where polarity is reversed. A doped-poly silicon film formed by adding an impurity element imparting one conductivity type, then laminating a poly silicon film containing no impurities, and further adding an impurity element imparting one conductivity type. It is also possible to form the channel structure of the present invention by forming an impurity and adding an impurity element imparting one conductivity type to the portion where the polarity is inverted using a mask.

In any crystallization process of any semiconductor layer, the crystallization rate can be improved by irradiating laser light after the crystallization process by the heat treatment. The material of the amorphous semiconductor film is not limited, and silicon, silicon germanium (Si _1-x Ge _x ; 0 <x <1, typically x
= 0.001-0.05) In addition to alloys, GaAs, In
A compound semiconductor layer of P, SiC, ZnSe, GaN or the like may be used.

As described above, the impurity element imparting one conductivity type is added to the channel regions of the first semiconductor layer and the third semiconductor layer at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ^3. In the channel region of the second semiconductor layer, a channel structure containing an intrinsic or a very small amount of an impurity element imparting one conductivity type is formed.

After that, the semiconductor films 110, 115, 116.
Is divided by etching to form semiconductor films 121 to 123 as shown in FIG.

Next, as shown in FIG. 5B, a second gate insulating film 124 is formed so as to cover the semiconductor films 121 to 123. The second gate insulating film 124 is formed by plasma CV.
It is formed of an insulator containing silicon by the D method or the sputtering method.
Its thickness is 40 to 150 nm.

Next, a conductive film is formed on the second gate insulating film 124 to form a gate electrode and wiring. In this embodiment, the gate electrode is formed by stacking two or more conductive films. The first conductive film 125 formed over the second gate insulating film 124 is formed of a nitride of a high melting point metal such as molybdenum or tungsten, and the second conductive film 126 formed over the first conductive film 125 is formed of a high melting point metal or aluminum. It is formed of a low resistance metal such as copper or copper, or polysilicon. Specifically, as the first conductive film, W, Mo, Ta,
One or more kinds of nitrides selected from Ti are selected and one or more kinds of alloys selected from W, Mo, Ta, Ti, Al, Cu, or n-type polycrystalline silicon is used as the second conductive film. To use. A mask (not shown) is formed on the first conductive film 125 and the second conductive film 126, and then a first etching process is performed to form the second gate electrodes 127 to 130.
To form. FIG. 7B shows a top view thereof.

By the first etching process, a first shape electrode having a taper at the end is formed (not shown).
Next, using the first shape electrode formed by the first etching process as a mask, the first doping process is performed to form the n-type impurity regions of the first concentration in the semiconductor films 121 to 123. The first concentration is 1 × 10 ^{20 to} 1.5 ×
10 ²¹ / cm ³

Next, a second etching process is performed without removing the resist mask. In this etching process, the first shape electrode is anisotropically etched to form a second shape electrode. The width of the second shape electrode is reduced by this etching process, and the end portion of the second shape electrode has the first concentration n.
It is formed so as to be located inside the type impurity region. The length of the LDD is determined by the receding width of this conductive film.

Then, a second doping process is performed to add an n-type impurity element to the semiconductor films 121 to 123. The second-concentration n-type impurity region formed by this doping process has the second shape electrode (second gate electrode) 127 to
It is formed in a self-aligned manner so as to partially overlap with the first conductive film forming 130. Note that the second gate electrode 127
To 130 are first conductive films 127a to 13 of the second shape.
0a, and the second shape second conductive films 127b to 130b.
Consists of. The impurities added by the ion doping method are the first conductive films 127a to 13a forming the second gate electrode.
Since it is added through 0a, the number of ions reaching the semiconductor film is reduced, and the concentration is inevitably low. Its concentration is 1
× a ^{10 17 ~1 × 10 19 / cm} 3.

Next, a mask made of resist is formed to cover the region to be the n-channel TFT, and then a third doping process is performed. By this third doping process, the p-type impurity regions 132 and 135 to which the p-type impurity element having the third concentration is added are formed in the semiconductor film 122. The third concentration of the p-type impurity region is 1.5 × 10 ²⁰
The p-type impurity element is added in a concentration range of up to 5 × 10 ²¹ / cm ³ .

In the above steps, the second TFT of each TFT is
Region of the gate electrode and the semiconductor film to which impurities are added for the purpose of controlling valence electrons, high concentration (1 × 10 ¹⁹ to 1 × 10
²¹ / cm ³ ) with n-type impurities added 131, 133
And regions 134 and 136 to which the n-type impurity element is added at a low concentration (1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ ) are formed. First gate electrodes 103, 104, 106, 108
Then, the second gate electrodes 127 to 129 function as gate electrodes at positions intersecting with the semiconductor film. In addition, the second shape wiring 130 serves as one capacitance wiring of the storage capacitor element (FIG. 5C).

After that, a step of activating the impurity element added to each semiconductor film is performed. This activation is performed using a gas heating type instant thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 400 to 700 ° C., typically 450 to 500 ° C. In addition to this, a laser annealing method using the second harmonic (532 nm) of a YAG laser can be applied. The second harmonic of the YAG laser (532 nm) is used for activation by irradiation with laser light.
Is used to irradiate the semiconductor film with this light. Of course, the same applies not only to the laser light but also to the RTA method using a lamp light source,
The semiconductor film is heated by radiation from a lamp light source from both surfaces of the substrate or one surface (for example, the back surface) of the substrate.

After that, as shown in FIG. 6A, the first interlayer insulating film 1 made of silicon nitride is formed by the plasma CVD method.
37 is formed to a thickness of 50 to 100 nm, heat treatment is performed at 410 ° C. using a clean oven, and hydrogen released from the silicon nitride film hydrogenates the semiconductor film.

Next, a second interlayer insulating film 138 made of an organic insulating material is formed on the first interlayer insulating film 137. The reason for using the organic insulating material is the second interlayer insulating film 1.
38 for flattening the surface. In order to obtain a more complete flat surface, it is desirable that this surface be flattened by the CMP method. When the CMP method is used together, the second interlayer insulating film is a silicon oxide film formed by a plasma CVD method and an SOG (Spin on G) formed by a coating method.
(lass) or PSG can also be used.

After that, an opening is formed in the first gate insulating film, the second gate insulating film, the first interlayer insulating film, or the second gate insulating film and the second interlayer insulating film, and the wiring 139 is formed. ~ 1
43, the pixel electrode 144 is formed. This wiring is formed by stacking a titanium film and an aluminum film (FIG. 6B).
FIG. 8 shows the top view of the active matrix substrate manufactured through the steps up to here.

As described above, the driving circuit 205 including the n-channel TFT 201 and the p-channel TFT 202 and the pixel TFT 20 for switching are formed on the same substrate.
3 and the active matrix substrate including the pixel portion 206 having the storage capacitor element 204 can be realized.

As shown in FIG. 14, a reflective electrode 144 (typically, a conductive film containing Al as a main component as shown in this embodiment) which serves as a reflective electrode is formed on the pixel electrode and a transmissive electrode. A semi-transmissive display device using a transparent electrode 160 (typically, indium tin oxide (ITO)) as an electrode can be used. In order to increase the reflection efficiency of the reflective electrode, the reflective electrode may be formed after the surface of the interlayer insulating film is subjected to a treatment such as etching to form unevenness.

N-channel TFT 20 of drive circuit 205
1 is the first gate electrode 103 and the first gate insulating film 1
09, a first semiconductor layer 112a and a third semiconductor layer 118a containing a p-type impurity element in a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ³ , the first semiconductor layer and the third semiconductor A semiconductor layer including a channel region formed of the substantially intrinsic second semiconductor layer 150, a low-concentration (n-type) impurity region 134, and a high-concentration (n-type) impurity region 131 to be a source region or a drain region between the layers. 121, the second gate insulating film 124, and the second gate electrode 127.

The p-channel TFT 20 of the drive circuit 205
2 is the first gate electrode 104 and the first gate insulating film 1
09, a first semiconductor layer 114 and a third semiconductor layer 120 containing an n-type impurity element in a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ³ , the first semiconductor layer and the third semiconductor A semiconductor layer including a channel region formed of the substantially second semiconductor layer 151, a low-concentration (p-type) impurity region 135, and a high-concentration (p-type) impurity region 132 serving as a source region or a drain region between the layers. 122, second gate insulating film 12
4 and the second gate electrode 128.

The TFT 203 of the pixel portion 206 has a first gate electrode 105, 106 a first gate insulating film 109, p
The first semiconductor layers 112b and 112c and the third semiconductor layers 118b and 118c containing the impurity element of the type at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ³ , the first semiconductor layer and the third semiconductor layer Second semiconductor layer 1 that is substantially intrinsic between the semiconductor layers
A semiconductor layer 123 including a channel region composed of 52, a low-concentration (n-type) impurity region 136, a high-concentration (n-type) impurity region 133 to be a source region or a drain region, and a second
Of the gate insulating film 124 and the second gate electrode 129.

The storage capacitor element 204 of the pixel portion 206 includes the semiconductor layer 123 formed continuously from the semiconductor layer 123 of the pixel TFT, the second shape capacitor wiring 130, and the second gate insulating film 124 serving as a dielectric. Consists of.

In each TFT, the length of the low concentration impurity region (LDD region) in the channel length direction is 0.5 to 2.5 μm, preferably 1.5 μm.
The structure of such an LDD is mainly intended to prevent the deterioration of the TFT due to the hot carrier effect.

A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, etc. can be formed by these n-channel type TFT and p-channel type TFT. In particular, an n-channel T
The structure of FT201 is suitable.

Even if the CMOS structure is not used, the NMO
The present invention can be similarly applied to a circuit based on S or PMOS.

(Embodiment 2) In this embodiment, an example of a process for manufacturing an active matrix type liquid crystal display device using the active matrix substrate manufactured in Embodiment 1 will be described.

After forming up to FIG. 6B, an alignment film 153 is formed as shown in FIG. 9 and a rubbing process is performed. Although not shown, before forming the alignment film 153, an organic resin film such as an acrylic resin film may be patterned to form columnar spacers for holding the substrate distance at desired positions. . Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, the counter electrode 15 is formed on the counter substrate 154.
5 is formed, an alignment film 156 is formed thereon, and rubbing treatment is performed. The counter electrode 155 is made of ITO. Then, the counter substrate 154 on which the seal pattern 157 is formed
Stick together. Then, the liquid crystal material 158 is placed between both substrates.
And then completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. In this way, the active matrix driving liquid crystal display device shown in FIG. 9 is completed.

(Example 3) The present invention can be applied to a TFT having a structure other than the structure of the TFT shown in the embodiment and Example 1. The same reference numerals as those used in FIG. 1 are used.

FIG. 10 shows a first gate electrode 11 on a substrate 10, a first gate insulating film 12 on the first gate electrode 11, and a first semiconductor layer on the first gate insulating film 12. 1
3, the second semiconductor layer 14 on the first semiconductor layer 13, the third semiconductor layer 15 on the second semiconductor layer 14, and the second gate insulating film 18 on the third semiconductor layer 15. A second gate electrode 19 is provided on the second gate insulating film 18. In addition, the first semiconductor layer 13 and the third semiconductor layer 1
In the channel region of No. 5, the impurity element imparting one conductivity type (p-type impurity element in the case of an n-channel TFT and n-type impurity element in the case of a p-channel TFT) is 1 × 10 ¹⁵ to It is added at a concentration of 1 × 10 ¹⁷ / cm ³ .

First semiconductor layer 13 and second semiconductor layer 14
In the third semiconductor layer 15, the impurity element (n having a conductivity type different from the conductivity type added to the channel region (n
In the case of a channel type TFT, it is an n-type impurity element and p
In the case of a channel type TFT, a region to be a source region or a drain region to which a high concentration (1 × 10 ^{20 to} 5 × 10 ²¹ / cm ³ ) of p-type impurity element) is added, and a channel region and a source region or a drain region. Impurity element imparting a conductivity type different from the conductivity type added to the channel region between 16b and 17b has a low concentration (1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ ).
Low concentration impurity region (also called LDD region) added to
It has 16a and 17a.

The first gate electrode 11 is formed so as to overlap the channel region with the first gate insulating film 12 interposed therebetween, and the second gate electrode 19 is formed in the second gate insulating film 1.
8 so as to overlap the LDD regions 16a and 17a.

The structure in which the gate electrode overlaps with the LDD region via the insulating film has a structure of GOLD (Gate-drain Overlappe).
This is known as a d LDD structure, and a high electric field in the vicinity of the drain is relaxed to prevent hot carrier injection and effectively prevent a deterioration phenomenon.

By combining the present invention with the GOLD structure, deterioration due to hot carrier injection can be prevented,
Higher field effect mobility, drain current, lower S value,
A semiconductor device having a high threshold value and high reliability can be realized.

Example 4 In this example, a semiconductor device including a channel region having an energy band structure as shown in FIG. 2A-1 by stacking mixed crystal semiconductors will be described. Note that FIG. 2B-1 is an explanatory diagram of a semiconductor device including a channel region having a conventional energy band structure.

Similar to the first embodiment, the first gate electrode is formed on the substrate, and the first gate insulating film is formed on the first gate electrode.

Next, an Al _x GaAs _1-x film is formed as a first semiconductor layer on the first gate insulating film, and then,
A GaAs film is formed as a second semiconductor layer on the first semiconductor layer. Further, an Al _x GaAs _1-x film is formed as a third semiconductor layer on the second semiconductor layer.

According to the first embodiment, after forming the second gate insulating film and forming the second gate electrode on the second gate insulating film, the n-channel type TFT has a source region or a drain region with n. A semiconductor device having an energy band structure as shown in FIG. 2A-1 is added by adding a p-type impurity element to a source region or a drain region of a p-channel TFT by adding the p-type impurity element. You can

By stacking mixed crystal semiconductor films in this manner, a channel region having an energy band structure as shown in FIG. 2A-1 is formed without stacking semiconductor layers to which an impurity element is added. be able to.

(Embodiment 5) The CMOS circuit and the pixel portion formed by implementing the present invention can be used for an active matrix type liquid crystal display (liquid crystal display device). That is, the present invention can be applied to all electric appliances in which the liquid crystal display device is incorporated in the display section.

Examples of such electric appliances include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, cell phones or electronic books). Etc.) and the like. Examples of those are shown in FIGS.
13 and FIG.

FIG. 11A shows a personal computer, which has a main body 2001, an image input section 2002, and a display section 20.
03, keyboard 2004 and the like.

FIG. 11B shows a video camera, which includes a main body 2101, a display portion 2102, a voice input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
Including 6 etc.

FIG. 11C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205 and the like.

FIG. 11D shows a goggle type display, which includes a main body 2301, a display portion 2302 and an arm portion 230.
Including 3 etc.

FIG. 11E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) in which a program is recorded, and has a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, operation switches 2405 and the like. This player uses a DVD (D
digital Versatile Disc), CD
It is possible to play music, watch movies, play games, and use the internet.

FIG. 11F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown) and the like.

FIG. 12A shows a front type projector including a projection device 2601, a screen 2602 and the like.

FIG. 12B shows a rear type projector, which includes a main body 2701, a projection device 2702 and a mirror 270.
3, screen 2704 and the like.

Note that FIG. 12C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 12A and 12B. Projection device 2601, 27
02 is a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280.
9, a projection optical system 2810. Projection optical system 28
Reference numeral 10 is composed of an optical system including a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited and may be, for example, a single-plate type. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting the phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 12D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 12C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813, and a lens array 2813.
814, a polarization conversion element 2815, and a condenser lens 2816. The light source optical system shown in FIG. 12D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, the projector shown in FIG. 12 shows a case where a transmissive electro-optical device is used, and an application example of a reflective liquid crystal display device is not shown.

FIG. 13A shows a mobile phone, which is 3001.
Is a display panel and 3002 is an operation panel. The display panel 3001 and the operation panel 3002 are connected to each other by the connecting portion 3
Connected at 003. The angle θ between the surface of the connection panel 3003 on which the display portion 3004 of the display panel 3001 is provided and the surface of the operation panel 3002 on which the operation keys 3006 are provided can be arbitrarily changed. Furthermore, a voice output unit 3005 and operation keys 300
6, a power switch 3007, and a voice input unit 3008.

FIG. 13B shows a portable book (electronic book) including a main body 3101, display portions 3102 and 3103, a storage medium 3104, operation switches 3105, and an antenna 3106.
Including etc.

FIG. 13C shows a display, which includes a main body 3201, a support base 3202, a display portion 3203, and the like.
The display of the present invention is particularly advantageous when it has a large screen, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electric appliances in all fields.

(Embodiment 6) In this embodiment, the dual of the present invention is used.
The gate structure (configuration a) and the general Dual Gate structure (configuration b) were used to simulate gm, drain current and the like. It is assumed that the transistors of configurations a and b have L / W = 10/8 μm and a single drain structure. Further, in the configuration a, the film thickness of the first semiconductor film and the third semiconductor film is 10 nm, and the film thickness of the second semiconductor film is 3 nm.
0 nm, and 2 × 10 ¹⁶ / cm ³ of boron is added to the channel regions of the first semiconductor film and the third semiconductor film.
Channel region of the semiconductor film of
10 ¹⁰ / cm ³ ). Further, in the configuration b, the thickness of the semiconductor film is set to 50 nm, and boron is added to the channel region by 2 × 10 5.
¹⁶ / cm ^{3 was} added. The results of these simulations are shown in FIGS. 15 (A) and (B).

FIG. 15A shows a graph (a) showing gm (transconductance) and a graph (b) showing Vg-Id characteristics. It can be seen from the graph (a) that the configuration a has a higher gm than the configuration b. This gm has a proportional relationship with the mobility of the transistor, and it can be said that the mobility of the configuration a is larger than that of the configuration b.

Further, from the graph (b), it can be seen that the configuration a has a higher Id (drain current) than the configuration b in the saturation region. The configuration a having a high drain current can make the channel region smaller than that of the configuration b capable of obtaining the same drain current, and enables high integration of the transistor.

FIG. 15B shows a graph showing Vd-Id characteristics. It can be clearly seen from FIG. 15B that the configuration a has a higher Id (drain current) than the configuration b. The configuration a having a high drain current can make the channel region smaller than that of the configuration b capable of obtaining the same drain current, and enables high integration of the transistor.

As described above, according to the present invention, a transistor with improved mobility and drain current can be obtained. Such a transistor having improved mobility and drain current is preferably used for a driver circuit.

[0102]

When a voltage higher than the threshold voltage that causes an inversion state is applied to the TFT having the structure of the present invention, the first semiconductor to which the impurity element imparting one conductivity type which serves as a potential barrier is added is added. Since the inversion layer is widely formed in the intrinsic second semiconductor layer formed between the layer and the third semiconductor layer, the region in which carriers flow is expanded, the drain current is increased, and the subthreshold coefficient (S
Value) becomes smaller. It can be said that an element having a small S value is an ideal switch having a sharp rising edge.

Further, since the main inversion layer is formed in the second semiconductor layer by forming the channel region as described above, hot carriers generated in the second semiconductor layer are scattered at the interface of the insulating film. Never injected. Therefore, the field-effect mobility is improved, and the potential generated by the difference in Fermi energy between the first semiconductor layer and the second semiconductor layer or the second semiconductor layer and the third semiconductor layer surrounds the second semiconductor layer. Therefore, it is possible to prevent the hot carriers generated in the second semiconductor layer from being scattered and injected into the insulating film, and the influence of the hot carrier deterioration on the drain current can be reduced.

As described above, according to the present invention, a semiconductor device having excellent reliability and electric characteristics can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a TFT of the invention.

FIG. 2 is a diagram showing an energy band structure of a channel region of the present invention.

FIG. 3 is a diagram showing an example of implementation of the present invention.

FIG. 4 is a diagram showing an example of implementation of the present invention.

FIG. 5 is a diagram showing an example of implementation of the present invention.

FIG. 6 is a diagram showing an example of implementation of the present invention.

FIG. 7 is a diagram showing an example of implementation of the present invention.

FIG. 8 is a diagram showing an example of implementation of the present invention.

FIG. 9 is a diagram showing an example of implementation of the present invention.

FIG. 10 is a diagram showing an example of implementation of the present invention.

FIG. 11 is a diagram showing an example of an electric appliance.

FIG. 12 is a diagram showing an example of an electric appliance.

FIG. 13 is a diagram showing an example of an electric appliance.

FIG. 14 is a diagram showing an example of implementation of the present invention.

FIG. 15 is a graph showing characteristics of the TFT of the invention.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 613A 27/08 321G 321C (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21 / 336 H01L 21/8238 H01L 27/08 H01L 27/092 G02F 1/1368

Claims (13)

(57) [Claims] 1. A first gate electrode, a first gate insulating film provided on the first gate electrode, and a source region and a drain region provided on the first gate insulating film. A semiconductor film and a second film provided on the semiconductor film
A gate insulating film and a second gate electrode provided on the second gate insulating film, the lower part of the channel forming region of the semiconductor film being in contact with the first gate insulating film. The region and the upper region in contact with the second gate insulating film include an impurity element imparting a conductivity type different from the conductivity type of the source region and the drain region, and a region between the upper region and the lower region is ,
A thin film transistor comprising an intrinsic or impurity element imparting the same conductivity type as that of the upper and lower regions at a concentration of 1 × 10 ¹⁵ / cm ³ or less. 2. A first gate electrode, a first gate insulating film provided on the first gate electrode, and a first semiconductor film provided on the first gate insulating film. The first
A second semiconductor film provided on the semiconductor film of
A third semiconductor film provided on the semiconductor film of
A thin film transistor having a second gate insulating film provided on the semiconductor film, and a second gate electrode provided on the second gate insulating film, wherein the channel of the first semiconductor film is provided. The formation region and the channel formation region of the third semiconductor film contain an impurity element imparting the same conductivity type at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ³ , and the second region
The channel formation region of the semiconductor film is intrinsic or 1 × 10 ¹⁵
A thin film transistor comprising an impurity element imparting the conductivity type at a concentration of / cm ³ or less. 3. A first gate electrode, a first gate insulating film provided on the first gate electrode, and a first semiconductor film provided on the first gate insulating film. The first
A second semiconductor film provided on the semiconductor film of
A third semiconductor film provided on the semiconductor film of
A second gate insulating film provided on the semiconductor film, a second gate electrode provided on the second gate insulating film, the first semiconductor film, the second semiconductor film, and the third semiconductor film.
A source region, a drain region, and a channel formation region provided in the semiconductor film, wherein the channel formation region of the first semiconductor film and the channel formation region of the third semiconductor film are 1 × 10. ¹⁵ ~ 1 x
The channel formation region of the second semiconductor film contains an impurity element imparting the same conductivity type at a concentration of 10 ¹⁷ / cm ³ and imparts the conductivity type at an intrinsic or concentration of 1 × 10 ¹⁵ / cm ³ or less. A thin film transistor comprising an impurity element. 4. A first gate electrode, a first gate insulating film provided on the first gate electrode, and a first semiconductor film provided on the first gate insulating film. The first
A second semiconductor film provided on the semiconductor film of
A third semiconductor film provided on the semiconductor film of
An n-channel type thin film transistor and a p-channel type thin film transistor, each having a second gate insulating film provided on the semiconductor film and a second gate electrode provided on the second gate insulating film. An impurity imparting p-type at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ³ in the channel forming region of the first semiconductor film and the channel forming region of the third semiconductor film in the n-channel thin film transistor. The channel forming region of the second semiconductor film contains an impurity element that imparts p-type intrinsic or at a concentration of 1 × 10 ¹⁵ / cm ³ or less, and the first semiconductor in the p-channel thin film transistor containing an impurity element channel forming region and a channel forming region of the third semiconductor film which imparts n-type at a concentration of ^{1 × 10 15 ~1 × 10 17} / cm 3 of membrane And the channel formation region of the second semiconductor film, a thin film transistor which comprises an impurity element imparting intrinsic or 1 × 10 ¹⁵ / cm ³ n-type at a concentration. 5. A first gate electrode, a first gate insulating film provided on the first gate electrode, and a first semiconductor film provided on the first gate insulating film. The first
A second semiconductor film provided on the semiconductor film of
A third semiconductor film provided on the semiconductor film of
A second gate insulating film provided on the semiconductor film, a second gate electrode provided on the second gate insulating film, the first semiconductor film, the second semiconductor film, and the third semiconductor film.
An n-channel thin film transistor and a p-channel thin film transistor having a source region, a drain region, and a channel forming region provided in the semiconductor film, respectively, the channel forming region of the first semiconductor film in the n-channel thin film transistor. And the channel formation region of the third semiconductor film is 1 × 10 ¹⁵ to 1 × 10
The channel formation region of the second semiconductor film contains an impurity element imparting p-type at a concentration of ¹⁷ / cm ^{3 and} the impurity element imparting intrinsic or p-type concentration is 1 × 10 ¹⁵ / cm ³ or less. And a channel forming region of the first semiconductor film and the third semiconductor film in the p-channel thin film transistor is an impurity element imparting n-type at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ^3. And the channel formation region of the second semiconductor film contains an impurity element imparting intrinsicity or n-type at a concentration of 1 × 10 ¹⁵ / cm ³ or less. 6. A first gate electrode, a first gate insulating film provided on the first gate electrode, and a first semiconductor film provided on the first gate insulating film. The first
A second semiconductor film provided on the semiconductor film of
A third semiconductor film provided on the semiconductor film of
A second gate insulating film provided on the semiconductor film, a second gate electrode provided on the second gate insulating film, the first semiconductor film, the second semiconductor film, and the third semiconductor film.
N-channel thin film transistor and p-type thin film transistor having a source region, a drain region and a channel forming region provided in the semiconductor film, and a low concentration impurity region provided between the source region and the drain region and the channel forming region, respectively. A channel type thin film transistor, wherein n
The channel formation region of the first semiconductor film and the channel formation region of the third semiconductor film in the channel type thin film transistor are doped with an impurity element imparting p-type at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ^3. And a channel formation region of the second semiconductor film, which contains an impurity element imparting p-type intrinsic or at a concentration of 1 × 10 ¹⁵ / cm ³ or less, and the first semiconductor film in the p-channel thin film transistor; The channel formation region of the third semiconductor film has a size of 1 × 1.
The channel formation region of the second semiconductor film contains an impurity element imparting n-type at a concentration of 0 ¹⁵ to 1 × 10 ¹⁷ / cm ³ and 1 × 10 ¹⁵ impurity element imparting intrinsic or n-type conductivity.
A thin film transistor, which is characterized by containing at a concentration of / cm ³ or less. 7. The thin film transistor according to claim 6, wherein the first gate electrode overlaps the low concentration impurity region with the first gate insulating film interposed therebetween. 8. The thin film transistor according to claim 6, wherein the second gate electrode overlaps the low concentration impurity region through the second gate insulating film. 9. The low-concentration impurity region according to claim 6, wherein the low-concentration impurity region contains an impurity element of one conductivity type added at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. Characteristic thin film transistor. 10. A first gate electrode, a first gate insulating film provided on the first gate electrode, and a first semiconductor film provided on the first gate insulating film. A second semiconductor film provided on the first semiconductor film, a third semiconductor film provided on the second semiconductor film, and a second semiconductor film provided on the third semiconductor film. A thin film transistor having a gate insulating film and a second gate electrode provided on the second gate insulating film, wherein the first semiconductor film and the third semiconductor film have AlGaAs, The thin film transistor, wherein the second semiconductor film contains GaAs. 11. A first gate electrode, a first gate insulating film provided on the first gate electrode, and a first semiconductor film provided on the first gate insulating film. A second semiconductor film provided on the first semiconductor film, a third semiconductor film provided on the second semiconductor film, and a second semiconductor film provided on the third semiconductor film. A gate insulating film, a second gate electrode provided on the second gate insulating film, the first semiconductor film, the second semiconductor film, and the third semiconductor film.
A thin film transistor having a source region, a drain region, and a channel formation region provided in the semiconductor film, wherein the first semiconductor film and the third semiconductor film are A
A thin film transistor having 1 GaAs and the second semiconductor film having GaAs. 12. The method according to claim 1, wherein the first gate electrode and the second gate electrode are one or more selected from tungsten, molybdenum, tantalum and titanium. A thin film transistor, comprising: 13. The one conductivity type according to claim 3, wherein the source region or the drain region is added at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²¹ / cm ³ . A thin film transistor comprising an impurity element.