JP2000014127A - Gate drive circuit for voltage-driven semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower a spike voltage at turning off, and to shorten the operation starting time by clamping a gate voltage at turning off to a voltage between a reverse bias voltage and a threshold voltage only for a constant time, and returning it to the reverse bias voltage after that. SOLUTION: If a signal changes from an on-signal to an off-signal, a transistor TR4 is turned on instantly, and a current flows between the base and the emitter of a transistor TR3 and turns it on. Following this, charging of the capacitor (input capacity) between the gate and the emitter of an insulated gate bipolar transistor IGBT is started toward a reverse bias voltage, and the insulated gate bipolar transistor IGBT starts its turn-on operation. Then when it reaches the zener voltage VZD1 of a zener diode ZD1, the transistor TR3 is turned off, and the charging into the input capacity of the insulated gate bipolar transistor IGBT is stopped and the voltage between the gate and the emitter is clamped. Here, the value of the zener voltage VZD1 is set to a value, which makes the gate voltage a value between a threshold voltage and the reverse bias voltage. If the transistor TR4 is turned off, if time set by a timer passes after inputting of an off-signal, a gate voltage clamping circuit GC is cut off, and the insulated gate bipolar transistor IGBT is turned off by the reverse bias voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a gate drive circuit for a voltage-driven semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) constituting a power converter.

[0002]

2. Description of the Related Art FIG.
A conventional example of a voltage source inverter using a BT is shown. This includes a DC voltage source Ed, a smoothing capacitor C _F , an IGBT
It comprises elements Q11, Q12, Q21 and Q22. For example, turning on Q12 and Q21 produces a positive DC voltage.
Further, by turning on Q11 and Q22, a negative DC voltage is output. By alternately outputting the output voltage from positive to negative, an AC voltage is output, whereby the load current I _L is applied to the load resistance _RL and the load reactor _L.
Is flowing.

FIG. 6 is an equivalent circuit diagram when Q21 switches in the voltage source inverter of FIG.
Denotes a wiring inductance of the circuit, and FDW11 denotes a free wheel diode built in Q11. FIG.
And the collector-emitter voltage V when the Q21 is turned off.
Shows the waveform of the _CE and the collector current I _C. In FIG. 6, when Q21 is on, Ed → Lm → _RL → L → Q
A current flows through a path from 21 to Ed. When Q21 is turned off, the collector of Q21 - emitter voltage V _CE rises as shown in FIG. 7. V _CE reaches DC voltage Ed and FDW
By 11 is turned on, the load current I _L FDW1
Commutated to 1, the collector current I _C decreases as shown in FIG. 7. The induced voltage V _Lm (= ΔV _SP ) is applied to the circuit wiring inductance Lm by the current change rate (decrease rate) -di / dt.
As shown in FIG. 7, E21 is generated for Q21.
d + ΔV _SP is applied. Spike voltage ΔV _SP is Lm ×
(−di / dt), and to reduce ΔV _SP , the circuit wiring inductance Lm or the current change rate −
It is necessary to reduce di / dt. However, there is a restriction (limitation) on the circuit wiring to reduce the circuit wiring inductance Lm.
Therefore, to reduce ΔV _SP , the current change rate −di
It is a general method to reduce / dt.

FIG. 8 shows a conventional example of a method for reducing the current change rate -di / dt. This shows an IGBT gate drive circuit, and when turned off, M-N1 of FIG.
The power supply for off-gate is connected between 5. At that time, the current is changed from the gate power supply (M) to the IGBT gate input capacitance (IGB
It flows through the route of T gate-emitter) → Rg (off) → TR2 → gate power supply (N15). When this current flows, the IGBT input capacitor is charged with a reverse bias voltage, and the IGBT is turned off. At this time, by increasing the gate resistance Rg (off), the IGB
By delaying the charging time for the T input capacitance, the gate voltage can be gradually changed. Thereby, IGB
The current change rate -di / dt of T is reduced, and as a result, the spike voltage ΔV _SP can be reduced as shown by the dotted line in FIG. The gate voltage can be changed gradually by reducing the voltage value of the off gate power supply and decreasing the reverse bias voltage. Because of this, IG
The current change rate -di / dt of the BT is reduced, and the spike voltage ΔV _SP can be reduced.

[0005]

As described above, IGB
At the time of T-turn-off, the spike voltage ΔV _SP can be reduced by increasing the gate resistance Rg (off), but the time delay from the input of the on / off signal to the operation of the IGBT increases as shown in FIG. There is a problem.
The spike voltage ΔV _SP can also be reduced by making the reverse bias voltage shallow, but if the reverse bias voltage is shallow, the gate voltage easily exceeds the threshold voltage of the IGBT due to various noises and malfunctions of the gate drive circuit. So I
There is also a problem that the GBT is easily turned on (malfunction). SUMMARY OF THE INVENTION It is therefore an object of the present invention to reduce a spike voltage when an element is turned off, to shorten the time from when an on / off signal is input to when the IGBT operates, and to prevent malfunction.

[0006]

According to the first aspect of the present invention, there is provided a control apparatus for controlling the switching of a voltage-driven semiconductor device in a power conversion device comprising the voltage-driven semiconductor device. A driving circuit for driving the voltage-driven semiconductor device based on a signal from the control device, and a clamp circuit for clamping a gate voltage when the voltage-driven semiconductor device is turned off for a predetermined period, wherein the voltage-driven semiconductor device is provided. The gate voltage when the element is turned off is
The clamp circuit clamps the voltage between the reverse bias voltage and the threshold voltage for a certain period of time, and thereafter returns to the reverse bias voltage, thereby reducing the spike voltage generated at the time of turning off the voltage-driven semiconductor element and controlling the control signal. Thus, the time from when the element is turned off to when the element is turned off is shortened. According to the first aspect of the present invention, the predetermined time during which the gate voltage is clamped is set as a spike voltage generation period of the voltage-driven semiconductor device, and malfunction can be prevented during a period in which the device is normally turned off. 2).

[0007]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a specific example of a gate voltage clamp circuit used in FIG. That is, the present invention is configured by adding a gate voltage clamp circuit GC to the conventional example. As the gate voltage clamp circuit GC, for example, as shown in FIG.
A circuit including the ET element TR4, the Zener diode ZD1, the capacitor C1, the resistors R1, R2, R3, the timer TM, and the like can be provided.

Next, the operation of the circuit of FIG. 2 will be described with reference to FIG. It is assumed that a power supply of 15 V is connected as a gate power supply for turning off, and the reverse bias voltage is -15 V. Now, when the on / off signal in FIG. 3 changes from on to off, TR4 immediately turns on as shown, and a current flows between the base and the emitter of TR3 to turn it on. When TR3 is turned on, the capacitor (input capacitance) between the gate and the emitter of the IGBT starts charging toward the reverse bias voltage, and the IGBT starts to turn off. Then, the Zener voltage V _{ZD1 of ZD1}
Is reached, TR3 is turned off, charging of the input capacitance of the IGBT is stopped, and the voltage between the gate and the emitter is clamped. Here, the value of the Zener voltage V _ZD1 is set to a value such that the gate voltage is between the threshold voltage and the reverse bias voltage.

A timer circuit TM is connected to the gate of TR4, so that TR4 turns off after a timer period from the input of the OFF signal. When TR4 is turned off, the gate voltage clamp circuit GC is disconnected, and IGB
The gate-emitter voltage V _GE of T is the reverse bias voltage (−
15V), and the IGBT is completely turned off. As described above, when the IGBT is turned off, the gate voltage of the IGBT is clamped to a voltage value between the reverse bias voltage and the threshold voltage as shown in FIG. (See dotted line), the input capacitance of the IGBT is more slowly charged, and therefore, as shown by the solid line in FIG. 3, the current change rate -di / dt of the IGBT is reduced, and the spike voltage is suppressed. Become.

FIG. 4 is a waveform diagram for comparing and explaining the case where the spike voltage is suppressed by the present invention and the case of the conventional method which suppresses the spike voltage by adjusting the gate resistance which is generally used conventionally. As shown in the figure,
The time from the input of the on / off signal to the start of the turn-off operation of the IGBT is T according to the present invention.
1. In the case of the conventional method, T2 is satisfied, and T1 <T2. Therefore, it can be seen that the increase of the operation delay time can be suppressed in the case of the present invention.

Further, if the clamp time of the gate voltage is the spike voltage generation period of the voltage-driven semiconductor element, it is possible to prevent the IGBT from malfunctioning when it is off. Further, even if the IGBT is turned on due to a malfunction of the IGBT during the gate voltage clamp period, the IGBT of the opposite arm is turned off during the dead time period.
There is no risk of arm short-circuit.

[0012]

According to the present invention, the gate voltage clamp circuit is provided to clamp the gate voltage for a certain period during the turn-off operation, and thereafter, to restore the IGBT to the original state.
Without slowing down the switching operation and increasing the delay time from the input signal to the switching operation,
Spike voltage can be suppressed. In addition, by limiting the fixed time for clamping the gate voltage to the spike voltage generation period of the voltage-driven semiconductor device, not only the effect of suppressing the spike voltage but also preventing the arm short circuit due to the IGBT turn-off and the IGBT malfunction during the normal off-time. There is also the advantage that it can be done.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the gate voltage clamp circuit of FIG.

FIG. 3 is an operation explanatory diagram of FIG. 2;

FIG. 4 is an explanatory diagram for explaining the effect of suppressing the spike voltage by comparing the effect according to the present invention with the conventional method.

FIG. 5 is a circuit diagram showing a general example of a voltage-source inverter main circuit using an IGBT.

FIG. 6 is an equivalent circuit diagram for explaining a case where an element Q21 operates in FIG.

FIG. 7 is an operation explanatory diagram of FIG. 6;

FIG. 8 is a circuit diagram showing a conventional example of a gate drive circuit.

FIG. 9 is an operation explanatory diagram of FIG. 8;

[Explanation of symbols]

IF: Interface circuit, GC: Gate voltage clamp circuit, TM: Timer, TR1 to TR3: Transistor, TR4: FET, ZD1: Zener diode, Q
11 to Q22, IGBT: switch element (insulated gate bipolar transistor), R: resistor, C: capacitor,
Ed: DC voltage source, L: Reactor.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5H740 AA04 BA11 BB05 BB08 BB10 BC01 BC02 HH06 JA01 JB02 5J055 AX02 AX22 AX56 BX16 CX07 DX09 EX02 EX06 EX11 EY01 EY10 EY13 EY17 EY21 EZ16 GX01 GX04

Claims (2)

[Claims] 1. A control device for controlling the switching of the voltage-driven semiconductor device, and a drive for driving the voltage-driven semiconductor device based on a signal from the control device. A circuit and a clamp circuit for clamping a gate voltage at the time of turn-off of the voltage-driven semiconductor element for a certain period of time. The spike voltage generated at the time of turning off the voltage-driven semiconductor device is reduced by clamping the voltage to a voltage for a certain period of time and thereafter returning to the reverse bias voltage, and the time from receiving the control signal until the device starts turning off. A gate drive circuit for a voltage-driven semiconductor device, characterized by shortening. 2. The device according to claim 1, wherein the predetermined time for clamping the gate voltage is a spike voltage generation period of the voltage-driven semiconductor device, and a malfunction is prevented during a period when the device is normally off. Gate drive circuit for a voltage-driven semiconductor device.