JP3417859B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a contact hole connecting a bit line of a semiconductor memory device having a trench type element isolation region and a drain diffusion layer of a MOS transistor. And its manufacturing method.

[0002]

2. Description of the Related Art In a conventional semiconductor memory device, a plurality of MOS transistors are regularly arranged with the lower part of each bit line arranged in parallel as an element region, and the bit line is formed between adjacent bit lines. Some memory cell arrays are formed by forming element isolation regions extending in parallel and isolating the element regions from each other.

In recent years, a shallow trench isolation (hereinafter referred to as STI) in which a trench is formed in a semiconductor substrate and is filled with an insulating material such as a silicon oxide film for planarization is used as a method of forming an element isolation region. The so-called technology has come into wide use.

In the memory cell array, writing and reading of stored data are performed by a large number of MOs connected to bit lines.
Since these are done through the S-transistor, these MOS
The contact hole connecting the current terminal of the transistor and the bit line is strictly required to have low resistance and little variation, and to have high yield and high reliability.

For this reason, the widths of the source / drain diffusion layers for supplying the operating current to the MOS transistors are adjacent to each other.
Since the device is designed to be as large as possible by using the entire width of the element region separated by the TI region, both ends of the source / drain diffusion layer are usually in contact with the sidewalls of the STI region.

The structure of a conventional contact hole for connecting a bit line and a drain diffusion layer of a MOS transistor and its problem will be described in detail with reference to FIG. 7, taking a NAND type nonvolatile semiconductor memory device as an example.

FIG. 7A is an enlarged plan view of the vicinity of the bit line contact of the memory cell array in the NAND type nonvolatile semiconductor memory device. 1 indicates a bit line contact, and 2 indicates a width of the bit line contact. 3 is BL1,
The bit line is composed of BL2 and BL3, and the surface of the silicon substrate thereunder is used as an element region 4 for forming an active element such as a MOS transistor. The bit line contact width 2 is designed to be larger than the width of the element region 4 in order to allow a mask alignment margin with the drain diffusion layer formed to be as large as possible using the entire width of the element region 4.

Along the bit lines 3, element isolation regions 5 having an STI structure for isolating the element regions 3 from each other are formed. As shown above and below the bit line contact 1 in FIG.
A select line 6 composed of SG1 and SG2 for selecting a NAND cell and a word line 7 of a memory cell composed of WL1 and WL2.
Are formed respectively.

Gate electrodes of the select transistor and the memory cell transistor are formed as a part of the word line in the region where the bit line 4 and the select line 6 and the word line 7 intersect, and the element region 4 between the word lines 7 is formed. In addition, the source / drain diffusion layers of these MOS transistors are formed in a self-aligned manner using the gate electrode as a mask. The bit line contact 1 in FIG. 7A is a contact that connects the bit line 3 to the drain diffusion layers of the select transistors arranged above and below in the drawing.

Next, the BB disconnection of the bit line contact 1 is shown in FIG. The cross-sectional structure of the bit line contact 1 includes a p-type silicon substrate 10, an element region 4 formed of a part of the upper surface of the p-type silicon substrate 10, an STI type element isolation region 5, a nitride film 15, and a BPSG ( Boro-Phospho
-Silicate-Glass) film 16.

For the bit line contact 1, the PSG film 16 and the nitride film 15 thereunder are removed to form a contact hole 17.
By burying a conductive material such as conductive polycrystalline silicon or tungsten therein, the drain diffusion layer formed in the element region 4 and the bit line 3 are connected.

However, RIE (Reactive Ion Etching)
Contact hole 17 using a dry etching method such as
When forming the, on the shoulder portion of the element isolation region 5 of STI,
The local etching 17a as shown in FIG. 7B is generated, and the shape of the element isolation region 5 is destroyed. For this reason, the pn junction surface of the n ⁺ type drain diffusion layer formed in the element region 4 with the p type silicon substrate 10 is exposed, so if the contact hole 17 is filled with a conductive material for connection, the junction surface leaks. Electric current is generated.

Next, with reference to FIGS. 8A to 8D, problems in the conventional manufacturing process that occur in the process of forming the contact hole 17 will be described in more detail. First, as shown in FIG. 8A, after the STI type element isolation region 5 is formed on the p type silicon substrate 10 by a usual method, the MOS is formed.
A gate oxide film 11 of the transistor and a gate electrode material 12 made of conductive polycrystalline silicon are formed on the entire surface of the element region 4.

Next, a resist mask is formed by a photo-etching method, and the unnecessary conductive polycrystalline silicon film other than the gate electrode portion is removed by a CDE (Chemical Dry Etching) method to remove the gate electrode (not shown). Pattern).

Next, by ion-implanting and diffusing n-type impurities into the surface of the element region 4 through the gate oxide film 11 using the gate electrode as a mask, an n ⁺ -type source / drain diffusion layer (see FIG. (Not shown) is formed. Here, the n ⁺ type means a high concentration n type.

In this step, after changing the surface of the element region 4 into an n ⁺ type drain diffusion layer, the gate oxide film 11 on the drain diffusion layer is removed as shown in FIG. 8B.

Next, as shown in FIG. 9C, a silicon nitride film 15 serving as an etching stopper and a thick BPSG film 16 are deposited to flatten the surface. The thick BPSG film 16 is used as an interlayer insulating film when arranging the bit lines 3 (not shown) in the direction perpendicular to the paper surface.

Next, as shown in FIG. 9D, the BPSG film 16 and the silicon nitride film 15 are selectively etched by using a resist pattern and the RIE method, etc., to thereby form the bit line 3 and the device. A contact hole 17 connecting to the n ⁺ type drain diffusion layer in the region 4 is formed.

At this time, the nitride film 15 is a thick BPSG film 1.
When etching 6 is performed, it acts as an etching stopper that protects the surface of the element region and the buried insulating material of the element isolation region 5. That is, the nitride film 15 is provided in order to prevent the thick BPSG film 16 from being etched once by the nitride film 15 and prevent the surface of the element region 4 and the shoulder portion of the element isolation region 5 from being etched. .

Next, if the thin nitride film 15 is etched under the etching conditions for the nitride film, the contact hole 1
When forming 7, the surface of the element region 4 and the buried insulating material of the element isolation region 5 can be protected.

However, the insulating material filling the element isolation region has a step on the surface of the element region 4 by the thickness of the nitride film used as the CMP stopper in the surface flattening process by CMP (Chemical Mechanical Polish). Cause Therefore, the thin nitride film 15 used as an etching stopper for forming the contact hole 17 is formed as shown in FIG.
Thus, the surface of the substrate is coated over the surface step shown in (b).

At this time, since abnormal growth of the nitride film 15 occurs at the corner portions on both shoulders of the element isolation region 5, the etching rate of the nitride film becomes high at the corner portions, so that it cannot serve as a stopper. That is, thick B
When the PSG film 16 is etched, the nitride film 14 covering the shoulder portion of the element isolation region 5 disappears, and both ends of the STI type element isolation region 5 are locally deepened as shown in 17a of FIG. 8D. Of the element isolation region 5 is destroyed by etching.

As described above, the drain diffusion layer formed on the surface of the element region 4 and the bit line 3 are formed by filling the contact hole 17 with a connecting material such as conductive polycrystalline silicon or tungsten. At this time, the conductive material filling the part of the local etching 17a short-circuits the pn junction formed between the n ⁺ drain diffusion layer on the surface of the element region 4 and the p-type silicon substrate 10. That was the cause of the junction leak.

As is clear from the above description, the problem of shape destruction due to local etching of the element isolation region is as shown in FIG.
As shown in (a), it becomes important when the width 2 of the bit line contact is larger than the width 4 of the element region (including the case of the diameter). Therefore, this problem is due to the progress of device miniaturization
The smaller the width of the drain contact (equal to the bit line width) on the device region, the more important it becomes.

[0025]

As described above, the structure of the bit line contact of the conventional semiconductor memory device and the method of manufacturing the same are provided as an etching stopper when forming the contact hole of the bit line in the interlayer insulating film. Even if the nitride film is used, there is a problem that a portion where the element isolation region and the element region are in contact with each other is locally deeply etched, causing shape breakdown of the element isolation region and causing a leak current of the drain pn junction. .

The present invention has been made to solve the above-mentioned problems. Even if the width of the bit line contact is larger than the width of the element region, the element isolation region is not locally etched, and the high isolation is achieved. An object is to provide a reliable semiconductor memory device with a high manufacturing yield.

Further, the present invention is generally applied to formation of a contact hole for connecting a source / drain diffusion layer of a MOS transistor on a miniaturized element region and an upper layer wiring in a semiconductor device having an STI type element isolation region. The purpose is to do.

[0028]

A semiconductor device and a method of manufacturing the same according to the present invention are particularly applicable to a bit line contact for connecting a bit line and a drain diffusion layer of a MOS transistor in a semiconductor memory device having an element isolation region of STI structure. In order to improve the manufacturing yield and reliability of the device, when forming a contact hole for a bit line contact, a pad made of a conductive polycrystalline silicon film larger than the width of the element region is previously formed on the drain diffusion layer of the element region. Formed,
It is characterized in that the drain diffusion layer and the bit line are connected using the contact hole reaching the polycrystalline silicon pad.

As described above, by making the width of the polycrystalline silicon pad larger than the width of the drain diffusion layer in the element region, the STI type element isolation region generated when the width of the contact hole is larger than the width of the element region. It is possible to prevent shape destruction.

Specifically, the semiconductor device of the present invention comprises an element isolation region in which a trench formed in the semiconductor substrate is filled with an element isolation insulating material, and the surface of the semiconductor substrate separated by the element isolation region. In a semiconductor device including an element region and a source / drain diffusion layer in the element region, a contact hole connecting any one of the source / drain diffusion layer and a wiring on an interlayer insulating film is one of the source / drain diffusion layer. of the conductive pads covering the front surface and the edge of the isolation region, provided on the bottom of the contact hole, the conductive pad, the isolation
In the area, the adjacent conductive pads are slits.
It is characterized in that they are separated from each other by a separation groove .

Preferably , the conductive pad is made of conductive polycrystalline silicon, the wiring is a bit line of a semiconductor memory device, and the bit line and the conductive pad covering the drain diffusion layer are: It is characterized in that the connection is made using the contact hole.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a trench in a semiconductor substrate, a step of forming an element isolation region by embedding an element isolation insulating material in the trench, and a step of separating the element isolation region. A step of depositing a conductive material for a gate electrode on a device region formed of the surface of the semiconductor substrate via a gate insulating film, and adjacent to the gate electrode when patterning the conductive material for a gate electrode as a gate electrode. Removing the conductive material for the gate electrode covering the region where the source and drain diffusion layers are formed on the device region, and forming the source and drain diffusion layers adjacent to the gate electrode,
Removing a gate insulating film covering the source and drain diffusion layers, and depositing a series of conductive pad materials covering either of the source and drain diffusion layers and the element isolation regions arranged on both sides thereof. And a step of forming a slit-shaped isolation groove reaching the surface of the element isolation region in the electrically conductive pad material deposited on the element isolation region, so that the series of conductive pad material is formed into the source and drain diffusion layers. A step of separating the conductive pads into individual conductive pads, a step of covering the conductive pads with a nitride film, a step of further covering the nitride film with a BPSG film, and a step of covering the nitride film with the nitride film as a stopper on the BPSG film. The step of forming a contact hole and the etching of the nitride film exposed on the bottom surface of the contact hole to remove the bottom of the contact hole. The exposed surface of the conductive pad, characterized in that it comprises the step of connecting the conductive pad and the metal wiring in the contact hole.

Preferably, in the method of manufacturing a semiconductor device of the present invention, the PSG film is entirely overlaid after the step of separating the series of conductive pad materials into individual conductive pads covering either the source or drain diffusion layer. And exposing the surface of the conductive pad to the bottom surface of the contact hole by forming a contact hole in the PSG film, and then connecting the conductive pad and the metal wiring in the contact hole. It is characterized by including and.

Also preferably, the method of manufacturing a semiconductor device according to the present invention comprises a step of removing the conductive material for a gate electrode covering a region where a source and drain diffusion layer is formed on the element region adjacent to the gate electrode. Subsequently, the step of removing the gate insulating film covering the source and drain diffusion layers is performed.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a trench in a semiconductor substrate, a step of forming an element isolation region by filling the trench with an element isolation insulating material, and a step of separating the element isolation region. A step of depositing a conductive material for a gate electrode on a device region formed of the surface of the semiconductor substrate via a gate insulating film, and adjacent to the gate electrode when patterning the conductive material for a gate electrode as a gate electrode. Removing the conductive material for the gate electrode covering the region where the source and drain diffusion layers are formed on the device region, and forming the source and drain diffusion layers adjacent to the gate electrode,
A series of conductive pad materials is provided so as to cover one of the source and drain diffusion layers and the element isolation regions arranged on both sides of the source and drain diffusion layer through the gate insulating film remaining on the source and drain diffusion layers. depositing, by forming a slit-shaped separation grooves on the conductive pad material deposited on said isolation region reaching the surface of the isolation region, wherein the conductive pad material of the bout source and A step of separating the drain diffusion layer into individual conductive pads, a step of covering the conductive pads with a nitride film, a step of further covering the nitride film with a BPSG film , and a step of using the nitride film as a stopper. wherein the step of BPSG film <br/> forming a contact hole in, the nitride film exposed on the bottom of the contact hole is removed by etching, the co A step of exposing the surface of the conductive pads on the bottom of the contact holes and removing the conductive pads the gate insulating film as a stopper, the gate insulating exposed on the bottom of the contact hole by the step
Removing the etching film, the source diffusion layer exposed on the bottom of the contour <br/> Kutohoru This step or before
The method is characterized by including a step of connecting any of the drain diffusion layers to a metal wiring.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a view showing the structure of a semiconductor device according to the first embodiment of the present invention. In the first embodiment, a structure of a bit line contact that connects a bit line and a drain region of a selection gate MOS transistor will be described by taking a NAND nonvolatile semiconductor memory device as an example.

FIG. 1A is a plan view showing the structure near the bit line contact. Since this plan view has already been described in FIG. 8A, the same parts are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1B shows a BB cross section of FIG. The bit line contact according to the first embodiment of the present invention is formed so as to cover the STI type element region 5 formed on the p type silicon substrate 10, the entire surface of the element region 4, and both ends of the element isolation region 5. Conductive polycrystalline silicon film 13
And a BPSG film 16 remaining on the element isolation region 5 in the process of forming the contact hole 17 reaching the conductive pad.

As shown in FIG. 1B, the width of the conductive pad made of the polycrystalline silicon film 13 is made larger than the width of the element isolation region 5, and the element including the shoulder portions at both ends of the element isolation region 5 is included. If the contact hole 17 reaching the conductive pad is formed after the area 4 is protected, the conventional problem is to avoid the occurrence of the local etching 17a described above with reference to FIG. 8B. You can

The nitride film 15 in FIG.
As shown below, when forming the contact hole 17 reaching the conductive pad, it plays the role of a stopper that protects the surface of the conductive pad from being etched.

Next, a method of manufacturing the semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. The second embodiment shows a method of manufacturing the solid bit line contact of the first embodiment.

As shown in FIG. 2A, an element isolation region 5 is formed on a p-type silicon substrate 10, a gate oxide film 11 and a gate electrode material 12 made of conductive polycrystalline silicon are deposited, and a gate electrode is formed. After patterning, high-concentration n-type impurities are ion-implanted using the gate electrode as a mask,
An n ⁺ type source / drain diffusion layer is formed in the element region 4.

At this time, the ion implantation is performed on the gate oxide film 11
And the thermal diffusion of the n ⁺ type source / drain diffusion layer formation may be performed with the gate oxide film 11 left.
Ion implantation / diffusion may be performed after removing the gate oxide film. When the ion implantation is performed through the gate oxide film 11, the gate oxide film 11 is removed after the ion implantation and diffusion.

After removing the gate oxide film 11 and the gate electrode material 12 on the n ⁺ type source / drain diffusion layer, FIG.
As shown in (b), a conductive polycrystalline silicon film 13 is deposited and planarized so as to cover the n ⁺ type source / drain diffusion layer formed in the element region 4 and the element isolation regions 5 on both sides thereof.

Next, as shown in FIG. 2C, a resist pattern for forming the slit 14 is formed on the element isolation region 5 by using a photo-etching method, and the resist pattern is used as a mask to perform a normal RIE method. CDE (Chemical Dry Etching)
Method or wet etching method is used to etch the conductive polycrystalline silicon film 13 into a slit shape so that the polycrystalline silicon film 13 is individually provided in the contact hole formation portion of each bit line. To process as.

Next, as shown in FIG. 3D, a silicon nitride film 15 and a BPSG film 16 are sequentially deposited by a normal method to flatten the surface of the BPSG film. Subsequently, a resist pattern for forming a contact hole is formed by using a photo-etching method, and the BPSG film 16 and the nitride film 15 are partially etched by the RIE method using the resist pattern as a mask, as shown in FIG. Thus, the contact hole 17 is formed.

In this way, when the contact hole 17 is etched, only the flat portion of the nitride film 15 is exposed at the bottom of the contact hole 17, so that the nitride film 15 is a conductive pad made of the polycrystalline silicon film 13. On the other hand, it can serve as an etching stopper, and can avoid the occurrence of the local etching 17a which has been a problem in the past.

Next, a third embodiment of the present invention will be described with reference to FIG. 2 (a) to 2 described above
Since the manufacturing process up to (c) is the same as the manufacturing process of the second embodiment, the description thereof will be omitted. FIG. 2 (c)
After the step shown in FIG. 4 is completed, as shown in FIG. 4A, without forming the solid nitride film 15 shown in FIG.
The SG film 16 is deposited and the surface is flattened.

Subsequently, a resist pattern for forming a contact hole is formed by using a photo-etching method, and the BPSG film 16 is etched by using the RIE method as a mask to locally etch as shown in FIG. 4 (b). The contact hole 17 for the bit line can be formed without producing 17a.

In the third embodiment, the nitride film 15 that serves as a stopper is omitted, but since there is a conductive pad made of a flat polycrystalline silicon film 13 that covers the shoulders at both ends of the element isolation region. , The BPSG film 16 and the polycrystalline silicon film 13 are used to control the etching process of the contact hole 17 to control the etching process of FIG.
It is possible to avoid the occurrence of the local etching 17a in (d).

Next, a fourth embodiment of the present invention will be described with reference to FIGS. In the fourth embodiment,
Gate oxide film 11 covering the n ⁺ type source / drain diffusion layer
It is characterized in that the conductive polysilicon film 13 serving as the material of the conductive pad is deposited without removing the above.

That is, as shown in FIG. 5A, a polysilicon film 13 is deposited so as to cover the gate oxide film 11 and the element isolation region 5, and the surface is flattened. Next, FIG.
As shown in (b), a resist pattern for forming the slit 14 is formed on the element isolation region 5 by using a photolithography method, and the resist pattern is used as a mask for the RIE method, the CDE method,
Alternatively, by etching the conductive polycrystalline silicon film 13 into a slit shape using a wet etching method,
A conductive pad made of the polycrystalline silicon film 13 is formed.

Next, as shown in FIG. 5C, the nitride film 1
5 and the BPSG film 16 are deposited, a resist pattern for forming a contact hole is formed by photolithography following the step of planarizing, and RIE is performed using this as a mask.
By the method, the BPSG film 16 is etched until the conductive pad made of the polycrystalline silicon film 13 is reached, thereby forming the contact hole 17 shown in FIG. 6D.

However, in the steps up to FIG. 6D, since the gate oxide film 11 exists between the conductive pad made of the polycrystalline silicon film 13 and the element region 4, it is used as a contact hole in this state. I can't.

Therefore, as shown in FIG. 6E, the BPSG film 16 having the contact hole 17 formed therein is used as a mask to finally reach the element region 4 where the n ⁺ type drain diffusion layer is formed. The contact hole 18 is formed using a wet etching method.

In the contact hole forming step of the fourth embodiment, the conductive pad and the gate oxide film 1 shown in FIG.
1 are etched by using a normal wet method for the BPSG film and the polycrystalline silicon to obtain a polysilicon film 1
3 and the silicon oxide film filling the element isolation region 5 can have a sufficient etching selection ratio, and the gate oxide film 11 is sufficiently thinner than the silicon oxide film filling the element isolation region 5, so that the element isolation The conductive pad and the gate oxide film 11 can be removed without causing the shape destruction of the region 5.

Even when dry etching such as RIE is used to form the deep contact hole 18,
In the step of removing the conductive pad, if the polysilicon film is removed under the condition that the etching selection ratio with respect to the silicon oxide film is large, the gate oxide film 11 acts as an etching stopper, so that the local etching 17a shown in FIG.
The deep contact hole 18 can be formed without causing Then, if a slight etching for removing the gate oxide film 11 is added under the etching conditions for the silicon oxide film, the deep contact hole 18 connected to the bit line is completed.

The present invention is not limited to the above embodiment. In the first to fourth embodiments, the case of forming the drain contact of the NAND type nonvolatile semiconductor memory device has been described.
At least ST such as AM, SRAM, and logic integrated circuit
If it is a semiconductor integrated circuit having an I-type element isolation region,
The same process can be used for connecting the source / drain diffusion layer of the MOS transistor forming the semiconductor integrated circuit and the upper wiring. Other various modifications can be made without departing from the scope of the present invention.

[0060]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, a conductive silicon film is provided particularly in a semiconductor memory device including a memory cell array formed by using an STI type element isolation region. Is used as the conductive pad, it becomes possible to form a highly reliable bit line contact with a high manufacturing yield.

In the manufacturing process of the bit line contact of the present invention, the shape of the STI type element isolation region in the etching process of the contact hole is performed regardless of the width or diameter of the bit line contact and the dimension of the element region width between the bit lines. Destruction can be completely prevented.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view showing a structure near a bit line contact according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process of a bit line contact according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the continuation of the manufacturing process of the bit line contact according to the second embodiment of the invention.

FIG. 4 is a sectional view of a step of manufacturing a bit line contact according to the third embodiment of the present invention.

FIG. 5 is a sectional view of a manufacturing process of a bit line contact according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing a sequel to the manufacturing process of the bit line contact according to the fourth embodiment of the invention.

FIG. 7 is a plan view and a cross-sectional view showing a structure in the vicinity of a conventional bit line contact.

FIG. 8 is a cross-sectional view showing a manufacturing process of a conventional bit line contact.

[Explanation of symbols] 1 ... bit line contact 2 ... Contact width 3 ... Bit line 4 ... Element area 5: Element isolation region (STI) 6 ... Selection line 7 ... Word line 10 ... p type silicon substrate 11 ... Gate oxide film 12 ... Gate electrode material 13 ... Polycrystalline silicon film (conductive pad) 14 ... Slit 15 ... Nitride film 16 ... BPSG film 17 ... Contact hole 17a ... local etching 18 ... Deep contact hole

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 21/8246 H01L 27/10 681B 27/088 27/108 27/11 27/112 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/085-27/092 H01L 21/8234-21/8238 H01L 27/11 H01L 27/112 H01L 27/108

Claims (6)

(57) [Claims] 1. A device isolation region in which a device isolation insulating material is buried in a trench formed in a semiconductor substrate, a device region formed of a semiconductor substrate surface separated by the device isolation region, and a source in the device region. in and a semiconductor device comprising a drain diffusion layer, a contact hole for connecting the one to the wiring on the interlayer insulating film of said source and drain diffusion layer, the isolation region and one of the front surface of the source and drain diffusion layer of the conductive pads covering the edges, with the bottom of the contact hole, the conductive pad, the isolation region
Above, the adjacent conductive pads are slit-shaped.
A semiconductor device characterized by being separated from each other by a separation groove . 2. The conductive pad is a conductive polycrystalline silicon.
The wiring is a bit line of a semiconductor memory device.
And covers the bit line and the drain diffusion layer.
With the conductive pad, using the contact hole
The semiconductor device according to claim 1, characterized in that it is connected. 3. A step of forming a trench in a semiconductor substrate.
When, to fill the device isolation insulating material to the trench
Forming a device isolation region, and the semiconductor substrate surface separated by the device isolation region
For the gate electrode through the gate insulating film in the element region consisting of
The step of depositing the conductive material and the patterning of the conductive material for the gate electrode as the gate electrode.
The device region adjacent to the gate electrode when forming
Before covering the area to form the source and drain diffusion layers above
The step of removing the conductive material for the gate electrode and the step of forming the source and drain diffusion layers adjacent to the gate electrode.
The step of forming the gate insulating film covering the source and drain diffusion layers is removed.
Step of removing, one of the source and drain diffusion layers, and both sides thereof
A series of conductive layers covering the element isolation region arranged in
A step of depositing a pad material, and a step of depositing the conductive pad material deposited on the isolation region
Form a slit-shaped isolation groove that reaches the surface of the element isolation region
By adding the conductive pad material
Separate conductivity over either source or drain diffusion
And separating sexual pad, a step of covering the conductive pad nitride layer, contactors the nitride film and the step of further covered with a BPSG film, the BPSG film using the nitride film as a stopper
Forming a contact hole and removing the nitride film exposed on the bottom surface of the contact hole.
The bottom surface of the contact hole by
Exposing the surface of the conductive pad to the contact hole
And a step of connecting the conductive pad and the metal wiring
A method of manufacturing a semiconductor device, comprising: 4. A step of forming a trench in a semiconductor substrate, a step of forming an element isolation region by filling the trench with an element isolation insulating material, and a surface of the semiconductor substrate separated by the element isolation region. A step of depositing a conductive material for a gate electrode on the element region through a gate insulating film, and a step of patterning the conductive material for the gate electrode as a gate electrode, the source on the element region adjacent to the gate electrode and Removing the gate electrode conductive material covering the region where the drain diffusion layer is formed; forming source and drain diffusion layers adjacent to the gate electrode; and gate insulating covering the source and drain diffusion layers. A step of removing a film, one of the source and drain diffusion layers, and the element isolation regions arranged on both sides thereof. A step of depositing a continuous conductive pad material covering the element isolation region, and forming a slit-shaped isolation groove reaching the surface of the element isolation region in the conductive pad material deposited on the element isolation region, Separating the conductive pad material into separate conductive pads covering either the source or drain diffusion layer, and on the device region including on the conductive pad and the device isolation.
A step of depositing a BPSG film on the region and a step of forming a contact hole in the BPSG film.
The surface of the conductive pad on the bottom of the contact hole.
And a step of connecting the conductive pad and the metal wiring in the contact hole after exposing the surface . 5. A step of forming a trench in a semiconductor substrate.
When, to fill the device isolation insulating material to the trench
Forming a device isolation region, and the semiconductor substrate surface separated by the device isolation region
For the gate electrode through the gate insulating film in the element region consisting of
The step of depositing the conductive material and the patterning of the conductive material for the gate electrode as the gate electrode.
The device region adjacent to the gate electrode when forming
Before covering the area to form the source and drain diffusion layers above
The step of removing the conductive material for the gate electrode , the step of removing the conductive material for the gate electrode, and the step of covering the region where the source and drain diffusion layers are formed.
The step of removing the gate insulating film and the step of forming the source and drain diffusion layers adjacent to the gate electrode.
Step of forming , either of the source and drain diffusion layers, and both sides thereof
A series of conductive layers covering the element isolation region arranged in
A step of depositing a pad material, and a step of depositing the conductive pad material deposited on the isolation region
Form a slit-shaped isolation groove that reaches the surface of the element isolation region
By adding the conductive pad material
Separate conductivity over either source or drain diffusion
And separating sexual pad, a step of covering the conductive pad nitride layer, contactors the nitride film and the step of further covered with a BPSG film, the BPSG film using the nitride film as a stopper
Forming a contact hole and removing the nitride film exposed on the bottom surface of the contact hole.
The bottom surface of the contact hole by
Exposing the surface of the conductive pad to the contact hole
And a step of connecting the conductive pad and the metal wiring
A method of manufacturing a semiconductor device, comprising: 6. A step of forming a trench in a semiconductor substrate.
When, to fill the device isolation insulating material to the trench
Forming a device isolation region, and the semiconductor substrate surface separated by the device isolation region
For the gate electrode through the gate insulating film in the element region consisting of
The step of depositing the conductive material and the patterning of the conductive material for the gate electrode as the gate electrode.
The device region adjacent to the gate electrode when forming
Before covering the area to form the source and drain diffusion layers above
The step of removing the conductive material for the gate electrode and the step of forming the source and drain diffusion layers adjacent to the gate electrode.
Forming process and the gate remaining on the source and drain diffusion layers
Any of the source and drain diffusion layers via an insulating film
And the element isolation regions arranged on both sides of the heel.
And depositing a series of conductive pad materials on the conductive pad material deposited on the isolation regions.
A slit-shaped isolation groove reaching the surface of the element isolation region
Forming a series of conductive pad materials
A separate cover over either the source or drain diffusion layer
A step of separating into conductive pads, a step of covering the conductive pads with a nitride film, a step of further covering the nitride film with a BPSG film, and a step of contacting the BPSG film with the nitride film as a stopper.
Process for forming a contact hole and removing the nitride film exposed on the bottom surface of this contact hole.
To remove it on the bottom of the contact hole.
The step of exposing the surface of the conductive pad, and the conductive pad using the gate insulating film as a stopper.
And the step of removing and exposing the bottom surface of the contact hole by this step.
The step of etching away the gate insulating film, and the step of exposing the bottom surface of the contact hole by this step
Gold with either the source diffusion layer or the drain diffusion layer
A method of manufacturing a semiconductor device, comprising the step of connecting to a metal wiring .