JP3468386B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3468386B2 JP3468386B2 JP11406695A JP11406695A JP3468386B2 JP 3468386 B2 JP3468386 B2 JP 3468386B2 JP 11406695 A JP11406695 A JP 11406695A JP 11406695 A JP11406695 A JP 11406695A JP 3468386 B2 JP3468386 B2 JP 3468386B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- resin sealing
- semiconductor device
- sealing film
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 title description 6
- 239000011347 resin Substances 0.000 claims description 46
- 229920005989 resin Polymers 0.000 claims description 46
- 238000007789 sealing Methods 0.000 claims description 30
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 description 25
- 239000008393 encapsulating agent Substances 0.000 description 8
- 239000003566 sealing material Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 5
- 238000009832 plasma treatment Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000008642 heat stress Effects 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device .
【０００２】[0002]
【従来の技術】例えばフリップチップ方式と呼ばれる半
導体装置（突起電極を有する半導体チップ）の実装技術
では、図４に示すように、半導体チップ１の下面に設け
られた突起電極２を回路基板３の上面に設けられた接続
パッド４にボンディングすることにより、半導体チップ
１を回路基板３上に搭載し、次いで外周雰囲気からの汚
染や破損から半導体チップ１の下面（突起電極形成面）
を保護するために、ディスペンサー５を用いてエポキシ
系の熱硬化性樹脂からなる樹脂封止材６を半導体チップ
１の周囲にサイドポッティングして、毛細管現象を利用
することにより、図５に示すように、サイドポッティン
グされた樹脂封止材６を半導体チップ１と回路基板３と
の間に入り込ませている。2. Description of the Related Art For example, in a mounting technique of a semiconductor device (semiconductor chip having protruding electrodes) called a flip chip method, as shown in FIG. 4, the protruding electrodes 2 provided on the lower surface of a semiconductor chip 1 are mounted on a circuit board 3. The semiconductor chip 1 is mounted on the circuit board 3 by bonding to the connection pads 4 provided on the upper surface, and then the lower surface of the semiconductor chip 1 (projection electrode forming surface) from contamination or damage from the ambient atmosphere.
In order to protect the semiconductor chip 1, a resin sealing material 6 made of an epoxy-based thermosetting resin is side-potted around the semiconductor chip 1 by using a dispenser 5, and a capillary phenomenon is utilized to obtain the resin sealing material 6 as shown in FIG. Then, the side potted resin sealing material 6 is inserted between the semiconductor chip 1 and the circuit board 3.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
このような半導体装置の実装方法では、次のような問題
があった。第１に、サイドポッティングと毛細管現象の
利用による封止では、図６に示すように、樹脂封止材６
が半導体チップ１と回路基板３との間にある程度までし
か入り込まない場合が生じることがあり、この結果半導
体チップ１の底面中央部と回路基板３との間に気泡７が
残存することになる。このような現象が生じた場合に
は、気泡７中の水分や不純物が半導体チップ１内に入り
込み、半導体チップ１内の配線が腐食したりする等の問
題が生じることになる。このような現象は樹脂封止材６
の粘度が高いほど生じやすく、したがって使用できる樹
脂封止材の粘度に制約を受けるという問題もあった。第
２に、半導体チップ１の突起電極形成面側の構造は、図
示していないが、一般的に、パッシベーション膜に形成
された開口部を介して露出された接続パツド上に下地金
属層を介して突起電極が形成された構造となっている。
この場合、パッシベーション膜の厚さは１〜２μｍ程度
とかなり薄いので、パッシベーション膜に傷が付きやす
く、したがって半導体チップ１の取り扱いにかなりの注
意を払う必要があるという問題があった。第３に、回路
基板３上に搭載した半導体チップ１ごとにディスペンサ
ー５を用いて樹脂封止材６をサイドポッティングしてい
るので、封止に時間がかかるという問題があった。第４
に、樹胎封止材６をサイドポッティングした後、樹脂封
止材６を加熱して硬化させているが、この加熱により、
回路基板３やそれに搭載された他の搭載部品（図示せ
ず）に熱ストレスが加わり、回路基板３やそれに搭載さ
れた他の搭載部品を損傷することがあるという問題があ
った。この発明の目的は、樹脂封止材の粘度に関係なく
気泡が残存しないように封止することができ、また半導
体チップの取り扱いにあまり注意を払う必要がないよう
にすることができ、また封止を短時間で行うことがで
き、さらに回路基板やそれに搭載された他の搭載部品が
樹脂封止材を加熱して硬化させる際の熱ストレスにより
損傷しないようにすることができる半導体装置の製造方
法を提供することにある。However, the conventional mounting method for such a semiconductor device has the following problems. First, in the sealing using side potting and the capillary phenomenon, as shown in FIG.
There may be a case where the particles enter between the semiconductor chip 1 and the circuit board 3 to some extent, and as a result, the bubble 7 remains between the center part of the bottom surface of the semiconductor chip 1 and the circuit board 3. When such a phenomenon occurs, water or impurities in the bubbles 7 may enter the semiconductor chip 1 and cause a problem such as corrosion of the wiring in the semiconductor chip 1. Such a phenomenon is caused by the resin sealing material 6
The higher the viscosity is, the more likely it is to occur, and therefore the viscosity of the usable resin encapsulant is restricted. Secondly, although not shown, the structure of the semiconductor chip 1 on the side where the protruding electrodes are formed generally has a base metal layer on the connection pad exposed through the opening formed on the passivation film. Has a structure in which protruding electrodes are formed.
In this case, since the thickness of the passivation film is as thin as about 1 to 2 μm, the passivation film is likely to be scratched, so that there is a problem in that the semiconductor chip 1 needs to be handled with great care. Thirdly, since the resin encapsulating material 6 is side-potted by using the dispenser 5 for each semiconductor chip 1 mounted on the circuit board 3, there is a problem that the encapsulation takes time. Fourth
Then, after the side potting of the resin sealing material 6, the resin sealing material 6 is heated and cured.
There has been a problem that thermal stress is applied to the circuit board 3 and other mounting components (not shown) mounted thereon, and the circuit board 3 and other mounting components mounted thereon may be damaged. It is an object of the present invention to perform sealing so that air bubbles do not remain regardless of the viscosity of the resin encapsulant, and to make it possible to handle the semiconductor chip with little care. Manufacturing of semiconductor devices that can be stopped in a short time and can prevent the circuit board and other mounted components mounted on it from being damaged by thermal stress when heating and curing the resin encapsulant. Person
To provide the law .
【０００４】[0004]
【課題を解決するための手段】請求項１記載の発明は、
ウエーハの一の面に突起電極を形成した後、該ウエーハ
の一の面に樹脂封止膜を前記突起電極の上部が突出する
ように被覆し、次いで前記樹脂封止膜を加熱して硬化さ
せ、次いでウエーハ全面に酸素プラズマ処理あるいは紫
外線オゾン処理を行うことにより前記突起電極上に付着
している樹脂を除去し、この後、前記ウエーハをダイシ
ングして個々のチップに分割するようにしたものであ
る。請求項２記載の発明は、前記樹脂封止膜の厚さを前
記突起電極の高さの半分程度としたものである。The invention according to claim 1 is
After forming the protruding electrode on one surface of the wafer, a resin sealing film is coated on the one surface of the wafer so that the upper portion of the protruding electrode protrudes, and then the resin sealing film is cured by heating. , Then oxygen plasma treatment or purple on the entire wafer surface
Adhesion on the protruding electrode by external ozone treatment
The resin on the wafer and then dicing the wafer.
The chip is divided into individual chips . According to a second aspect of the present invention, the thickness of the resin sealing film is about half the height of the protruding electrode.
【０００５】請求項１記載の発明によれば、ウエーハの
一の面に突起電極を形成した後、該ウエーハの一の面に
樹脂封止膜を前記突起電極の上部が突出するように被覆
し、次いで前記樹脂封止膜を加熱して硬化させ、次いで
ウエーハ全面に酸素プラズマ処理あるいは紫外線オゾン
処理を行うことにより前記突起電極上に付着している樹
脂を除去し、この後、前記ウエーハをダイシングして個
々のチップに分割しているので、半導体装置を回路基板
上に実装する場合、回路基板やそれに搭載された他の搭
載部品が樹脂封止膜を加熱して硬化させる際の熱ストレ
スにより損傷しないようにすることができ、また、ウエ
ーハ全面に酸素プラズマ処理あるいは紫外線オゾン処理
を行った上、個々のチップに分割するので、大変効率的
なものである。 According to the first aspect of the present invention, after the protruding electrode is formed on one surface of the wafer, a resin sealing film is coated on the one surface of the wafer so that the upper portion of the protruding electrode protrudes. Then, the resin sealing film is heated and cured , and then
Oxygen plasma treatment or ultraviolet ozone over the entire wafer
Trees adhering to the protruding electrodes due to the treatment
Remove the fat and then dice the wafer
Since it is divided into different chips, when mounting a semiconductor device on a circuit board, the circuit board and other mounted components will not be damaged by the thermal stress when heating and curing the resin sealing film. You can also
-Oxygen plasma treatment or ultraviolet ozone treatment on the entire surface
It is very efficient because it is divided into individual chips after performing
It is something.
【０００６】[0006]
【実施例】図１及び図２はそれぞれこの発明の一実施例
における半導体装置の各製造工程を示したものである。
そこで、これらの図を順に参照しながら、この実施例に
おける半導体装置の製造方法について説明する。1 and 2 show respective steps of manufacturing a semiconductor device according to an embodiment of the present invention.
Therefore, a method of manufacturing a semiconductor device according to this embodiment will be described with reference to these drawings in order.
【０００７】まず、図１に示すように、ウェーハ１１上
に突起電極１２が形成されたものを用意する。突起電極
１２ははんだ突起あるいは金や銅等の金属突起上にはん
だ層が設けられたものからなり、高さは２０〜１００μ
ｍ程度となっている。なお、ウェーハ１１上の格子状の
線はダイシングストリート１３を示す。そして、ディス
ペンサー１４を用いてポリイミドあるいはエポキシ系の
熱硬化性樹脂からなる樹脂封止材１５をウェーハ１１の
上面中央部にポッティングし、次いでウェーハ１１を高
速回転させると、図２に示すように、ウェーハ１１の上
面に樹脂封止膜１６が突起電極１２の上部が突出するよ
うに被覆される。First, as shown in FIG. 1, a wafer 11 on which the protruding electrodes 12 are formed is prepared. The bump electrode 12 is composed of a solder bump or a metal bump such as gold or copper provided with a solder layer and has a height of 20 to 100 μm.
It is about m. The grid lines on the wafer 11 indicate the dicing streets 13. Then, using the dispenser 14, a resin encapsulant 15 made of polyimide or epoxy thermosetting resin is potted on the central portion of the upper surface of the wafer 11, and then the wafer 11 is rotated at a high speed, as shown in FIG. A resin sealing film 16 is coated on the upper surface of the wafer 11 so that the upper portions of the protruding electrodes 12 project .
【０００８】このように、ウェーハ１１の上面にスピン
コートにより樹指封止膜１６を突起電極１２の上部が突
出するように被覆させているので、樹脂封止材１５の粘
度に関係なく気泡が残存しないように封止することがで
き、またウェーハ１１の状態における全てのチップを一
度に封止することができるので、封止を短時間で行うこ
とができる。[0008] Thus, upper butt of the tree fingers sealing film 16 protruding electrodes 12 by spin coating on the upper surface of the wafer 11
Since the coating is performed so as to be exposed, it is possible to perform sealing so that air bubbles do not remain regardless of the viscosity of the resin sealing material 15, and all chips in the state of the wafer 11 can be sealed at once. Therefore, the sealing can be performed in a short time.
【０００９】次に、図示しないオーブン等を用いて加熱
し、樹脂封止膜１６を硬化させる。次に、突起電極１２
上に樹脂封止材１５が付着している場合には、酸素プラ
ズマ処理あるいは紫外線オゾン処理を行うことにより突
起電極１２上に付着している樹脂封止材１５を除去す
る。この場合、樹脂封止膜１６の表面も若干除去され
る。そして、この状態における樹脂封止膜１６の厚さが
突起電極１２の高さ２０〜１００μｍ程度の半分程度つ
まり１０〜５０μｍ程度となるようにする。次に、ウェ
ーハ１１をダイシングストリート１３に沿って図示しな
いダイシングブレードによってダイシングして個々のチ
ップに分割すると、図２において一部を拡大して示すよ
うな半導体装置１７が得られる。Next, the resin sealing film 16 is cured by heating using an oven or the like (not shown). Next, the protruding electrode 12
When the resin encapsulant 15 is adhered on the upper surface, oxygen plasma treatment or ultraviolet ozone treatment is performed to remove the resin encapsulant 15 adhered on the protruding electrodes 12. In this case, the surface of the resin sealing film 16 is also slightly removed. The thickness of the resin sealing film 16 in this state is about half the height of the protruding electrode 12 of about 20 to 100 μm, that is, about 10 to 50 μm. Next, the wafer 11 is diced along the dicing streets 13 by a dicing blade (not shown) and divided into individual chips, so that a semiconductor device 17 as shown in a partially enlarged view in FIG. 2 is obtained.
【００１０】このようにして得られた半導体装置１７で
は、半導体チップ１８の上面に突起電極１２が設けら
れ、半導体チップ１８の上面に樹脂封止膜１６が突起電
極１２の上部が突出するように被覆された構造となって
いる。この場合、既に説明したように、スピンコートに
より樹脂封止膜１６を気泡が残存しないように被覆する
ことができる上、樹脂封止膜１６の厚さが１０〜５０μ
ｍ程度と比較的厚いので、外周雰囲気からの汚染や破損
から半導体チップ１８の上面（突起電極形成面）を十分
に保護することができる。したがって、半導体チップ１
８の取り扱いにあまり注意を払う必要がないようにする
ことができる。In the semiconductor device 17 thus obtained, the protruding electrode 12 is provided on the upper surface of the semiconductor chip 18, and the resin sealing film 16 is formed on the upper surface of the semiconductor chip 18 so that the upper portion of the protruding electrode 12 projects. It has a covered structure. In this case, as described above, the resin sealing film 16 can be coated by spin coating so that air bubbles do not remain, and the thickness of the resin sealing film 16 is 10 to 50 μm.
Since it is relatively thick, such as about m, the upper surface (projection electrode forming surface) of the semiconductor chip 18 can be sufficiently protected from contamination and damage from the outer atmosphere. Therefore, the semiconductor chip 1
It is possible to avoid paying too much attention to the handling of 8.
【００１１】次に、図３は半導体装置１７を回路基板１
９上に実装した状態を示したものである。この実装構造
では、半導体チップ１８の下面に設けられた突起電極１
２を回路基板１９の上面に設けられた接続パッド２０に
ボンディングすることにより、半導体装置１７を回路基
板１９上に実装している。この場合、突起電極１２はそ
の高さの半分程度を樹脂封止膜１６の下方に突出されて
いるので、半導体チップ１８の下面に樹脂封止膜１６が
予め被覆されていても、突起電極１２を回路基板１９の
接続パツド２０に良好にボンディングすることができ
る。また、樹脂封止膜１６は既に加熱されて硬化してい
るので、この実装の段階で樹脂封止膜１６を加熱して硬
化させる必要はなく、したがって回路基板１９やそれに
搭載された他の搭載部品（図示せず）が樹脂封止膜１６
を加熱して硬化させる際の熱ストレスにより損傷しない
ようにすることができる。Next, FIG. 3 shows the semiconductor device 17 on the circuit board 1.
9 shows a state in which it is mounted on the device 9. In this mounting structure, the protruding electrode 1 provided on the lower surface of the semiconductor chip 18
The semiconductor device 17 is mounted on the circuit board 19 by bonding 2 to the connection pad 20 provided on the upper surface of the circuit board 19. In this case, since the protruding electrode 12 projects about half of its height below the resin sealing film 16, even if the lower surface of the semiconductor chip 18 is covered with the resin sealing film 16 in advance, the protruding electrode 12 is not formed. Can be satisfactorily bonded to the connection pad 20 of the circuit board 19. Further, since the resin sealing film 16 has already been heated and cured, it is not necessary to heat and cure the resin sealing film 16 at this stage of mounting, and therefore, the circuit board 19 and other mountings mounted thereon. The component (not shown) is the resin sealing film 16
It can be prevented from being damaged by heat stress when heating and curing.
【００１２】[0012]
【発明の効果】以上説明したように、請求項１記載の発
明によれば、ウエーハの一の面に突起電極を形成した
後、該ウエーハの一の面に樹脂封止膜を前記突起電極の
上部が突出するように被覆し、次いで前記樹脂封止膜を
加熱して硬化させ、次いでウエーハ全面に酸素プラズマ
処理あるいは紫外線オゾン処理を行うことにより前記突
起電極上に付着している樹脂を除去し、この後、前記ウ
エーハをダイシングして個々のチップに分割しているの
で、半導体装置を回路基板上に実装する場合、回路基板
やそれに搭載された他の搭載部品が樹脂封止膜を加熱し
て硬化させる際の熱ストレスにより損傷しないようにす
ることができ、また、ウエーハ全面に酸素プラズマ処理
あるいは紫外線オゾン処理を行った上、個々のチップに
分割するので、大変効率的に行うことができるという効
果を奏する。 As described above, according to the first aspect of the present invention, after the protruding electrode is formed on the one surface of the wafer, the resin sealing film is formed on the one surface of the wafer. Cover so that the upper part protrudes, then heat and cure the resin sealing film , and then apply oxygen plasma to the entire surface of the wafer.
Treatment or UV ozone treatment
After removing the resin adhering to the starting electrode,
Since the wafer is diced and divided into individual chips, when mounting the semiconductor device on the circuit board, when the circuit board and other mounted components are heated and cured by the resin sealing film, It can be prevented from being damaged by heat stress , and the whole surface of the wafer is treated with oxygen plasma.
Alternatively, after subjecting it to ultraviolet ozone treatment,
Because it is divided, it can be done very efficiently.
Play the fruit.
【図１】この発明の一実施例における半導体装置の製造
に際し、ウェーハの上面中央部に樹脂封止材をポッティ
ングした状態の一部を拡大して示す斜視図。FIG. 1 is an enlarged perspective view showing a part of a state where a resin encapsulant is potted on a central portion of an upper surface of a wafer when manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】図１に続く工程であって、スピンコートにより
ウェーハの上面に樹脂封止膜を突起電極の上部が突出す
るように被覆させた状態の一部を拡大して示す斜視図。[2] A process subsequent to FIG. 1, an enlarged part of a state in which the top was covered to <br/> so that to the projection of the resin sealing film protruding electrodes on the upper surface of the wafer by spin coating FIG.
【図３】半導体装置を回路基板上に実装した状態の断面
図。FIG. 3 is a cross-sectional view of a semiconductor device mounted on a circuit board.
【図４】従来の半導体装置の実装に際し、樹脂封止材を
サイドポッティングした状態の断面図。FIG. 4 is a cross-sectional view of a state in which a resin encapsulant is side-potted when mounting a conventional semiconductor device.
【図５】従来の半導体装置を回路基板上に実装した状態
の断面図。FIG. 5 is a cross-sectional view of a conventional semiconductor device mounted on a circuit board.
【図６】従来の半導体装置の実装方法の問題点の１つを
説明するために示す断面図。FIG. 6 is a cross-sectional view shown for explaining one of the problems of the conventional semiconductor device mounting method.
１１ ウェーハ １２ 突起電極 １３ ダイシングストリート １６ 樹脂封止膜 １７ 半導体装置 １８ 半導体チップ １９ 回路基板 11 wafers 12 protruding electrode 13 Dicing Street 16 Resin sealing film 17 Semiconductor device 18 semiconductor chips 19 circuit board
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−55278（ＪＰ，Ａ) 特開 平５−3183（ＪＰ，Ａ) 特開 平６−151487（ＪＰ，Ａ) 特開 昭61−236167（ＪＰ，Ａ) 特開 昭61−53335（ＪＰ，Ａ) 特開 平３−73534（ＪＰ，Ａ) 特開 平10−313016（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continued front page (56) Reference JP-A-5-55278 (JP, A) Japanese Patent Laid-Open No. 5-3183 (JP, A) JP-A-6-151487 (JP, A) JP-A-61-236167 (JP, A) JP-A-61-53335 (JP, A) JP-A-3-73534 (JP, A) Japanese Patent Laid-Open No. 10-313016 (JP, A)
Claims (2)
後、該ウエーハの一の面に樹脂封止膜を前記突起電極の
上部が突出するように被覆し、次いで前記樹脂封止膜を
加熱して硬化させ、次いでウエーハ全面に酸素プラズマ
処理あるいは紫外線オゾン処理を行うことにより前記突
起電極上に付着している樹脂を除去し、この後、前記ウ
エーハをダイシングして個々のチップに分割することを
特徴とする半導体装置の製造方法。1. A protrusion electrode is formed on one surface of a wafer, and then a resin sealing film is coated on the one surface of the wafer so that the upper portion of the protrusion electrode protrudes. Heat and cure , then oxygen plasma over the entire wafer
Treatment or UV ozone treatment
After removing the resin adhering to the starting electrode,
A method of manufacturing a semiconductor device, which comprises dicing an wafer to divide it into individual chips .
止膜の厚さは前記突起電極の高さの半分程度であること
を特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the resin sealing film is about half the height of the bump electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11406695A JP3468386B2 (en) | 1995-04-17 | 1995-04-17 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11406695A JP3468386B2 (en) | 1995-04-17 | 1995-04-17 | Method for manufacturing semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11285398A Division JP3468406B2 (en) | 1998-04-09 | 1998-04-09 | Semiconductor device mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08288293A JPH08288293A (en) | 1996-11-01 |
| JP3468386B2 true JP3468386B2 (en) | 2003-11-17 |
Family
ID=14628185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11406695A Expired - Lifetime JP3468386B2 (en) | 1995-04-17 | 1995-04-17 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3468386B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3152180B2 (en) | 1997-10-03 | 2001-04-03 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP3577419B2 (en) | 1998-12-17 | 2004-10-13 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP4416218B2 (en) | 1999-09-14 | 2010-02-17 | アピックヤマダ株式会社 | Resin sealing method and resin sealing device |
| KR100425946B1 (en) * | 2002-02-20 | 2004-04-01 | 주식회사 칩팩코리아 | METHOD FOR FORMING Au STUD BUMP OF FLIP CHIP PACKAGE |
| KR100520080B1 (en) * | 2003-07-18 | 2005-10-12 | 삼성전자주식회사 | Surface Mounting Method of Semi-conduct Chip on PCB |
-
1995
- 1995-04-17 JP JP11406695A patent/JP3468386B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08288293A (en) | 1996-11-01 |
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