JP3467353B2 - Data storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device provided with a capacitor having a capacitive insulating film made of a ferroelectric material.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a structure of an element for storing data in a dynamic random access memory (hereinafter referred to as "DRAM") which is a typical rewritable semiconductor memory device at present.

FIG. 5 is a circuit diagram of a conventional DRAM. In FIG. 5, 51 is a capacitor for storing electric charge, 5
Reference numerals 2 and 53 are electrodes of the capacitor 51, 54 is an N-channel metal oxide semiconductor (hereinafter, referred to as “NMOS transistor”) for a switch that permits or prohibits the read operation and the write operation of the charge of the capacitor 51, and 55 is A bit line for reading or writing the charge of the capacitor 51, a differential amplifier 56 for amplifying a voltage proportional to the difference between the potential read through the bit line 55 and the reference potential, 57 NMO
It is a word line for applying a potential for opening and closing the switch to the S transistor 54.

An element for storing information is called a memory cell,
The memory cell of FIG. 5 is composed of one capacitor 51 that stores electric charges for storing one bit of information and one switching NMOS transistor 54. One electrode 53 of the capacitor 51 is connected to the bit line 55 through the NMOS transistor 54, and the bit line 55 is connected to the differential amplifier 56. The other electrode 52 of the capacitor 51 is grounded to the ground level. The other electrode 52 may be connected to another appropriate potential instead of the ground level.

The outline of the operation of the DRAM configured as described above will be described below. When the data is read,
First, the level of the word line 57 is raised and the NMOS transistor 54 is turned on. Next, the differential amplifier 56
At, the potential obtained through bit line 55 is compared with the reference potential. At this time, when the potential of the bit line 55 is equal to or higher than the reference potential, the data is "1", and in other cases, it is "0", which can correspond to 1-bit information. Next, the potential of the bit line 55 is amplified to the power supply level or the ground level corresponding to the data and output as the read data. Next, since the data in the memory cell is destroyed once read, the potential corresponding to the read data is applied to the bit line 55 to rewrite the data. Then, the level of the word line 57 is lowered and the NMOS transistor 54 is turned off. This returns to the state before reading.

When data is written, a potential corresponding to the data written in the rewriting procedure is externally applied to the bit line 55.

Recently, a ferroelectric memory device has been developed which uses a ferroelectric material for the insulating film of a capacitor that stores electric charges.

A conventional ferroelectric memory device will be described below with reference to the drawings.

FIG. 6 is a circuit diagram of a conventional ferroelectric memory device. In FIG. 6, reference numeral 61 is a ferroelectric capacitor using a ferroelectric substance having a property of spontaneous polarization in which the polarization does not disappear even if the electric field is removed, in the capacitor insulating film of the capacitor, and 58.
Is a cell plate to which the other electrode 52 of the ferroelectric capacitor 61 is connected. The other members are denoted by the same reference numerals as those in FIG. 5, and the description thereof will be omitted.

The ferroelectric capacitor 61 is connected to the bit line 55 through the NMOS transistor 54, and the other electrode 52 is connected to the cell plate 58. The bit line 55 is connected to the differential amplifier 56. In addition,
In FIG. 6, a ferroelectric capacitor 61 and a bit line 55
Although the NMOS transistor 54 is used as a switch element for electrically connecting and, a P-channel MOS transistor (hereinafter, referred to as “PMOS transistor”) may be used in some cases.

The memory cell of this memory device can store data by the same operation as the memory cell of the DRAM of FIG. 5 if the cell plate 58 is grounded. Furthermore, the data of "0" or "1" can be obtained by utilizing the property of the ferroelectric substance that spontaneous polarization remains even if the electric field is removed.
By making it correspond to the direction of spontaneous polarization of the ferroelectric insulating film of the capacitor, not depending on whether the capacitor stores electric charge or not, it can be used as a non-volatile memory in which data is not erased even when the power is turned off.

The operation of the non-volatile memory configured as described above will be described below.

When data is read, the bit line 55 is first precharged to a constant potential, for example, the ground level. Then, the level of the word line 57 is raised and the NMOS transistor 54 is turned on. next,
The potential of the cell plate 58 is raised, and the potential of the bit line 55 at this time is determined by the ratio of the capacitance of the ferroelectric capacitor 61 and the capacitance of the bit line 55 by capacitance division.
The capacitance of the ferroelectric capacitor 61 differs depending on whether or not the polarization direction of the capacitance insulating film is reversed. That is, as shown in FIG. 7B, when one electrode 53 is applied with a voltage sufficiently higher than that of the cell plate 58 in advance so that the direction of polarization is downward, FIG. As shown in FIG.
As compared with the case where the direction of polarization is set to be upward by applying a voltage sufficiently lower than 8, the direction of polarization is reversed when the potential of the cell plate 58 is increased, so that the capacitance of the ferroelectric capacitor 61 is large. Become. Therefore, as shown in FIG. 7B, the downward direction in which the polarization reversal occurs is more
As shown in (a), the potential of the bit line 55 becomes higher than in the case where the direction of spontaneous polarization of the ferroelectric capacitor 61 is upward.

Next, the reference potential in the middle of those potentials is compared with the potential obtained through the bit line 55 in the differential amplifier 56, and then the potential obtained through the bit line 55 is compared with the power supply level or the ground level. Is amplified and output as data.

Next, since the data in the memory cell is destroyed once read, the read data needs to be written again. Therefore, the potential of the cell plate 58 is lowered to the ground level in the state where the potential of the bit line 55 is amplified to the power supply level or the ground level by the differential amplifier 56 according to the read data. As shown in FIG. 7B, when the potential of the bit line 55 is at the power supply level, the polarization is downward,
As shown in (a), when the potential of the bit line 55 is at the ground level, the potentials applied to both ends of the ferroelectric capacitor 61 are equal, so that the polarization direction remains upward.

Next, the level of the word line 57 is lowered, the NMOS transistor 54 is turned off, the polarization state returns to the state before reading, and the reading operation is completed.

When data is written, the potential of the bit line 55 is externally applied in the procedure of rewriting data to the memory cell described in the read operation.

[0018]

At the present time, as the cost of semiconductor memory devices is rapidly decreasing, one effective means for achieving this is to reduce the chip area, that is, the memory cell area. However, since the memory device having the conventional ferroelectric capacitor has the memory cell structure described above, an element that constitutes a memory cell is different from a flash memory which is another rewritable nonvolatile memory device. It had the problem of being disadvantageous in numbers.

It is a principal object of the present invention to solve the above conventional problems and to reduce the number of elements constituting a memory cell of a memory device having a ferroelectric capacitor so that the memory cell area can be reduced. It is a thing.

[0020]

In order to achieve the above object, the present invention provides a data storage device in which a plurality of ferroelectric capacitors connected in series and a common contact of each of the capacitors are connected by a signal line. It is composed of a potential detector connected thereto.

[0021] Specifically, the means for solving the problems according to the invention of claim 1 is to connect a plurality of capacitors that have a capacitive insulating film made of a ferroelectric substance and are connected in series, and the plurality of capacitors are connected to each other. Bei example a potential detector for detecting the respective potentials of the common contact, wherein the plurality of capacitors each conductive
The areas of the poles are different from each other .

With the above configuration, since n (where n is an integer of 2 or more. The same applies hereinafter) number of ferroelectric capacitors are connected in series, one ferroelectric capacitor is dependent on the polarization of the ferroelectric substance. Since it has two different potentials, each has 2n different polarization directions that can be applied to the potential detector. Moreover, each ferroelectric capacitor
Since the capacitance of the
A sufficient potential should be applied to the common contact of each ferroelectric capacitor.
You can

According to a second aspect of the present invention, a plurality of capacitors having a capacitive insulating film made of a ferroelectric substance and connected in series are provided.
E Bei and data, and a potential detector plurality of Capacity data What happened detects each potential of the common contact connected, the calibration
The capacity of each passer is different from each other .

With the above configuration, the same as the invention of claim 1
, N ferroelectric capacitors are connected in series.
Therefore, one ferroelectric capacitor is
Since it has two different potentials, it has 2n
The orientations of the poles will be combined, which results in 2
N potentials can be applied to the potential detector. That
Above, ferroelectric capacitors have different capacitance.
Therefore, a sufficient electric potential to invert the polarization of the ferroelectric substance is applied to each ferroelectric substance.
It can be applied to the common contact of the electric capacitor.

According to a third aspect of the invention, in the structure of the first or second aspect, a switch element is further provided between the potential detector and the common contact to open and close the connection between the common contact and the potential detector. This is to add the configuration of having.

With the above structure, since the potential detector is connected to the common contact of the ferroelectric capacitor through the switch element, the read operation and the write operation of the data storage device can be controlled by opening / closing the switch element. . Further, by controlling the switch element, a desired data storage device can be selected from the data storage devices arranged in an array.

[0027]

[0028]

[0029]

[0030]

DETAILED DESCRIPTION OF THE INVENTION A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of a data storage device according to the first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a first ferroelectric capacitor having an insulating film for storing electric charges, and a capacitor insulating film made of a ferroelectric material having a property of spontaneous polarization in which polarization does not disappear even if an electric field is removed, and 12 denotes a first ferroelectric capacitor. Second ferroelectric capacitor having a smaller capacity than that of the ferroelectric capacitor 11, 13 is a first cell plate to which one electrode of the first ferroelectric capacitor 11 is connected, and 14 is a second ferroelectric capacitor. A second cell plate to which one electrode of the dielectric capacitor 12 is connected, 15 is a common contact to which the other electrodes of the first ferroelectric capacitor 11 and the second ferroelectric capacitor 12 are connected, Reference numeral 16 is a bit line for reading out the potential of the common contact 15 and writing charge as data to the first ferroelectric capacitor 11 and the second ferroelectric capacitor 12, and 17 is a potential detection A is, in this embodiment, a differential amplifier to which the voltage is amplified by the comparison between the potential and the reference potential read out through the bit line 16. Generally, in a data storage device, 13, 14 and 16 are signal lines, but in the present embodiment, 13 is a first cell plate, 14 is a second cell plate, and 16 is a signal line in accordance with a semiconductor storage device. I will call it the bit line.

The operation of the data storage device configured as described above will be described below.

In the initial state, the potentials of the bit line 16, the first cell plate 13 and the second cell plate 14 are at the ground level, and the first ferroelectric capacitor 11 and the second ferroelectric capacitor 12 have the same potential. It is assumed that there is spontaneous polarization.

When data is read, the cell plate 14 is first connected to an appropriate potential, for example, the ground level potential.

Next, when the potential of the cell plate 13 is raised to an appropriate potential, for example, the power supply level, the bit line 16
The potential of the bit line 16 is determined by the ratio of the capacitance of the first ferroelectric capacitor 11 and the capacitance of the second ferroelectric capacitor 12 to the capacitance of the first ferroelectric capacitor 11. Further, the capacities of the first ferroelectric capacitor 11 and the second ferroelectric capacitor 12 differ depending on the directions of their spontaneous polarizations. The combination of these spontaneous polarization directions and the potential of the bit line 16 will be described in order.

As described with reference to FIG. 6, the direction of polarization generated when an electric field is applied to the ferroelectric capacitor is represented by an arrow from a higher potential to a lower potential. For example, the common contact 15 has the first cell plate 1
When a higher potential than that of No. 3 is applied, polarization of the downward arrow in FIG. 1 occurs in the first ferroelectric capacitor 11. [Table 1] below shows the combination of the directions of the spontaneous polarization of the ferroelectric capacitor by this expression method.
Corresponds to bit data.

[0037]

[Table 1]

When the read operation is performed, the second cell plate 14 is grounded and the potential of the first cell plate 13 rises. Therefore, the first ferroelectric capacitor 1
Finally, the polarization directions of the first and second ferroelectric capacitors 12 are both upward.

In the combination corresponding to the data (1,1), the polarization of the first ferroelectric capacitor 11 is inverted, but the polarization of the second ferroelectric capacitor 12 is not inverted. Therefore, the capacitance of the first ferroelectric capacitor 11 connected to the power source is larger than that when the polarization is not inverted, and the second ferroelectric capacitor 12 grounded to the ground is when the polarization is inverted. The potential of the bit line 16 is the highest among the four combinations in [Table 1].

In the combination corresponding to the data (0,0), the polarization of the first ferroelectric capacitor 11 is not inverted, but the polarization of the second ferroelectric capacitor 12 is inverted, so that the bit line 16 of the bit line 16 is inverted. The potential is the lowest.

In the combination corresponding to the data (1,0), the polarization of the first ferroelectric capacitor 11 is inverted and the polarization of the second ferroelectric capacitor 12 is also inverted.

In the combination corresponding to the data (0, 1), neither the polarization of the first ferroelectric capacitor 11 nor the polarization of the second ferroelectric capacitor 12 is inverted. In the combination corresponding to the data (1,0) and the data (0,1), which of the potentials of the bit line 16 is higher is determined by the capacitance of the capacitor. The capacitance is determined by the physical size of each of the first ferroelectric capacitor 11 and the second ferroelectric capacitor 12. Therefore, in order to obtain a potential at the common contact 15 that is sufficient to invert the polarization of the second ferroelectric capacitor 12,
It is desirable to adjust the physical size of the two ferroelectric capacitors so that the capacitance of the first ferroelectric capacitor 11 is larger than that of the second ferroelectric capacitor 12. If the size is adjusted in this way, bit line 1
The potential generated at 6 is as shown in FIG.

FIG. 2 is a simplified diagram of bit line potentials corresponding to combinations of polarizations of the ferroelectric capacitors of the data storage device according to the first embodiment of the present invention. In FIG. 2, the reference potential A is a potential set in the middle of both potentials for distinguishing the potentials corresponding to the data (1,0) and the data (0,1), and the reference potential B is the data (1 , 1) and the data (1, 0) are potentials set in the middle of the two potentials for identifying the potentials, and the reference potential C is the data (0, 1) and the data (0, 0). It is a potential set in the middle of both potentials for identifying the potentials corresponding to and.

Next, the potential read through the bit line 16 is compared with the reference potentials A, B, and C in the differential amplifier 17, respectively, and the voltage is amplified according to the obtained potential to obtain 2 bits. Is output as any one of the data.

Next, once the read operation is performed, the polarization which is the accumulated data is lost, and therefore the write operation needs to be performed again.

The procedure for rewriting data will be described below for each of the four combinations shown in [Table 1]. In the case of data (1,1), the bit line 16 is set to the power supply level potential, and the first cell plate 13 and the second cell plate 14 are set to the ground level potential to generate the first ferroelectric capacitor. After the polarization of 11 is reversed,
The potential of the bit line 16 is set to the ground level.

In the case of data (0,0), the bit line 16
To the ground level potential, and the first cell plate 1
3 and the second cell plate 14 are set to the potential of the power supply level to invert the polarization of the second ferroelectric capacitor 12, and then the first cell plate 13 and the second cell plate 14
Is set to the ground level.

In the case of data (1, 0), first, the bit line 16 and the second cell plate 14 are set to the potential of the power supply level,
The potential of the first cell plate 13 is set to the ground level and the polarization of the first ferroelectric capacitor 11 is inverted. Next, after the potential of the bit line 16 is set to the ground level and the polarization of the ferroelectric capacitor 12 is inverted, the potential of the second cell plate 14 is set to the ground level.

For data (0, 1), the bit line 16
And the potential of the first cell plate 13 are set to the power supply level, the potential of the second cell plate 14 is set to the ground level, and then the potential of the bit line 16 is set to the ground level. By setting the potential of 13 to the ground level, the polarization for the next read becomes sufficiently large.

The read operation is completed by the above procedure. When data is written, the rewriting operation in the read operation is performed based on the data input from the outside. In the present embodiment, the first
Although the potentials applied to the cell plate 13, the second cell plate 14, and the bit line 16 are set to the ground level and the power supply level, these two potentials do not necessarily have to be used.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit configuration diagram of a data storage device having a switch element according to the second embodiment of the present invention. In FIG. 3, reference numeral 18 is an NMOS transistor for a switch that permits or prohibits the read operation and the write operation of the charges of the first ferroelectric capacitor 11 and the second ferroelectric capacitor 12, and 19 is an NMOS transistor 18. It is a word line for applying the gate potential of. It is also possible to use a PMOS transistor instead of the NMOS transistor 18. Although 19 is generally a signal line, it will be called a word line in this embodiment after the semiconductor memory device. The other members are denoted by the same reference numerals as those in FIG. 1 and their description is omitted. This data storage device includes a common contact 15 and a bit line 1
The electrical connection with 6 can be controlled by the voltage level of word line 12.

FIG. 4 shows a circuit configuration of a data storage device in which the data storage devices of FIG. 3 are arranged in an array and a plurality of memory cells share a bit line, a cell plate, a word line and a potential detector. There is. Since the same members as those in FIG. 3 are repeatedly arranged, the description of each member will be omitted. The operation of this data storage device will be described below.

The read operation is basically the same as that of the data storage device shown in FIG. 1, and the read operation is performed after the level of the word line 19 is raised and the NMOS transistor connected to the word line 19 is turned on. When the operation starts, the data of the memory cells connected to the word line 19 and the first cell plate 13 and the second cell plate 14 are simultaneously read to the bit line 16. The potentials are detected by a potential detector and data is output.

The rewriting operation differs from that of the device shown in FIG. 1 because a common cell plate is used. Similar to the device shown in FIG. 1, the first cell plate 13
Is set to the power supply level and the potential of the second cell plate 14 is set to the ground level, the polarization directions of the first ferroelectric capacitor 11 and the second ferroelectric capacitor 12 after the read operation is completed. Is facing upwards. When the potential of the bit line 16 is moved to the power supply level and the ground level, the upward polarization is further ensured and erroneous writing can be prevented. In the write operation, first, the potential of the bit line 16 is set to an appropriate potential, for example, a potential of about ½ of the power supply level, and then the potentials of the first cell plate 13 and the second cell plate 14 are changed. The potential is almost the same as that of the bit line 16. Next, the potential of the bit line 16 is set to the ground level when writing the data (0,0), and is set to approximately a quarter of the power supply level when the data (0,1) is written, and
In the case of 0) and data (1, 1), 1/2 of the power supply level is maintained as it is. Here, when the potential difference across both ends of one ferroelectric capacitor is ½ of the power supply voltage, the opposite polarization direction can be reversed, but in the case of ¼ of the power supply voltage If the direction of polarization cannot be reversed, the direction of polarization of the second ferroelectric capacitor 12 in the case of data (0,0) is reversed, but the direction of the ferroelectric capacitor in other cases is Do not flip. Next, when the potential of the first cell plate 13 is set to the ground level, the data (1,0) and the data (1,1)
In this case, the polarization direction of the first ferroelectric capacitor 11 is reversed. Next, the potential of the bit line 16 changes to the data (1,
In the case of 0), if the potential is set to the ground level and in other cases, the potential is maintained as it is, the polarization direction of the second ferroelectric capacitor 12 in the case of data (1, 0) is inverted. Next, the potential of the second cell plate 14 is set to the ground level. Next, the potential of the bit line 16 is set to the ground level, the potential of the word line 19 is lowered, the NMOS transistor 18 is turned off, and the rewriting operation is completed.

Regarding the write operation, the rewrite operation is performed based on the data input from the outside.

For convenience of description, the potentials of the cell plate and the bit line are set to the ground level and the power supply voltage and ½ and ¼ of the ground level. A potential difference sufficient to reverse all the polarization directions of the connected ferroelectric capacitors is applied between the first cell plate 13 and the second cell plate 14, and one ferroelectric capacitor is used at the time of rewriting or writing. Of the electric potential difference that cannot reverse the polarization direction by half the polarization direction.
Is applied between the cell plate 13 and the second cell plate 14 and the bit line 16 has a first potential difference for reversing the polarization direction of one ferroelectric capacitor when it is desired to reverse the polarization direction. The first cell plate 13 and the second cell plate 14 are provided between the cell plate 13 and the second cell plate 14 when it is not desired to reverse the polarization direction.
It suffices to apply a potential approximately in the middle of the potential. However, it is desirable to adjust the intermediate potential of the bit line if there is a difference between the first ferroelectric capacitor 11 and the second ferroelectric capacitor 12 in the coercive voltage at which the polarization direction is reversed.

As described above, in this data storage device, a desired memory cell is selected from the memory cells connected to the common bit line by controlling the ON / OFF of the NMOS transistor 18 by the voltage of the word line 19. Then, the common potential detector 17 can be used to read and write data. Also common 1st
It is possible to write desired four-valued data to each of the memory cells connected to the cell plate, the common second cell plate, and the common word line 19. In addition, as a feature of this embodiment, the NMOS transistor 1 is set after the potential of the first cell plate 13 is raised during the read operation.
By taking the operation sequence of turning on the transistors 8, the potential of the common contact 15 at the time of reading can be temporarily made higher than the potential of the common contact 15 of the data storage device shown in FIG. Therefore, it is possible to prevent the desired data from being unable to be read correctly because the common contact 15 does not have a sufficient potential to invert the polarization of the second ferroelectric capacitor 12.

The four-value data storage device in which the first ferroelectric capacitor 11, the second ferroelectric capacitor 12 and the potential detector 17 capable of detecting four potentials are connected to the common contact 15 has been described above. It is easily inferred that a data storage device having four or more values can be provided by increasing the number of ferroelectric capacitors connected to the common contact and the number of detection levels of the potential detector.

[0060]

As described above, claim 1 or claim
According to the data storage device of the invention of Item 2 , since 2n-value data corresponds to 2n potentials, n-bit information can be stored. Moreover, the common contact has a ferroelectric
There is enough potential to polarize the capacitor.
Prevent data from being read incorrectly
be able to. It also has the same capacity and hysteresis characteristics.
When a ferroelectric capacitor that
The polarization-reversed capacitor is simply replaced by the new capacitor.
If the number of passitas is the same, the voltage that appears at the common contact
It is possible to avoid the situation where the ranks are the same.

[0061]

According to the data storage device of the third aspect of the present invention, since the read operation and the write operation of the data storage device can be controlled by opening and closing the switch element, the read operation and the write operation to the data storage device are permitted. You can get the banned state. Further, since a desired data storage device can be selected and controlled from a plurality of data storage devices arranged in an array, it can be integrated on a semiconductor substrate as a semiconductor integrated circuit. In that case, in comparison with the conventional case where n ferroelectric capacitors and n switch elements were required to store n-bit information, in comparison with n ferroelectric capacitors (n ÷ series). Number of ferroelectric capacitors connected to)
The number of switch elements is sufficient, which can reduce the occupied area per bit of the ferroelectric memory device having the same storage capacity. Furthermore, since a sufficient potential for polarization of the ferroelectric capacitor can be obtained at the common contact, it is possible to prevent a situation in which data cannot be read correctly.

[0063]

[0064]

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a data storage device according to a first embodiment of the present invention.

FIG. 2 is a diagram simply showing bit line potentials corresponding to combinations of polarizations of the ferroelectric capacitors of the data storage device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a data storage device including a switch element according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a data storage device in which the data storage devices of FIG. 3 are arranged in an array and a plurality of memory cells share a bit line, a cell plate, a word line and a potential detector. .

FIG. 5 is a diagram showing a circuit configuration of a conventional DRAM.

FIG. 6 is a diagram showing a circuit configuration of a conventional ferroelectric memory device.

FIG. 7 is a diagram showing a polarization state of a ferroelectric capacitor.

[Explanation of symbols]

11 First ferroelectric capacitor 12 Second ferroelectric capacitor 13 First cell plate 14 Second cell plate 15 common contacts 16 bit line 17 Differential amplifier 18 NMOS transistor 19 word lines 51 Capacitor 52 electrodes 53 electrodes 54 NMOS transistor 55 bit line 56 differential amplifier 57 word lines 58 cell plate 61 Ferroelectric capacitor

Claims (3)

(57) [Claims] 1. A first capacitor and a second capacitor, which have a capacitive insulating film made of a ferroelectric substance and are connected in series with each other, and respective potentials of a common contact to which the first capacitor and the second capacitor are connected. and a potential detector for detecting a first and second capacitor varies the area of the respective electrodes to each other, combination of polarization direction of the first and second capacitors
Depending on the situation, four different potentials are generated at the common contact.
The four different potentials generated at the common contact.
A data storage device characterized by detecting data with a detector and outputting data. 2. A first capacitor and a second capacitor, which have a capacitive insulating film made of a ferroelectric substance and are connected in series with each other, and respective potentials of a common contact to which the first capacitor and the second capacitor are connected. and a potential detector for detecting the said first and second capacitors Ri each volume different from each other, combination of polarization direction of the first and second capacitors
Depending on the situation, four different potentials are generated at the common contact.
The four different potentials generated at the common contact.
A data storage device characterized by detecting data with a detector and outputting data. 3. The switch element according to claim 1, further comprising a switch element between the potential detector and the common contact, which opens and closes a connection between the common contact and the potential detector. The data storage device described.