JP2706584B2 - Non-volatile storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line to which a plurality of memory cells each comprising one capacitor using a ferroelectric film and one MOS transistor are connected.
The present invention relates to a nonvolatile memory device in which a plurality of sense amplifiers connected to a book are arranged on a semiconductor substrate, and a polarization direction of a ferroelectric film of the capacitor is stored in correspondence with binary information.

[0002]

2. Description of the Related Art FIG. 11 shows a conventional example of a nonvolatile memory device using such a ferroelectric film. FIG.
Reference numeral 1 denotes a part of the nonvolatile memory device, that is, two of a plurality of bit lines wired in the column direction and the peripheral configuration thereof. Two adjacent bit lines BL and bar B
A plurality of memory cells 25 are connected between L. A sense amplifier 30 for amplifying and detecting the potential between both bit lines BL and / BL is connected to one terminal of these bit lines BL and / BL.

A memory cell 25 is formed by connecting two N-channel MOS transistors 21 and 22 to two capacitors 23 and 24 having two ferroelectric films opposed to each other.
The drain of one MOS transistor 21 is connected to bit line B
L. The source of the MOS transistor 21 is connected to one end of the capacitor 23, and the gate is connected to the word line 28. Word line 28 is bit line BL,
A plurality of wires are wired in a row direction orthogonal to the bar BL. Also,
The same number of drive lines DL are wired in parallel with the word lines 28.

[0006] The drain of the other MOS transistor 22 is connected to the bit line BL, and the source is connected to the capacitor 2.
At one end of the gates 4, the gates are connected to word lines 28, respectively. The other ends of the capacitors 23 and 24 are connected to the drive line D
L.

In the nonvolatile memory device having the above configuration, 2
Writing of the value data "1" and "0" is performed as follows. First, when writing data "1", as shown in FIGS. 12 and 13, the power supply voltage V _CC is supplied to one bit line BL, the word line 28 is set to "H" level, and the MOS transistor 21 is turned on. Turn on. As a result, the power supply voltage V _CC is supplied to one end of the capacitor 23. At this time, as shown in FIG.
A voltage that rises from the ND level to the V _CC level and falls is applied in a pulse shape.

When the drive line DL is at the GND level, a voltage of V _CC is applied between both electrodes of the capacitor 23, and in response to this, an electric field E _VCC appears as shown in FIG. Charge P _S is accumulated in 23. When the drive line DL is V _CC level from this state, the external electric field is eliminated, charge P _r for polarization of the ferroelectric Shirubemaku In this state remains.

On the other hand, the other bit line bar BL is connected to GND.
The level is supplied, and at the same time, the word line is set to “H” level to turn on the MOS transistor 22, and the GND level is supplied to one end of the capacitor 24. The above-described pulse is applied to the drive line DL. Therefore, when the drive line DL is at the GND level, no external electric field is applied between both electrodes of the capacitor 24. From this state, the drive line DL becomes V
_{At the CC} level, −V is applied between both electrodes of the capacitor 23.
_Since the voltage of _CC is applied, a corresponding electric field −E _VCC appears between the two electrodes, and the electric charge −P _r is accumulated in the capacitor 24 as shown in FIG. Even drive line DL from this state no longer external electric field becomes GND level, charge -P _r for polarization of the ferroelectric film remains.

[0008] These residual charge P _r, -P _r is even longer supply voltage V _CC is supplied to the apparatus is held. Therefore, information can be held in a nonvolatile manner.

When writing data "0", the voltage levels supplied to the bit line BL and the bit line / BL are opposite to those described above. That is, the GND level is supplied to the bit line BL, and the V _CC level is supplied to the bit line BL. Thus, the residual charge of -P _r the capacitor 23 contrary to the above,
The capacitor 24 so that the charge of P _r remains.
That is, data “0” is written to the capacitor 24.

The data written as described above
Reading of "1" is performed as follows, but prior to reading, both bit lines BL and / BL are discharged and set to the GND level.
As shown in FIG. 15, the word line 28 is set at "H" level to turn on the MOS transistors 21 and 22, and the read operation is started. Subsequently, as shown in the figure, the drive line DL is raised from the GND level to the V _CC level. In the case of reading data "1", the polarization is inverted because the electric field is applied to the capacitor 23 in the direction opposite to the writing, but the polarization is not inverted because the electric field is applied to the capacitor 24 in the same direction as when writing. At this time, the bit line B
Due to the difference between the charge amount flowing into L and the bit line bar BL, the bit line BL has a slightly higher potential than the bit line bar BL. Then, this potential difference is applied to the sense amplifier 3
0 is amplified and detected. As a result, reading of data “1” is performed.

On the other hand, in the case of reading data "0", the polarization is reversed because the electric field is applied to the capacitor 24 in the direction opposite to the writing, but the electric field is applied to the capacitor 23 in the same direction as the writing. Therefore, the polarization does not reverse. At this time, the potential of the bit line BL becomes slightly larger than that of the bit line BL due to the difference in the amount of charge flowing into the bit line BL and the bit line BL. Then, this potential difference is amplified by the sense amplifier 30 in the same manner as described above, and data "0" is read.

[0012]

By the way, the memory cell 25 having the above-mentioned structure is composed of the capacitors 23 and 24 and the two N-channel MOS transistors 21 and 22 using two ferroelectric films. There are the following disadvantages. That is, since four elements are required to store one bit of information, the chip area is increased, and this has been a bottleneck in achieving high mounting of a circuit board.

An object of the present invention is to solve such a disadvantage of the prior art, and an object of the present invention is to provide a nonvolatile memory device capable of reducing a chip area and greatly contributing to high mounting of a circuit board.

[0014]

According to the present invention, there is provided a nonvolatile memory device comprising: a bit line to which a plurality of memory cells each including one capacitor using a ferroelectric film and one MOS transistor are connected; A nonvolatile memory device comprising a plurality of sense amplifiers connected to two bit lines arranged on a semiconductor substrate and storing a polarization direction of a ferroelectric film of the capacitor in correspondence with binary information. A dummy capacitor having a capacitance half the size of the capacitor of the memory cell, an access MOS transistor and a ferroelectric film of the dummy capacitor using a body film; Two dummy cells each including one MOS transistor are connected to each of the two bit lines,
Before reading the polarization charge from the capacitor of the memory cell to the bit line, the ferroelectric films of the dummy capacitors in the two dummy cells connected to the same bit line are polarized in directions opposite to each other, At the same time as reading the polarization charge from the memory cell on one of the bit lines connected to the sense amplifier, reading the polarization charge from the two dummy cells on the other bit line, the potential difference between the two bit lines is read. The sense amplifier amplifies the data and reads the data, thereby achieving the above object.

[0015]

As described above, two dummy cells each having a dummy capacitor having a capacity equal to one half of that of the memory cell are connected to two adjacent bit lines, and each dummy capacitor is connected to each other prior to the read operation. Polarized in the opposite direction,
Thereafter, if the polarization charge from the memory cell is read out to only one of the bit lines and the charge from the dummy capacitor is read out to the other bit line at the same time, the data "1" written to the capacitor of the memory cell and A charge amount corresponding to an intermediate value of the charge amount corresponding to “0” is read out to the bit line connected to the two dummy cells.

Therefore, according to such a configuration, the potential difference appearing between the two bit lines becomes the input signal of the sense amplifier connected to both bit lines, and this potential difference indicates the data "
When reading the data "1" and the data "0", the polarities are opposite and the absolute values are equal, so if this potential difference is amplified to a predetermined level by the sense amplifier, the data "1" is obtained.
And data "0" can be reliably determined.

[0017]

Embodiments of the present invention will be described below.

FIG. 1 shows a part of the circuit configuration of the nonvolatile memory device of the present invention, that is, two of a plurality of bit lines wired in the column direction and the peripheral configuration thereof. One end of two adjacent bit lines 8 and 9 is connected to a sense amplifier 14 for amplifying and detecting a potential difference between the two bit lines 8 and 9.
In the row direction orthogonal to the bit lines 8 and 9, the word line 1
A plurality of wires 5 and 16 are wired. The memory cells 3 are arranged in regions surrounded by the bit lines 8 and 9 and the word lines 15 and 16, respectively.

The memory cell 3 comprises a capacitor 1 using a ferroelectric film and an N-channel MOS transistor 2, and is connected to bit lines 8, 9 and word lines 15, 16 as follows. In other words, one of the memory cells 3 opposed to each other across the word line 16 has the drain of the MOS transistor 2 connected to the bit line 8, the source connected to one end of the capacitor 1, and the gate connected to the bit line 8. Each is connected to a word line 15. In the other memory cell 3, the drain of the MOS transistor 2 is connected to the bit line 9, and the source is connected to one end of the capacitor 1.
Gates are connected to word lines 16 respectively. The other ends of the capacitors 1 and 1 have a voltage of _の of the power supply voltage V _CC ,
That is, a voltage of 1/2 V _CC is supplied from the outside.

In addition to the above configuration, two dummy cells are connected to each of the bit lines 8 and 9. That is, the dummy cells 7a and 7b are connected to the bit line 8, and the dummy cells 7c and 7d are connected to the bit line 9. These dummy cells 7a, 7b, 7c and 7d are composed of a dummy capacitor 4 using a ferroelectric film and MOS transistors 5 and 6. These MOS transistors 5 are all N-channel MOS transistors. In contrast, MO
Among the S transistors 6, the MOS transistors 6 forming the dummy cells 7a and 7d are P-channel MOS transistors, and the MOS transistors forming the dummy cells 7b and 7c are N-channel MOS transistors.

The specific connection between the dummy cell 7a and the bit line 8 is as follows. That is, the drain of the MOS transistor 5 is connected to the bit line 8, the source is connected to one end of the dummy capacitor 4, and the gates are connected to the word lines 15, 16.
Are connected to the dummy cell word lines 17 wired in parallel with. The dummy capacitor 4 is formed using a ferroelectric film, and its capacity is set to half the capacity of the capacitor 1 of the memory cell 3. That is, as shown in the figure, C _D = １ ／ C _S. The other end of the dummy capacitor 4 is supplied with a voltage of 1/2 V _CC from outside. The drain of the MOS transistor 6 is a MOS
The source of the transistor 5 and one end of the dummy capacitor 4 are connected, and the source is connected to the V _CC terminal. Furthermore,
The gate of the MOS transistor 6 is connected to a Φ _PDUM signal line 19 wired in parallel with the dummy cell word line 17.

The connection between the dummy cell 7b and the bit line 8 is M
This is performed by connecting the drain of the OS transistor 5 to the bit line 8. The gate of the MOS transistor 5 is
Connected to the gate of transistor 5. The source is connected to one end of the dummy capacitor 4 constituting the dummy cell 7b as described above. The drain of the MOS transistor 6 is connected to the source of the MOS transistor 5 and one end of the dummy capacitor 4, and the source is connected to the GND terminal. The gate is connected to the Φ _PDUM signal line 20.

The gate of the MOS transistor 6 constituting the dummy cell 7c is connected to the Φ _PDUM signal line 20. The connection between the dummy cell 7c and the bit line 9 is M
This is performed by connecting the drain of the OS transistor 5 to the bit line 9. The source of MOS transistor 5 is connected to one end of dummy capacitor 4 and the drain of MOS transistor 6. The source of the MOS transistor 6 is GND
Connected to terminal. The gate is connected to the gate of the MOS transistor 5 forming the dummy cell 7d. The gate of the MOS transistor 5 is connected to the dummy cell word line 1
8 is connected.

The connection between the dummy cell 7d and the bit line 9 is as follows.
This is performed by connecting the drain of the MOS transistor 5 to the bit line 9. The source is connected to one end of the dummy capacitor 4 and the drain of the MOS transistor 6.
The gate is connected to the dummy cell word line 18. MOS
The source of the transistor 6 is connected to the V _CC terminal, and the gate is connected to the Φ _PDUM signal line 19 wired between the dummy cells 7c and 7d.

Further, the sense amplifier 1 between the bit lines 8 and 9
A bit line equalizing circuit 13 is provided in a portion corresponding to a portion between the memory cell 4 and the memory cell 3 adjacent thereto. The bit line equalizing circuit 13 has three P-channel MOSs.
The gates of these MOS transistors 10, 11, and 12 are all connected to a .PHI. _BEQ signal line 21 _disposed between the sense amplifier 14 and a word line 15 adjacent thereto. You. The sources of the MOS transistors 10 and 12 are connected to V _CC
, And the drains are connected to the bit lines 8 and 9, respectively. On the other hand, the drain of the MOS transistor 11 is connected to the bit line 8 and the source is
It is connected to the.

[0026] The sense amplifier 14 is connected to the bit line 8 and 9 as described above, a circuit for detecting and amplifying a small potential difference appearing between the bit lines 8 and 9, [Phi _s signal instructing the start amplification, i.e. When the “H” level φ _s signal is input, the amplification operation starts.

Next, the nonvolatile memory device having the above-described configuration is used.
Operating principle of the memory cell 3, ie, data writing
Diagram showing the operating principle of the memory cell 3 in reading and reading
This will be described with reference to FIGS. In addition, binary data
Writing “1” and “0” is connected to the word line 15.
Taking the memory cell 3 as an example, first, the word line
15 is set to "H" level, and the memory cells connected thereto
3 MOS transistor 2 to turn on the memory cell 2
select. Subsequently, the bit line 8 is set to a predetermined level (V_CCMa
Or GND), and a half of the voltage is applied between the two electrodes of the capacitor 1.
V_CCOr -1 / 2V _CC/ 2 voltage is applied.
The polarization direction of the ferroelectric film in correspondence with the binary data.
U. The details will be described below.

First, when writing data "1", as shown in FIG. 2, the power supply voltage V _CC is supplied to the bit line 8 and the word line 15 is set to "H" level to turn on the MOS transistor 2 and the capacitor is turned on. supplying a power supply voltage V _CC to 1 of one end. As shown in FIG.
/ 2V _CC voltage is applied. As a result, the capacitor 1
Of the voltage of 1 / 2V _CC is applied between the electrodes, to which corresponds appear field E _VCC shown in FIG. 3, the charge P _s
Is stored in the capacitor 1.

Subsequently, the word line 15 is changed from this state to "
When the MOS transistor 2 is turned off at L level,
Although the external electric field disappears, the electric charge _Pr remains due to the polarization of the ferroelectric film. The supply of the power supply voltage V _CC to the nonvolatile memory device stops, and the other end of the capacitor 1
Even when the voltage of / 2V _CC is not supplied, the residual charge _Pr is retained. That is, data “1” written in the memory cell 3 in a nonvolatile manner can be held.

Reading of data "1" is performed as follows. First, as shown in FIG. 4, the bit line 8 is precharged to the V _CC level prior to the read operation.
Subsequently, the word line 15 is set to "H" level to turn on the MOS transistor 2. As a result, the electric charge of the bit line 8 precharged to the power supply voltage V _CC is supplied to the capacitor 1 to cause charge sharing. Here, the capacity of the bit line 8 is considered to be at least ten times larger than the capacity of the capacitor 1 of the memory cell 3 in a normal case. Therefore, a voltage close to the power supply voltage V _CC is supplied to one end of the capacitor.

The other end of the capacitor 1 has a voltage of 1/2 V _CC
Is applied. Consequently, the voltage close to 1 / 2V _CC is applied between the electrodes of the capacitor 1, the electric field E _VCC corresponding thereto as shown in FIG. 5 appears, the charge P _s is accumulated. At this time, the amount of charge transferred from the bit line 8 to the capacitor 1 is P _s -P _r . Assuming now that the capacity of the bit line 8 is C _B and the capacity of the capacitor 1 is C _s , the data “
Voltage level V _BIT1 of bit line 8 when 1 ”is read
Is represented by the following equation.

[0032] In other _{words, V CC · C B - (} P s -P r) = V
Since the relationship between the _{BIT1 · (C B + C s} ) is _{established, V BIT1 = (V CC ·} C B - (P s -P r)) / (C B + C s) ... to become.

To write the data "0", as shown in FIG. 6, the GND level is supplied to the bit line 8, the word line 15 is set to the "H" level, the MOS transistor 2 is turned on, and one end of the capacitor 1 is connected. Supply GND level. As shown in FIG.
A voltage of V _CC is applied. As a result, a voltage of -1/2 V _CC is applied between both electrodes of the capacitor 1, and an electric field E _GND appears between both electrodes of the capacitor 1 as shown in FIG. P _s accumulates. When turning off the MOS transistor 2 and from this state the word lines 15 to the "L" level, but the external electric field is eliminated, charge -P _r remains the capacitor 1 due to the polarization of the ferroelectric film.
Even when the supply of the power supply voltage V _CC to the nonvolatile memory device is stopped and the voltage of 1/2 V _CC is not supplied to the other end of the capacitor 1, the residual charge −P _r is retained. That is, data “0” written in the memory cell 3 in a nonvolatile manner can be held.

Reading of data "0" is performed as follows. First, as shown in FIG. 8, the bit line 8 is precharged to the V _CC level prior to the read operation.
Subsequently, the word line 15 is set to "H" level to turn on the MOS transistor 2. As a result, the bit line 8 precharged to the power supply voltage V _CC is supplied to the capacitor 1,
Initiate charge sharing. As described above, bit line 8
Is sufficiently larger than that of the capacitor 1, and a voltage close to the power supply voltage V _CC is supplied to one end of the capacitor 1. In addition, as shown in FIG.
A voltage of 1/2 V _CC is applied. Consequently, the voltage close to 1 / 2V _CC is applied between the electrodes of the capacitor 1, as shown in FIG. 9, the electric field E _VCC corresponding thereto appears, the charge P _s is accumulated. At this time, the amount of charge transferred from the bit line to the capacitor 1 is P _s + P _r . Now, _assuming that the capacity of the bit line 8 is C _B and the capacity of the capacitor 1 is C _s , the voltage V _BIT0 of the bit line 8 when data “0” is read is expressed by the following equation. That is, V _CC · C _B
- since (P _s + P _r) = relationship of _{V BIT0 · (C B + C} s) is _{established, V BIT0 = (V CC ·} C B - (P s + P r)) / (C B + C s) ... and Become.

Next, a specific procedure of a read operation in the nonvolatile memory device of the present invention will be described with reference to FIG. First, prior to the read operation, the Φ _BEQ signal is input from the Φ _BEQ signal line 21 to the bit line equalizing circuit 13 at the timing shown in FIG. 10A, and the bit line equalizing circuit 13 is operated. That is, the P-channel transistors 10, 11, and 12 are turned on, and the bit lines 8, 9 are connected to V _CC.
Precharge to level. At the same time, FIG.
As shown in (b) and (c), the Φ _PDUM signal line 20 and the bar Φ _PDUM signal lines 19, 19 _{cause the} dummy cells 7a, 7b, 7
The Φ _PDUM signal and the Φ _PDUM signal are input to c and 7d, respectively. Thereby, the two dummy cells 7a, 7b (or 7c, 7d) connected to the same bit line 8 (or 9)
The ferroelectric films of the dummy capacitors 4 are polarized in opposite directions.

Subsequently, when the word line 15 becomes "H" level at the timing shown in FIG. 10D, the dummy cell word line 18 is simultaneously set at "H" as shown in FIG.
Then, the φ _s signal input to the sense amplifier 14 becomes “H” at the timing shown in FIG.
When the level reaches the level, the sense amplifier 14 simultaneously starts the amplification operation. More specifically, the sense amplifier 14 reads the polarization charge from the memory cell 3 selected from one of the two bit lines 8 and 9 (or 9), and reads the other bit line 9 (or 9). Or 8), two dummy cells 7c and 7d (or 7) whose polarization directions are opposite to each other.
a, 7b).

FIG. 10 (g) shows the voltage level of the bit line connected to the memory cell 3 when data "1" is read, and FIG. 10 (h) shows the memory level when data "0" is read. The change of the voltage level of the bit line connected to the cell 3 is shown.

When the read data is "1", the voltage level V _BIT1 represented by the above equation appears on the bit line 8 (or 9) from which the polarization charge has been read from the memory cell 3, and the read data becomes "0". ", The voltage level V _BIT0 shown by the above equation appears. On the other hand, dummy cells 7c, 7d
The voltage level V _BITD of the bit line 9 (or 8) from which charges from (or 7a, 7b) are read is expressed by the following equation.

That is, V _CC · C _B- (P _s -P _r ) / 2
- since _{(P s + P r) /} 2 = relationship of _{V BITD · (C B + C} s) is _{established, V BITD = (V CC ·} C B -P s) / (C B + C s) ... to become.

As described above, according to the nonvolatile memory device of the present invention, when data “1” is read, ΔV _{1 is applied} between the two bit lines 8 and 9 connected to the sense amplifier 14.
= V _BIT1 −V _BITD appears, and the potential difference ΔV ₁ becomes an input of the sense amplifier 14. The sense amplifier 14
This potential difference ΔV ₁ is amplified at the timing shown in FIG. 10F when the Φs signal at the H level is input. Similarly, when the read data is “0”, ΔV ₀ = V _BITD −
The potential difference of V _BIT0 becomes the input of the sense amplifier 14, and "
This potential difference △ at the time when the H ″ level Φ _s signal is input.
Amplify V ₀ .

The specific values of the potential differences ΔV ₁ and ΔV ₀ are given by the following formulas and formulas by using the above formulas and formulas.

[0042] _{△ V 1 = (V CC ·} C B - (P s -P r)) / (C B + C s) - (V CC · C B -P s) / (C B + C s) = P r / (C _B + C _s )... ΔV ₀ = (V _CC · C _B -P _s ) / (C _B + C _s )-(V _CC · C _B- (P _s + P _r )) / (C _B + C _s) ) = P _r / (C _B + C _s ) As can be seen from the above formulas and formulas, in the nonvolatile memory device, when data “1” and “0” are read, the absolute value between the bit lines 8 and 9 is required. Since a small potential difference having the same value and opposite polarity appears, if this potential difference is amplified to a predetermined level by the sense amplifier 14, the data "
It is possible to distinguish between 1 "and" 0 ", that is, according to the nonvolatile memory device of the present invention, it is possible to reliably read out the binary information held in a nonvolatile manner.

In addition, according to the nonvolatile memory device of the present invention, although the dummy cells 7a, 7b, 7c and 7d are required, the memory cell 3 is composed of one capacitor 1 and one MO.
Since the memory cell 3 can be constituted by the S-transistor 2, the chip area of the memory cell 3 can be remarkably reduced as compared with the memory cell 25 having the conventional structure. Also, the dummy cells 7a, 7b, 7c,
7d only needs to connect two to each bit line,
The number is significantly smaller than the number of memory cells 3. Therefore, according to the present invention, the chip area of the entire nonvolatile memory device can be significantly reduced as compared with the conventional example.

[0044]

As described above, according to the nonvolatile memory device of the present invention, a memory cell can be constituted by one capacitor using a ferroelectric film and one MOS transistor. It can be much smaller than the example,
As a result, the chip area of the entire nonvolatile memory device can be significantly reduced. Therefore, the use of the nonvolatile memory device of the present invention has an advantage that the mounting of the circuit board can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a nonvolatile memory device of the present invention.

FIG. 2 is a diagram for explaining an operation of a memory cell when writing data “1”;

FIG. 3 is a diagram showing a change in a charge stored in a capacitor when data “1” is written.

FIG. 4 is a diagram for explaining an operation of a memory cell when data “1” is read.

FIG. 5 is a diagram showing a change in a charge stored in a capacitor when data “1” is read.

FIG. 6 is a diagram for explaining an operation of a memory cell at the time of writing data “0”.

FIG. 7 is a diagram showing a change in a charge stored in a capacitor when data “0” is written.

FIG. 8 is a diagram for explaining an operation of a memory cell when data “0” is read.

FIG. 9 is a diagram showing a change in a charge stored in a capacitor when data “0” is read.

FIG. 10 is a timing chart showing a read operation in the nonvolatile memory device of the present invention.

FIG. 11 illustrates a conventional example of a nonvolatile memory device.

FIG. 12 is a diagram for explaining an operation of a conventional memory cell at the time of writing data “1”.

FIG. 13 is a diagram showing a change in accumulated charge of a conventional memory cell when data “1” is written.

FIG. 14 is a diagram for explaining an operation of a conventional memory cell at the time of reading data “1”.

FIG. 15 is a diagram showing a change in stored charge of a conventional memory cell when data “1” is read.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Capacitor which comprises a memory cell 2 MOS transistor which comprises a memory cell 3 Memory cell 4 Dummy capacitor 5 and 6 MOS transistor which comprises a dummy cell 7a, 7b, 7c, 7d Dummy cell 8, 9 Bit line 13 Bit line equalizing circuit 14 Sense Amplifier 15, 16 Word line 17, 18 _Dummy cell word line 19 bar Φ _PDUM signal line 20 Φ _PDUM signal line 21 bar Φ _BEQ line V _BIT1 Voltage level of bit line when _BIT1 data “1” is read V _BIT0 data “0” Voltage level of the bit line when data is read out V Voltage level of the bit line when charge from the _BITD dummy cell is read out

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication H01L 27/108 29/788 29/792

Claims (1)

(57) [Claims] A capacitor using a ferroelectric film and an MO
A plurality of bit lines connected to a plurality of memory cells each including one S transistor, and a plurality of sense amplifiers connected to the two bit lines are arranged on a semiconductor substrate, and polarization of a ferroelectric film of the capacitor is arranged. What is claimed is: 1. A non-volatile memory device for storing a direction in correspondence with binary information, comprising:
And two dummy cells each composed of one dummy capacitor having a capacity of 2 and one MOS transistor for access and one MOS transistor for polarizing the ferroelectric film of the dummy capacitor. And before reading out the polarization charge from the capacitor of the memory cell to the bit line, read the ferroelectric material of the dummy capacitor in the two dummy cells connected to the same bit line. The films are polarized in opposite directions so that one bit line connected to the sense amplifier reads the polarization charge from the memory cell, and the other bit line receives the polarization charge from two dummy cells. A non-volatile memory device in which data is read out by amplifying the potential difference between the read and both bit lines by the sense amplifier.