JP3332696B2 - Digital recording signal reproducing apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recording signal reproducing apparatus and method, and more particularly, to a digital magnetic recording signal reproducing apparatus and method suitable for reproducing a signal recorded at high density on a magnetic recording medium.

[0002]

2. Description of the Related Art With the miniaturization of information storage devices typified by magnetic disks, there is a demand for an improvement in recording density on a recording medium. In addition, with the increase in the calculation speed on the computer side for processing the recording information, there has been a demand for an increase in the speed of recording / reproducing a signal on a recording medium. From such a background, a recording / reproducing method in the magnetic disk field uses, for example, a coding rate of 2/3 as a recording code.
From the method of reproducing a recording signal by peak detection using a (1,7) run-length limiting code, a (0,4) run-length limiting code of coding rate 8/9 is used as a recording code, and a partial response class 4 ( Below, PR
No. 4).
Here, the coding rate m / n means that m-bit user data is converted into an n-bit recording code, and the (d, k) code reverses the recording magnetic field when the recording code is “1”. , "0", the presence of a code sequence between "1" and "1" is allowed on the premise of the so-called NRZI (Non Return to Zero Inverse) recording that maintains the state of the conventional magnetic field. Means that the minimum number of “0” is d and the maximum number is k. Regarding these technical features, for example, Journal of the Japan Society of Applied Magnetics, vol.
No. 08/1994, "PRML and Coding Techniques".

[0003] The magnetic recording / reproducing apparatus is basically designed on the assumption that the reproducing response of an isolated pulse is linearly added. However, when recording / reproducing a signal to / from a magnetic recording medium, a nonlinear element is essentially used. Is accompanied. The following two main non-linear components have been taken up conventionally. (1) Nonlinear transition shif
This is referred to as t), and refers to a change in which the magnetization reversal interval on the recording medium moves nonlinearly in accordance with the adjacent reversal interval in the recording signal sequence in the process of recording / reproducing a signal on / from the magnetic medium. To deal with this phenomenon, the relationship between the signal sequence to be recorded and the movement of the transition point that actually appears on the recording medium is grasped in advance by a recording / reproducing experiment, and the recording circuit performs magnetization reversal according to the recording signal sequence. By compensating the interval, it is possible to make the non-linear component hardly appear in the reproduced signal. (2) In a read head using a magneto-resistive element, if the bias applied to the magneto-resistive element deviates from a reference value, even if the input magnetic field of the read head has the same magnitude on the positive side and the negative side, the output signal of the head Has a phenomenon that the signal amplitude is different between the positive side and the negative side. For this non-linear phenomenon, it has been proposed to perform amplitude correction in an analog-to-digital converter for digitally processing a reproduced signal.

As the high-density recording further proceeds, the above (1),
In addition to (2), partial erasure phenomenon (PatialErasure, hereafter,
A nonlinear component called “PE phenomenon” becomes remarkable.
This is a phenomenon in which, when there is a portion (isolated bit) having a narrow magnetization reversal interval in a signal sequence to be recorded, the amplitude of a reproduced signal obtained from that portion becomes smaller than a value expected from linear addition. The partial response equalization method described above
Since linear addition is premised, PE measures become important as the recording density increases. However, up to now, there has been no report referring to specific PE measures in reproducing digital magnetic recording signals.

[0005]

One method for coping with the above-mentioned PE phenomenon is, as shown in FIG. 2, a judgment comprising a feedforward filter (hereinafter, referred to as FFF) 20 and a feedback filter (hereinafter, referred to as FBF) 30. It uses a feedback equalizer. The reproduction signal V1 from the magnetic head is input to the FFF 20. FFF20 is
For example, a reproduced signal S1 including an isolated bit “1” as shown by a recording signal “0001000.
As shown by 0, the response becomes zero at each sampling timing before time t = -Tc, is equalized to a predetermined reference amplitude value at t = 0, and each sampling timing (Tc, 2Tc, 3Tc) after t = Tc. ,...) Are equalized so that a response remains. That is, the FFF 20
Only the first half of the response of the bit is equalized.

[0006] Since the equalization by the FFF 20 does not narrow the range of response, it is not necessary to emphasize the high frequency region of the signal. For this reason, compared to the conventional partial response equalization method in which the response waveform is kept within a predetermined range before and after the bit, noise emphasis by equalization is less. The FFF 20 has a so-called transversal filter structure, and includes a plurality of delay elements 21 (21-1 to 21-) for sequentially delaying the reproduction signal V1.
N) and a coefficient operation element 22 (22-1 to 22-) provided with an output tap of each delay element and an input tap of a first stage.
N) and an addition circuit 23 for adding the outputs of the coefficient calculation elements, and the above-described equalization characteristic is obtained by giving the coefficient of the coefficient calculation element 22 at each tap.
The output signal V of the FFF 20 obtained from the addition circuit 23
The signal 20 is input to a feedback filter (FBF) 30, and the “1” and “0” signals are identified. The above FBF3
0 indicates an identification circuit 31, a shift register 32 for sequentially storing the identification result (output signal V30) of the identification circuit 31 over a predetermined period, and a random access memory (RA) accessed using the contents of the shift register 32 as an address.
M) 33, and a subtraction circuit 34 for subtracting the output of the RAM from the input signal V20 to the identification circuit 31.

In the above-mentioned decision feedback equalizer, the FFF in the preceding stage is used.
Since the output signal V20 of 20 includes the residual response of the latter half of each bit, it is necessary to remove the residual response component from the input signal of the identification circuit 31 in the subsequent stage FBF30. For this reason, the already determined identification results of the plurality of bit periods are held in the shift register 32, the estimated amount of the response characteristic of the latter half of each bit is read out from the RAM 33, and the estimated amount is calculated from the input signal V20 by the subtraction circuit 34. Is to be removed. Here, if the value of the estimated amount set in the RAM 33 is a value that takes into account not only the linear component but also the nonlinear component of the interference waveform, it is possible to deal with the above-described nonlinear component in high-density recording. However, in the decision feedback equalizer, the response of the latter half of each bit remaining in the output of the FFF 20 is reduced by several bits before that.
Since the estimation is performed based on the identification result in a period of several tens of bits, if the identification result is erroneous once, erroneous equalization based on an erroneous estimation amount for subsequent bits is performed, and the error may be transmitted. .

It is an object of the present invention to provide a digital recording signal reproducing apparatus and a reproducing method capable of accurately reproducing information recorded on a magnetic storage medium at high density without using a feedback system. Another object of the present invention is to apply a partial response class 4 (PR4) or an EPR4 equalizing circuit extended from the partial response class 4 to deal with a nonlinear phenomenon appearing in a reproduced signal from a magnetic storage medium. An object of the present invention is to provide a digital recording signal reproducing apparatus and a reproducing method suitable for magnetic recording. Another object of the present invention is to apply a PR4 or EPR4 equalizing circuit,
In particular, it is an object of the present invention to provide a digital recording signal reproducing apparatus and a reproducing method capable of coping with a partial erasure (PE) phenomenon of magnetic recording occurring on a magnetic storage medium on which high density recording is performed. Another object of the present invention is to provide a high-speed digital recording signal reproducing apparatus capable of applying PR4 or EPR4 equalization and maximum likelihood decoding and capable of coping with non-linear phenomena of reproduced signals accompanying high-density magnetic recording, in particular, PE phenomena. It is to provide a reproduction method. Still another object of the present invention is to reproduce digital recording signals suitable for high-density magnetic recording in which the ratio T50 / Tc of the recording signal bit width Tc of the reproducing system to the reproducing half-value width T50 for isolated magnetization reversal is about 2.0 or more. It is to provide an apparatus and a reproduction method. Still another object of the present invention is to provide
It is an object of the present invention to provide an equalization decoding device suitable for high-density magnetic recording capable of coping with a non-linear phenomenon appearing in a reproduced signal from a magnetic storage medium.

[0009]

In order to achieve the above object, in a digital magnetic recording signal reproducing apparatus according to the present invention, a reproduction signal from a magnetic recording medium on which a digital signal is recorded is equalized by an equalizing circuit. By passing the output signal of the circuit through a delay circuit that delays by one sample time, an equalized output signal for a plurality of samples (a plurality of bits) adjacent to each other in the recording code string is generated, and the output signal is parallel to the maximum likelihood decoding processing circuit. To supply. The equalization circuit is, for example, an equalization circuit of PR4 or EPR4, and the maximum likelihood decoding processing circuit is, for example, a method of the equalization circuit and the number of samples (number of bits) of a signal supplied from the equalization circuit. Signal (recording code)
Multiple ACSs (Add, Compare and S
elect) An arithmetic unit, a traceback RAM having a plurality of path memory areas, and a majority logic circuit.

Each of the ACS operation units is composed of a plurality of branch metric operation circuits corresponding to a change in state of a recording code assumed in advance. One of the features of the present invention is that a branch metric calculation circuit that calculates branch metrics (state transition likelihood) for a state change in which non-linear distortion (partial erasure phenomenon) is expected in an equalization response has an amplitude of the equalization response. The object of the present invention is to execute a likelihood calculation process (calculation formula) using a calculation parameter based on deterioration.

The output of each branch metric operation circuit is added to, for example, the value of the path metric stored in the register means corresponding to the state of the input signal to give a new branch metric value. In each ACS operation unit, when a previous state of the recording code is specified by selecting a branch metric having a minimum value (or a maximum value) from a plurality of branch metric values calculated in each operation cycle, The value of the branch metric corresponding to the previous state is stored in the register as the path metric used in the next calculation. Each ACS operation unit notifies the other ACS operation units of the value of the branch metric selected by itself, and stores it in each register means as a new path metric value corresponding to the signal state. The RAM forms a plurality of path memories corresponding to the ACS operation units, and each path memory constitutes a multi-stage shift register for storing a signal state value. Since each ACS operation unit corresponds to a unique signal state, each path memory is also associated with a unique signal state value. For example, i-th ACS
When the arithmetic unit determines that the previous state of the recording code is Sj, a series of signal state values stored in the path memory corresponding to Sj is taken into the shift register of the i-th path memory, Next, a signal state value unique to the i-th ACS operation unit is set in the first stage of the shift register. By repeating such an operation, the most probable state value sequence is set in each path memory as the previous state. The state value output from the last stage of each shift register is input to, for example, a majority logic circuit, and the signal state value to be output from the maximum likelihood decoding processing circuit is determined.

[0012]

FIG. 1 is a block diagram showing a main part of a signal system of a digital recording signal reproducing apparatus according to the present invention applied to a magnetic disk recording and reproducing apparatus. In this embodiment, an 8/9 conversion recording code is applied as a recording signal on a magnetic disk, and a partial response class 4 maximum likelihood decoding method (PR4ML: Partial Response c) is applied to a signal reproducing circuit.
lass 4Maximum Likelihood). Reference numeral 1 denotes a reproducing head for reading a recording signal from a magnetic disk. A reproducing signal output from the reproducing head is amplified by a preamplifier 2 and then a low-pass filter 3 removes noise components other than the signal band. Reference numeral 4 denotes an analog-to-digital converter (A / D converter) which discretizes (samples) the reproduced signal in a bit cycle in accordance with the reproduced clock signal supplied from the clock extracting circuit 5 and converts the reproduced signal into a digital data value. V1 is supplied to the equalization decoding circuit 10. The clock extraction circuit 5 extracts a clock component from an output signal V11 of a digital filter which is a component of the equalization decoding circuit 10, and generates a reproduced clock having a bit period.

The equalization decoding circuit 10 includes a digital filter 11 for performing PR4 waveform equalization, a one-sample delay circuit 12, and a maximum likelihood decoding processing circuit 13. The output signal (digital data value) V1 of the A / D converter 4 is subjected to digital processing by the digital filter 11. Here, when the recording code is “1”, the pulse is a positive pulse, and “0”.
NRZL (Non Return Zero Leve
l) Explaining on the premise of recording, when the recording code is “1”, the response of the equalized output is “1, 0, −1” and the recording code is “0”.
In the case of, equalization processing is performed so that the equalization output response becomes "-1, 0, 1". Therefore, for example, when the recording signal (code) sequence is “0011” as shown in FIG. 4A, the recording waveform is shown in FIG. 4B, and the equalized output response corresponding to each bit is shown in FIG. As shown in (C), an output signal V11 is obtained from the digital filter 11 as shown in (D) of FIG. FIG. 4 shows a case where the code immediately before the recording signal sequence “0011” is “0”.

One feature of the present invention is that the equalized output from the digital filter 11 and the one-sample delay circuit 1
It is to provide an equalized output signal for each two samples to the maximum likelihood decoding processing circuit 13 by making a set (or a pair) with the equalized output of one sample before output from 2. In the following description, the symbols y (2k) and y (2k-1) are used especially when one set of equalized outputs is handled in a distinguished manner. Where 2k
And 2k-1 represent time, k is an arbitrary integer, and means that equalization output is performed in units of one sampling clock.

The maximum likelihood decoding processing circuit 13 includes an add, compare and select circuit (hereinafter referred to as an ACS circuit) 7 for calculating the likelihood corresponding to the identification signal state every two samples. , Traceback RAM
(Path memory) 8 and a majority logic circuit 9, and the output of the majority logic circuit 9 becomes a decoded signal V10.

The ACS circuit 7 supplies the PR4 equalized signal to 2
Since the samples are supplied as a set for each sample, the state of the input signal handled by the ACS circuit 7 is represented by four states of “00”, “01”, “10”, and “11” in the state of the recording code. . In the case of the recording code sequence “0011” illustrated in FIG. 4, when the code state transits from “00” to “11”, if there is no noise, the input signal of the ACS circuit 7 is (D ), It changes from “0,0” or “−2,0” to “+ 2, + 2”. In the following description, the states of the above-mentioned reference numerals “00”, “0”
State symbols S0 to S3 are used corresponding to "1", "10", and "11". In an actual application circuit, the digital filter 11
Since the output signal V11 contains noise, it is necessary to calculate the likelihood (called metrics) of these state transitions (called branches) in order to perform maximum likelihood decoding. One of the features of the present invention resides in that, in the calculation of the branch metrics, an arithmetic expression considering the PE phenomenon is applied as described later.

For example, the input signal y (2) of the ACS circuit 7
When k) and y (2k-1) change from the “01” state S1 to the “00” state S0, the recording code string “01” is output from the recording medium.
That is, a signal corresponding to "00" has been read. In the present invention, since the second bit “1” in the recording code string is a pulse having the minimum magnetization reversal width, the PE phenomenon occurs on the recording medium, and the equalization circuit (digital filter) 11 Is smaller than that at the time of reading the continuous bit “1” having a large magnetization reversal width. Therefore, in the ACS circuit 7, for the normal bit “1”, the equalization response output is set to “1,0, −”.
For the bit "1" where the PE phenomenon is expected to occur, the equalizer outputs a response signal with a magnitude of "α, 0, -α" smaller than the normal amplitude, while treating it as "1". Treat as Α is a value satisfying 0 <α <1, and an appropriate value is set according to the recording density. When the bit “1” continues, the equalization response output of each bit is treated as “1, 0, −1”. The ACS circuit 7 is associated with the current states S0 to S3 as shown in FIG. Operation units 70
(70-0 to 70-3) and a parameter setting register 76. Each operation unit 70 has four branch metric operation circuits associated with the previous states S0 to S3 and a path metric register, as described later, and stores the operation result of each branch metric operation circuit and the path metric register. From the stored value,
The state transition likelihood (branch metrics) from the four states considered as the prior states to the current state is calculated. For example, in the first ACS operation circuit 70-0, the states S0 to S0
The branch metrics from S3 to the current state S0 are calculated, and the calculated results are compared to determine the most probable state transition (previous state Sj). Similarly, the second to fourth ACS operation circuits 70-1 to 70-3
Calculates branch metrics from the states S0 to S3 to the current state S1, S2 or S3, respectively, and finds the most probable state transitions. According to the present invention, in each of the ACS operation circuits 70-0 and 70-3, when the recording code string to be subjected to the state transition is a bit pattern accompanied by the PE phenomenon, the above-described amplitude degradation is output to the equalization response output. Assuming that there is a branch metric, a branch metric calculation is performed based on a calculation formula having parameters in consideration of the PE phenomenon.

The determination result of the state transition (prior state Sj) performed by each of the ACS operation circuits 70-0 and 70-3 is based on the signal V7.
Traceback RAM as (V7-0 to V7-3)
8 given. The RAM 8 has a plurality of path memories 80-0 to 80-3 corresponding to the respective ACS operation units, and each path memory constitutes a multistage serial shift register for storing the most likely prior state. . For example, the output signal V7- of the first ACS operation circuit 70-0
If 0 indicates the prior state Sj = S2, the path memory (shift register) 80-0 stores the third ACS operation circuit 70- which calculates the state transition likelihood for the current state S2.
Then, the stored contents of the path memory 80-2 corresponding to 2 are fetched, and thereafter, the latest state value (the value “00” of S0) is set in the first stage of the shift register with the shift operation. Similarly, the other path memories 80-1 to 80-3 also respond to the previous state Sj indicated by the output signals V7-1 to V7-3 from the paired ACS operation circuits 70-1 to 70-3, respectively. After fetching the contents of the path memory corresponding to the Sj value, the state value unique to the own path memory is set to the first stage. By repeating the above operation, the most probable state transition process determined by each ACS operation circuit is stored in each path memory, and after a predetermined number of ACS operations determined by the number of stages of the shift register, the output from each shift register is output. Among the state values V8-0 to V8-3, the state value having the largest number is selected by the majority logic circuit 9 and output as the equalization code circuit output V10.

FIG. 6 shows the configuration of the ACS operation unit 70-0. The ACS operation unit 70-0 outputs the state S0,
That is, four branch metric calculation circuits 7 for calculating metrics regarding the state transition to the recording code "00"
1-0 to 71-3. As shown in FIG. 7, the state S0 at an arbitrary time 2k may transition from the four states S0, S1, S2, and S3 at a time 2k-2 two samples earlier. The other states S1 to S3 may also transition from each of the four states. A
The four branch metric operation circuits 71-0 to 71-3 of the CS operation unit 70-0 each have a “state S0
From state S1 to S0 "," transition from state S1 to S0 ",
This is for performing a metric operation (likelihood calculation) for “transition from state S2 to S0” and “transition from state S3 to S0”. The function of each branch metrics operation circuit is as follows.

(1) Function of operation circuit 71-0 (state S0
Transition from S0 to S0): In this case, the recording code string is “00” at times (2k−3) to (2k−2) as shown in FIG. ) To (2k) are "00". Since there is no magnetization reversal in the recording code string in this case, P
There is no need to consider the E phenomenon. The PR4 equalized outputs y (2k-1) and y (2k) corresponding to the recording code string are
When there is no noise, it is "0,0". Therefore, the branch metric B (S0-S0) is given by the following equation. B ((S0-S0) 2k ) = (y (2k-1) -0) 2 + (y (2k) -0) 2 + P (S0 (2k-2)) = y (2k-1) 2 + y ( 2k) ² + P (S0 (2k-2)) (Equation 1) Here, P (S0 (2k-2)) is the time 2k− two samples earlier.
2 shows the value of the path metrics in the state S0. Also, (y (2k-1) -0) ² + (y (2k) -0) ² corresponds to the path distance between the state of the input signal and the state S0. y (2k-
1) The terms ² and y (2k) ² can be excluded in advance because they are common terms in all branch metrics. Therefore, the above equation (Equation 1) can be modified as the following equation.

B ((S0−S0) 2k) = P (S0 (2k−2)) (Equation 2) The branch metric B ((S0−S0) 2k) relating to the transition from the state S0 to the state S0 is As shown in FIG. 6, the branch metric calculation circuit 7 is added by the addition circuit 72-0.
1-0 and the symbol S given from the register 75.
It is obtained by adding the value of the path metric P (S0 (2k-2)) indicated by 0. Therefore, the expression (Equation 2) means that the branch metrics operation circuit 71-0 only needs to have a function of outputting a fixed value “0”.
In this case, the output value “0” of the arithmetic circuit 71-0 is input to the adding circuit 72-0, and this is added to the path metric P (S0 (2k−2)) given from the register 75, This means that the value of the branch metric B ((S0-S0) 2k) has been calculated. B output from adder 72-0
The value of ((S0-S0) 2k) is input to a 4-input comparator 73 and a selection circuit (selector) 74.

(2) Function of operation circuit 71-1 (state S1
From S0 to S0): As shown in FIG. 9A, the recording code string corresponding to this state transition is from time (2k-3)
"01" at (2k-2), "00" at time (2k-1) to (2k)
The recording code string “01” corresponding to this state transition
Since “00” includes an isolated bit having the minimum magnetization reversal, in the present invention, this state transition takes into account the PE phenomenon, and as shown in FIG.
Is treated as appearing as “α, 0, −α”. As a result, if there is no noise, the equalization response signal input to the ACS circuit 7 is “0” at time (2k−1) and “−” at time (2k), as shown in FIG. (1 + α) ”. The branch metric B (S1-S0) in this case is given by the following equation. B ((S1-S0) 2k) = (y (2k-1) -0) ² + (y (2k) + (1 + α)) ² + P (S1 (2k-2)) = y (2k-1) ² + Y (2k) ² +2 (1 + α) y (2k) + (1 + α) ² + P (S1 (2k-2)) (Equation 3) where P (S1 (2k-2)) is State S at time 2k-2
1 indicates the value of the path metric. y (2k-1) ² and y (2k) ²
Is a common term in all branch metrics, and can be excluded in advance. Further, the numerical value of the calculation result is normalized by multiplying the coefficient by 1/4 in any branch metric. By such operation,
The formula (Equation 3) is as follows: B ((S1−S0) 2k) = 1/2 · (1 + α) y (2k) + 1/4 · (1 + α) ² + P (S1 (2k−2)) (Equation 4) If the PE phenomenon is not considered, α = 1
And the value of B ((S1-S0) 2k) is B ((S1-S0) 2k) =
y (2k) + 1 + P (S1 (2k-2)). Here, α = 1−
When β is replaced, the equation (Equation 4) is transformed into B ((S1-S
0) 2k) ≒ y (2k) + 1-1 / 2 · βy (2k) + P (S1 (2k-2))
(Equation 5)

From the above, the branch metric operation circuit 71-1 uses only y (2k) of the two inputs y (2k-1) and y (2k) to calculate the equation (5). "Y (2
k) + 1-1 / 2 · βy (2k) ”. The output of the arithmetic circuit is input to the adder 72-1 and added to the value of the path metric P (S1 (2k-2)) given by the register 75 from the register 75. By the above addition, the value of the branch metric B ((S1-S0) 2k) is output from the addition circuit 72-1 and the above-mentioned B ((S0-S
0) As in 2k), the signals are input to the 4-input comparator 73 and the selection circuit 74.

(3) Function of arithmetic circuit 71-2 (state S2
From the state S3 to S0) and the function of the arithmetic circuit 71-3 (transition from the state S3 to S0): In the branch metrics arithmetic circuits 71-2 and 72-3, the arithmetic expression 50- in the table 50 shown in FIG. The arithmetic operation corresponding to 2, 50-3 may be performed (the arithmetic expression 50-0 in the table 50,
Reference numeral 50-1 denotes execution contents of the branch metric calculation circuits 71-0 and 72-1. These operation results are added to adders 72-2 and 72-3, respectively.
To the branch metrics B ((S2
-S0) 2k) and B ((S3-S0) 2k) are obtained.

Returning to FIG. 6, the comparator 73 includes an adder 72
From among the four branch metrics B ((S0-S0) 2k) to B ((S3-S0) 2k) output from -0 to 72-3, the branch metric B ((S3-S0) 2k) is determined to have the smallest value, and is most likely to be the previous state. Control signal V7-0 indicating the high state value Sj. Selection circuit 74
Are the four branch metrics B ((S0-S0) 2k) -B
From ((S3-S0) 2k), one branch metric corresponding to the value (state value Sj) of the control signal V7-0 is selected, and the path metric P of the state S0 in the next calculation is selected.
(S0 (2k)) as the value S0 'to be used as the register 75
In the S0 storage area. The value S0 'is different from other ACS
Also supplied to the arithmetic units 70-1 to 70-3,
The operation unit 70-1 itself, another ACS operation unit 7
New values S1 'to S3' are obtained from 0-1 to 70-3 and stored in the corresponding storage area of the register 75. The new branch metric values B ((S0-S0) 2k) to B ((S3-S0) 2k) set in the register 75 are calculated at the next operation time 2k.
At +2, the values of the path metrics in the states S0 to S3 are input to the adders 72-0 to 72-3.

Other ACS operation units 70-1 to 70-
3 also has four branch metrics operation circuits 71-0 to 71-0 similarly to the ACS operation unit 70-0 shown in FIG.
71-3, adders 72-0 to 72-3, and register 7
5 to calculate four branch metrics values from the output of each arithmetic circuit and the output value of the register 75.

Tables 51 to 52 shown in FIGS.
Indicates arithmetic expressions to be performed by the four branch metric arithmetic circuits of the ACS arithmetic units 70-1 to 70-3, respectively. As is apparent from these tables, A
In the CS calculation unit 70-1, the second and fourth branch metric calculation circuits 71-1 and 71-3 executing the calculation expressions 51-1 and 51-3 including the parameter β have P
It can be seen that the maximum likelihood decoding process is performed in consideration of the E phenomenon. Similarly, the AC that executes the arithmetic expressions 52-0 and 52-2
First and third branch metrics operation circuits 71-0 and 71-2 in S operation unit 70-2, and operation expression 5
3-2 in the ACS operation unit 70-3 for executing 3-2
It can be seen that also in the branch metric calculation circuit 71-2, the maximum likelihood decoding process taking into account the PE phenomenon is performed.

Returning to FIG. 5, the path memories (shift registers) 80-0 to 80-3 are mutually connected by a transfer path, so that the contents of the shift registers can be updated between the respective path memories. I have. For example, the comparator 73 of the ACS operation unit 70-0 switches from the state S1 to the state S1.
Select the transition to 0, ie, branch metrics B
Assuming that the value of ((S1-S0) 2k) is selected, the current state S
1 is stored in the path memory 80-1.
0-0, and similarly, the control signals V7-1 to V7-3
After the contents of the path memories 80-1 to 80-3 are updated according to the above, a state value unique to each ACS operation unit is set in the first stage of the shift register. in this way,
Since the update of the path memory is repeated every two samples,
Each path memory 80 stores an identification signal sequence having a small metric. If each path memory 80 has a predetermined memory length, that is, a shift register length,
Output values V8-0 to V8- from the last stage of the shift register
3 often has the same value in each path memory. However, the sample value y given as the equalized output V11
If (2k) and y (2k-1) contain much noise,
The outputs of these shift registers do not always have the same value. Therefore, the output of each shift register is input to the majority logic circuit 9, and the value selected by the majority logic is output as the final identification result V10.

As described above, in the PR4ML type magnetic recording signal reproducing apparatus, the PR4 equalized signal is supplied to the maximum likelihood decoding circuit by two.
Although the embodiment in which the samples are supplied and the state transition is determined in a two-sample cycle has been described, as a modification of the above-described embodiment, the number of samples simultaneously supplied to the maximum likelihood decoding processing circuit is two.
It is good also as above. In the above embodiment, α = 1
If (β = 0), the conventional PR4ML signal processing can be realized. Therefore, as shown in FIG.
If a parameter register 76 is provided so that the value of the parameter α (or β) can be switched or changed according to an external instruction, the signal reproducing circuit having the same structure can change the recording density from low-density recording to high-density recording. It is possible to support a wide range of recording densities. When a signal reproducing apparatus dedicated to high-density recording is configured, the parameter register 76 may be omitted, and arithmetic operation may be performed using a fixed α or β in each branch metrics arithmetic circuit. The maximum likelihood decoding method taking the above-mentioned PE phenomenon into consideration is PR
4 other than the partial response method, for example, EPR4
ML (Extended Partial Response class 4Maximum Lik
elihood). The EPR4ML is a system in which a digital filter 11 equalizes a reproduction response signal to a recording signal "1" so that a response of an equalized output becomes "1,1, -1, -1". While the number of states handled by the maximum likelihood decoding processing circuit 7 was 4 in PR4,
In PR4, three bits of samples are required to determine the code value, so the number of states handled is eight. FIG.
9 shows state transitions every two samples in PR4ML. As apparent from the code sequence, there are four combinations (four inputs) of code sequence combinations that transition from the previous state to the current state.

FIGS. 15 and 16 show the relationship between the recording code string and the equalized output when the PE phenomenon is considered in EPR4ML. FIG. 15 shows that, when the recording code string is “010”, a code “10” of two new samples at time (2k−1) and (2k) is given, and the code string of the latest 3 bits is the original. This is an example of the same “010” state. In this example, as can be seen from the code strings and the magnetization patterns shown in (A) and (B) of the figure, since the magnetization is inverted at one-bit intervals, the PE phenomenon occurs at bit “1”, and two In the bit “0” sandwiched between the bits “1”, it is considered that a stronger PE phenomenon occurs due to the influence of the PE phenomenon before and after. In this case, in the maximum likelihood decoding processing circuit, FIG.
, The equalization response of the two bits “1” is “α, α, −α, −α”, and the bit “0” between them is “−α ² , −α ² , α ² , α ² ", and is treated as if the PE phenomenon was strongly reflected in the value of the equalized output as shown in FIG.

FIG. 16 shows that when the recording code string is "000", a code "10" of two new samples at time (2k-1) and (2k) is given, and the code string of the latest 3 bits is given. Is "01
This is an example in which the state has changed to “0”. In this case, since the bit “1” is an isolated bit, the likelihood calculation of the likelihood calculation is performed so that the equalization response to this bit becomes “α, α, −α, −α” as shown in FIG. Set the parameter value.

As is clear from the above description, in each embodiment of the present invention, equalized outputs for a plurality of samples are supplied to the maximum likelihood decoding processing circuit, and the branch metric calculation performed by the maximum likelihood decoding processing circuit is performed. Applying a special operation parameter in consideration of the amplitude deterioration of the equalization response in the above, specifically, the reproduction output of the pulse having the shortest magnetization reversal width is different from the pulse output having other magnetization reversal widths. It is characterized in that likelihood determination is performed by an arithmetic expression using parameter values. However, the invention is not limited to the scope of the embodiments described above. For example, in a recording medium such as a magnetic disk in which the recording density changes according to the radius of gyration, the parameters of the branch metric calculation performed by the maximum likelihood decoding processing circuit are changed according to the position of the reproducing head on the storage medium, and stored. An embodiment in which the nonlinearity of the reproduction response that differs depending on the recording position on the medium is eliminated is also one of the present inventions. Further, by integrating the equalization decoding circuit 10 shown in FIG. 1 on the same semiconductor substrate as an integrated circuit and supplying it as one IC chip, it is possible to easily assemble a digital recording signal reproducing apparatus.
The clock extraction circuit 5 in FIG. 1 may be integrated on the same semiconductor substrate as the equalization decoding circuit 10. In this case, the A / D converter 4 may be integrated on the same semiconductor substrate.

[0033]

As is apparent from the above description, according to the present invention, as in the partial erasure phenomenon, the non-linearity of the reproduced signal amplitude which appears in relation to the preceding and following bit values in the recording code string during high-density recording. , And high-density recording becomes possible.
Also, high-speed signal reproduction can be performed by the maximum likelihood decoding process for each of a plurality of samples.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a reproducing system of a digital recording signal reproducing apparatus to which the present invention is applied.

FIG. 2 is a diagram showing a circuit configuration of a decision feedback equalizer in a conventional reproducing apparatus.

FIG. 3 is a diagram showing an equalized waveform by a feedforward filter 20 of the decision feedback equalizer.

FIG. 4 is a diagram for explaining a relationship between a recording signal sequence and an equalized output in a partial response class 4.

FIG. 5 is a diagram showing an embodiment of an ACS circuit 7 and a trace-back RAM 8 in the digital recording signal reproducing device of the present invention.

FIG. 6 is a diagram showing one embodiment of an ACS operation unit 70 in FIG. 5;

FIG. 7 is a diagram showing a state transition of an input signal of the ACS operation unit 70 according to the present invention.

FIG. 8 is a diagram showing a relationship between a recording signal sequence without a PE phenomenon and an equalized output.

FIG. 9 is a diagram showing a relationship between a recording signal sequence accompanied by a PE phenomenon and an equalized output.

FIG. 10 is a diagram illustrating a function (arithmetic expression) of a branch metrics arithmetic circuit in an ACS arithmetic unit 70-0 that calculates a transition likelihood to a state S0.

FIG. 11 is a diagram showing a function (arithmetic expression) of a branch metrics arithmetic circuit in the ACS arithmetic unit 70-1 for calculating the transition likelihood to the state S1.

FIG. 12 is a diagram showing a function (arithmetic expression) of a branch metric arithmetic circuit in an ACS arithmetic unit 70-2 for calculating a transition likelihood to a state S2.

FIG. 13 is a diagram showing a function (arithmetic expression) of a branch metrics arithmetic circuit in the ACS arithmetic unit 70-3 for calculating the transition likelihood to the state S3.

FIG. 14 is a diagram showing a state transition of an input signal of an ACS operation unit in an EPR4ML signal reproducing apparatus to which the present invention is applied.

FIG. 15 is a diagram illustrating an example of a relationship between a recording signal sequence in EPR4 equalization and an equalized output in consideration of a PE phenomenon.

FIG. 16 is a diagram showing another example of the relationship between a recording signal sequence in EPR4 equalization and an equalized output when the PE phenomenon is considered.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Reproduction head, 2 ... Preamplifier, 3 ... Low-pass filter, 4 ... A / D converter, 10 ... Equalization decoding processing circuit, 11
... Digital filter for PR4, 12 ... 1 sample delay circuit, 13 ... Maximum likelihood decoding processing circuit, 7 ... ACS circuit, 8 ...
RAM for traceback, 9 ... majority logic circuit, 70 ...
ACS operation unit, 71: branch metrics operation circuit, 72: adder, 73: comparator, 74: selection circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI G11B 20/18 570 G11B 20/18 570F 572 572B

Claims (7)

(57) [Claims] A magnetic disk and a recording medium from the magnetic disk.
A read head for reading a recording signal;
Analog-to-digital converter that samples at
Equalize the waveform of the output signal from the analog-to-digital converter.
The equalizing means to be performed and the output signal of the equalizing means
A delay circuit that delays by a time corresponding to
In parallel with the output signal of the equalizing means.
Maximum likelihood decoding processing means to be inputted;
Processing means corresponding to the equalized output signal input in parallel.
The isolated bit in the recording signal from the rotating magnetic disk.
Therefore, the output response of the equalizing means is set according to the recording density.
Using the calculated operation parameter α (0 <α <1)
The conventional recording code is assumed to be in the range of [α, 0, -α].
The likelihood of the state transition from the
A magnetic disk recording and reproducing apparatus. 2. The maximum likelihood decoding processing means determines likelihood in a state transition including an isolated bit having the shortest magnetization reversal width in the subsequent recording code string, and determines a continuous bit having a larger magnetization reversal width than this. 2. The magnetic disk recording / reproducing apparatus according to claim 1, wherein the likelihood determination in the state transition includes a calculation with a different calculation parameter α. 3. The magnetic disk recording / reproducing apparatus according to claim 1, wherein said maximum likelihood decoding processing means is respectively associated with different predetermined states which can be taken by said subsequent recording code string, and said maximum likelihood decoding processing means Based on the input equalized output signal, calculate the likelihood of a state transition from a plurality of states that can be taken by the previous recording code string to the predetermined state, and specify the state of the previous recording code string A plurality of arithmetic units,
A plurality of storage means for storing a recording code string output from each of the arithmetic units; and a selection for selecting a digital recording code to be output as an identification result from the recording codes output from the plurality of storage means. Means for calculating the likelihood of a state transition by applying an operation parameter on the assumption of amplitude degradation of an equalization response for a state transition with respect to an isolated bit. A magnetic disk recording / reproducing apparatus characterized by the above-mentioned. 4. The magnetic disk recording / reproducing apparatus according to claim 1, wherein the corresponding storage means stores the storage contents of another storage means according to the state of the previous recording code string specified by the arithmetic unit. A magnetic disk recording / reproducing apparatus characterized in that the predetermined state value is added after capturing. 5. The magnetic disk recording / reproducing apparatus according to claim 1, wherein each of the arithmetic units is associated with a different predetermined state that can be taken by a previous recording code string, and is input in parallel. A plurality of calculating means for calculating a likelihood of a state transition from one state of the previous recording code string to the predetermined state based on the equalized output signal and the previously stored likelihood value previously stored; 2. The magnetic disk recording / reproducing apparatus according to claim 1, further comprising means for comparing the calculation results of the plurality of calculation means to specify the state of the previous recording code string. Wherein said maximum likelihood decoding means, a magnetic disk recording and reproducing apparatus according to any one of claims 1 to 5, characterized in that it comprises means for changing the value of said operational parameter α . 7. A reproduction signal from a magnetic recording medium on which a digital signal is recorded is sampled at a bit cycle of the digital signal, and the sampled signal is converted to a PRML4 signal.
Alternatively, the PRML4 or EPRML4 equalized signal is delayed by one sample time by the EPRML4 signal, and the PRML4 delayed by the one sample time is used.
Alternatively, an equalized output signal for a plurality of samples is generated using the equalized signal of the EPRML4 system, the state transition likelihood is determined for the equalized signal for the plurality of samples, and an isolated bit is added to the equalized signal for the plurality of samples. Is included, the PR
Calculation parameter α (0 <α <1) for which the output of the ML4 or EPRML4 equalized signal is set according to the recording density
A digital recording signal reproducing method characterized in that the state transition likelihood is determined as being in the range of [α, 0, −α] using