JP3300238B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a semiconductor device in which a DMOSFET and a bipolar transistor are integrated on the same semiconductor substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Recently, a DMOSFET (Double Diffused), which is a device for driving various devices, has been developed.
Many proposals have been made regarding semiconductor devices in which a MOSFET is integrated with other devices.

A conventional method of manufacturing a DMOSFET disclosed in Japanese Patent Application Laid-Open No. 3-205832 will be described below with reference to FIGS.

First, as shown in FIG. 12A, an insulating gate 40 made of, for example, polycrystalline silicon or the like deposited on a surface of an N-type semiconductor substrate 39 serving as a drain region via a silicon oxide film is formed. I do.

Next, as shown in FIG. 12B, for example, boron ions are implanted by using the insulating gate 40 as a part of the mask, and a region in the semiconductor substrate 39 located on one side of the insulating gate 40 is formed. A p-type body layer 41 is formed.

Next, as shown in FIG. 12C, for example, arsenic ions are implanted by using the insulating gate 40 as a part of the mask, and a region in the semiconductor substrate 29 located on one side of the insulating gate 40 is formed. A drain contact layer 43 in a region of the semiconductor substrate 39 located on the other side of the insulated gate electrode 40 and separated from the insulated gate electrode 40, respectively. Form.

[0007] The formation of each semiconductor layer is completed by the above manufacturing steps, and thereafter, an electrode connected to each semiconductor layer via an interlayer insulating film is formed to complete a semiconductor element.

[0008]

The above-mentioned conventional DMOSF
The ET has a high drain withstand voltage since the drain contact layer is formed at a position distant from the gate electrode, and has a high durability required for a driving device. On the other hand, DM
The on-resistance, which is the resistance between the source and the drain when the OSFET is conducting, must be high. This is because a desired drain withstand voltage cannot be obtained if the impurity concentration of the drain layer is increased. On the other hand, when a large number of layers are provided in a semiconductor substrate, the number of manufacturing steps is increased, so that there is a problem that manufacturing costs are increased and practical value is lost.

The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device having a DMOSFET and a bipolar transistor and a method of manufacturing the same.
It is an object of the present invention to reduce the manufacturing cost and improve the characteristics of the semiconductor device by taking measures to reduce the ON resistance of the DMOSFET without increasing the number of manufacturing steps.

[0010]

Means for Solving the Problems] semi conductor arrangement of the onset Ming,
The semiconductor device equipped with at least one DMOSFET and a bipolar transistor on a semi-conductor substrate assumes,
The DMOSFET includes a gate electrode formed on the semiconductor substrate via a gate insulating film, and a low-concentration first conductivity type impurity formed at least in a region in the semiconductor substrate including a region below the gate electrode. A drain layer including a high concentration first conductivity type impurity formed in a region in the semiconductor substrate located on one side of the gate electrode; and a gate in a region surrounded by the drain region. A drain offset layer which is located on the other side of the electrode and is separated from the gate electrode and contains a first conductivity type impurity having a higher concentration than the drain layer; and a region surrounded by the drain offset layer. A drain contact layer formed and containing a first conductivity type impurity at a higher concentration than the drain offset layer; and a surface of the semiconductor substrate surrounding the source layer. A second conductivity type impurity having a threshold control level formed so as to reach a part of a region below the gate electrode in a near region and to be separated from the drain contact layer by a predetermined distance with the drain layer interposed therebetween; Wherein the bipolar transistor comprises:
A collector layer containing the second conductivity type impurity, a base layer formed in a region surrounded by the collector layer and containing the first conductivity type impurity, and an emitter formed in a region surrounded by the base layer and containing the second conductivity type impurity And the above DM
The drain offset layer of the OSFET and the base layer of the bipolar transistor contain simultaneously introduced first conductivity type impurities, and the diffusion depth of the impurity is the same as that of the DMOSFET.
It is deeper than the diffusion depth of the source layer .

As a result, the drain offset layer of the DMOSFET has the same conductivity type as the drain layer and contains an impurity having a higher concentration than the drain layer. Therefore, the resistance between the drain contact layer and the source layer, that is, the on-resistance is reduced. In addition, since the drain offset layer of the DMOSFET contains impurities introduced simultaneously with the base layer of the bipolar transistor, there is no need to provide a separate step for forming the drain offset layer at the time of manufacturing. A forming step can be used. That is, manufacturing costs can be reduced.

The concentration of the first conductivity type impurity in the drain layer of the DMOSFET is 5 × 10 ^{14 to} 5 × 10 ¹⁶ c.
m- ³ is preferred.

[0013] the production method of the present onset Ming semiconductors devices, D MO
A first step of forming a semiconductor substrate having an SFET formation region and a bipolar transistor formation region;
A second step of forming a drain layer of the DMOSFET by introducing a first conductivity type impurity into an OSFET formation region;
A third step of introducing a second conductivity type impurity into the bipolar transistor formation region to form a collector layer of the bipolar transistor, and a region surrounded by the drain layer of the DMOSFET and the collector layer of the bipolar transistor. And the region to be doped is doped with a first conductivity type impurity, and then heat-treated.
A fourth step of simultaneously forming the base layer of the drain offset layer and the bipolar transistor, the fourth
After the step, the semiconductor substrate is oxidized to form the DMOS
A gate insulating film is formed in the FET formation region, and then the gate insulating film is formed.
Separated from the drain offset layer on the gate insulating film
A fifth step of forming a gate electrode on the region, located on one side of the gate electrode and by introducing a second conductivity type impurity in a region surrounded by the drain layer, the gate insulating
A sixth step of forming a body layer of the DMOSFET reaching a part of a lower region of the film ;
A seventh step of forming a first conductivity type drain contact layer and a first conductivity type source layer surrounded by the body layer in a region surrounded by the drain offset layer in the formation region; and forming the bipolar transistor. eighth and Bei example a step of forming an emitter layer of the second conductivity type surrounded by the base layer in the region of the DMOSFET de
The rain offset layer and the bipolar transistor
The source layer is higher than the drain layer of the DMOSFET.
Impurity with a lower concentration than the drain contact layer
And the diffusion depth is the source layer of the DMOSFET.
Deeper than the diffusion depth .

According to this method, DMOSF can be performed in a common process.
A drain offset layer of the ET and a base layer of the bipolar transistor are formed. Since the drain offset layer for reducing the ON resistance of the DMOSFET is formed at the same time as the formation of the base layer which is indispensable when forming the bipolar transistor, it is not necessary to separately provide a step of forming the drain offset layer. . Therefore, the number of steps can be reduced, and the cost required for manufacturing can be reduced. Moreover, this method does not affect the characteristics of the bipolar transistor.

The concentration of the first conductivity type impurity in the drain layer of the DMOSFET is 5 × 10 ^{14 to} 5 × 10 ¹⁶ c.
m- ³ is preferred.

[0016]

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment will be described. 1 to 4
FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

In the step shown in FIG. 1, first, a P-type semiconductor substrate 1 made of silicon single crystal having a (100) plane as a main surface and having a specific resistance of, for example, 10 to 20 Ω · cm is prepared. The main surface of the semiconductor substrate 1 has a DMOSFET formation region Rdm
os and a PNP bipolar transistor formation region Rbpnp are provided. Here, for example, a resist mask (not shown) is formed on the semiconductor substrate 1 and is used to
DMOSFET formation region Rdmos, PN of semiconductor substrate 1
For example, phosphorus ions are implanted into the P bipolar transistor formation region Rbpnp at an energy of 150 keV and a dose of 5 keV.
Implantation is performed under conditions of about × 10 ¹² cm ⁻² and heat treatment is performed. Further, another resist mask (not shown) is formed, and P
For example, boron ions are implanted into the NP bipolar transistor formation region Rbpnp under the conditions that the implantation energy is about 40 keV and the dose is about 1 × 10 ¹³ cm ⁻² , and then heat treatment is performed.

Thus, the N- type drain layer 2 of the DMOSFET, the separation layer 3 and the collector layer 4 of the PNP bipolar transistor are formed.

[0021] Next, in the as shown be Engineering 2, for example, using the resist film 5 as a mask, DMOSFET forming region R
For example, phosphorus ions are implanted into a region surrounded by the drain layer 2 of dmos and a region surrounded by the collector layer 4 of the bipolar transistor formation region Rbpnp at an energy of 120 keV and
After the implantation under the condition that the dose is about 1.5 × 10 ¹³ cm ⁻² , heat treatment is performed.

Thus, a drain offset layer 6 is formed in a region surrounded by the drain layer 2 of the DMOSFET, and an intrinsic base layer 7 is formed in a region surrounded by the collector layer 4 of the bipolar transistor.

Next, in the step shown in FIG.
Oxidized at a temperature of 15 ° C. to a thickness of 15 nm on the semiconductor substrate 1.
After forming a silicon oxide film of a degree, further depositing a polycrystalline silicon film on the silicon oxide film, patterning the polycrystalline silicon film and the silicon oxide film,
An ET gate oxide film 8 and a polycrystalline silicon gate electrode 9 are formed. Further, for example, a resist film 10 having an opening in a region where a body layer of a DMOSFET is to be formed is formed. Using the resist film 10 and the polycrystalline silicon gate electrode 9 as a mask, a boron ion Injection energy is 140 ke
After implanting under conditions of V and a dose amount of about 5 × 10 ¹³ cm ⁻² , a heat treatment is performed.

Thus, a P-type body layer 11 is formed in a region surrounded by the drain layer 2 of the DMOSFET.

Next, in the step shown in FIG. 4, a region surrounded by the body layer 11 of the DMOSFET and a region surrounded by the drain offset layer 6 are formed by using a resist film (not shown) and the polycrystalline silicon gate 9 as a mask. to, for example, implantation energy of arsenic ions 40 keV, a dose amount is injected under the condition of about 1 × 10 ¹⁶ cm ^-2, further using another resist film (not shown) as a mask, the intrinsic base layer of the bipolar transistor in a region surrounded by 7, for example, a BF2 ion implantation energy is 40 keV, after the dose was injected at about 3 × 10 ¹⁵ cm ^-2 conditions, heat treatment is performed.

Thus, the body layer 1 of the DMOSFET
In the region surrounded by 1, the source layer 12 is a DMOSFET.
A drain contact layer 13 is formed in a region surrounded by the drain offset layer 6, and an emitter layer 14 is formed in a region surrounded by the intrinsic base layer 7 of the bipolar transistor.

Further, although not described in the drawings of the present embodiment, thereafter, for example, low-pressure CVD is performed as an interlayer insulating film.
Forming an NSG film with a thickness of about 800 nm
Thereafter, the NSG film is etched by dry etching using, for example, a resist film as a mask to form a contact hole. Finally, an Al film is formed by a sputtering method, for example, as a metal wiring, and thereafter, the Al film is etched using, for example, a resist film as a mask to form an Al wiring, whereby the semiconductor device is completed.

DMOSFE in the semiconductor device of this embodiment
According to T, the drain offset layer 6 containing an intermediate concentration of N-type impurities is formed between the drain contact layer 13 containing high-concentration N-type impurities and the drain layer 2 containing low-concentration N-type impurities. Therefore, the drain resistance can be reduced and the drain withstand voltage can be kept high.

In addition, in the manufacturing process of this embodiment, the drain offset layer 6 for reducing the ON resistance of the DMOSFET is formed simultaneously with the formation of the intrinsic base layer 7 which is inevitably required when forming the bipolar transistor. Therefore, there is no need to separately provide a step for forming the drain offset layer 6. By adopting such a structure, the characteristics of the PNP bipolar transistor are not affected. Therefore, it is possible to obtain a semiconductor device on which a DMOSFET and a bipolar transistor having good characteristics with low on-resistance are mounted at low cost.

In this embodiment, the DMOSF
The drain offset layer 6 of the ET is not in contact with the insulated gate composed of the polysilicon gate electrode 9 and the gate oxide film 8, but this is due to the required breakdown voltage and may be in contact. In this case, the drain contact layer 13 of the DMOSFET may be formed in a self-aligned manner with respect to the insulated gate similarly to the source layer 12.

Second Embodiment Next, a second embodiment will be described. 5 to 6
FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment.

In this embodiment, first, the same process as that shown in FIG. 1 in the first embodiment is performed, and the DMOSFET formation region Rdmos of the P-type semiconductor substrate 1 is provided with a DM.
An N- type drain layer 2 of the OSFET is formed, and an isolation layer 3 and a collector layer 4 of the PNP bipolar transistor are formed in a PNP bipolar transistor formation region Rbpnp.

Thereafter, in the step shown in FIG.
Oxidized at a temperature of 15 ° C. to a thickness of 15 nm on the semiconductor substrate 1.
After forming a silicon oxide film of a degree, further depositing a polycrystalline silicon film on the silicon oxide film, patterning the polycrystalline silicon film and the silicon oxide film,
An ET gate oxide film 8 and a polycrystalline silicon gate electrode 9 are formed.

Next, as shown in FIG. 6, using the resist film 17 and the polysilicon gate electrode 9 as a mask, for example, a region surrounded by the drain layer 2 of the DMOSFET formation region Rdmos and a PNP bipolar transistor formation region Rbpnp are formed. For example, phosphorus ions are implanted into a region surrounded by the collector layer 4 at an energy of 120 keV and a dose of 1.5.
After the implantation under the condition of about × 10 ¹³ cm ⁻² , a heat treatment is performed.

Thus, a drain offset layer 6 is formed in a region surrounded by the drain layer 2 of the DMOSFET, and an intrinsic base layer 7 is formed in a region surrounded by the collector layer 4 of the bipolar transistor.

Thereafter, through the same steps as in the first embodiment described above, the body layer, source layer, drain contact layer and the emitter layer of the bipolar transistor of the DMOSFET are formed, and the semiconductor device shown in FIG. A semiconductor device having the same structure as described above is obtained.

According to the present embodiment, basically, the first
The same effect as that of the embodiment can be obtained.

In addition, in this embodiment, the DMOSFET
In forming the drain offset layer 6 of FIG. 1, the already formed polycrystalline silicon gate electrode 9 can be used as a part of the mask. Therefore, the drain offset layer 6 can be formed in a self-aligned manner with respect to the polycrystalline silicon gate electrode 9, and a DMOSFET with a small ON resistance variation and stable characteristics can be formed. In addition, this method does not affect the characteristics of the bipolar transistor, and does not increase the manufacturing cost.

In this embodiment, the DMOSF
After the formation of the drain offset layer 6 of ET, the DMOSFE
Although the body layer (not shown) of T is formed, the body layer of DMOSFET may be formed first.

In this embodiment, the DMOSF
Similarly to the source layer (not shown), the drain contact layer (not shown) of the ET may be formed by self-alignment with respect to the polysilicon gate electrode 9.

Third Embodiment Next, a third embodiment will be described. 7 to 11
FIG. 9 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the third embodiment.

First, in the step shown in FIG. 7, a P-type semiconductor substrate 20 made of a silicon single crystal having a (100) plane as a main surface and having a specific resistance of, for example, 10 to 20 Ω · cm is prepared. The main surface of the semiconductor substrate 20 has a DMOSFET formation region Rdmos and an NPN bipolar transistor formation region Rbnpn
Are provided. Here, for example, a resist mask (not shown) is formed on the semiconductor substrate 20 and is used to form a DMOSFET formation region Rdm of the P-type semiconductor substrate 20.
os, in the NPN bipolar transistor formation region Rbnpn,
For example, arsenic ions are implanted under the conditions that the implantation energy is about 40 keV and the dose is about 5 × 10 ¹⁴ cm ⁻² , and heat treatment is performed to form the buried collector layer 21 of the bipolar transistor and the buried drain layer 22 of the DMOSFET.

Next, as shown in FIG. 8, an N-type epitaxial layer 23 having, for example, a specific resistance of 1 Ω · cm and a thickness of about 2 μm is formed. Next, using a resist mask (not shown), for example, boron ions are implanted under the conditions of an implantation energy of 150 keV and a dose of about 2 × 10 ¹² cm ⁻² , and a heat treatment is performed, thereby performing element isolation. Is formed. The region in the N-type epitaxial layer 23 partitioned by the formation of the separation layer 24 is a DMO
It becomes the drain layer 25 of the SFET and the collector layer 26 of the bipolar transistor.

Next, in the step shown in FIG.
9 is used as a mask, for example, phosphorus ions are implanted under the conditions of an implantation energy of 80 keV and a dose of about 3 × 10 ¹⁵ cm ⁻² , and a heat treatment is performed to thereby form the collector wall layer 27 of the NPN bipolar transistor and the DMOS.
A drain offset layer 28 of the FET is formed.

Next, in the step shown in FIG. 10, for example, boron ions are implanted into a region surrounded by the collector layer 26 of the NPN bipolar transistor forming region Rbnpn at an implantation energy of 30 keV and a dose of about 1.5 × 10 ¹³ cm ^−2. And heat treatment is performed to form an intrinsic base layer 29 in a region surrounded by the collector layer 26 of the NPN bipolar transistor. Next, oxidation is performed at, for example, 900 ° C., a silicon oxide film having a thickness of about 15 nm is formed on the semiconductor substrate 20, and a polycrystalline silicon film is further deposited thereon. Is patterned to form a gate oxide film 30 and a polycrystalline silicon gate electrode 31 of the DMOSFET. Further, for example, using a resist film 32 having an opening in the body formation region of the DMOSFET and the polycrystalline silicon gate electrode 31 as a mask, a region surrounded by the drain layer 25 of the DMOSFET is implanted with, for example, boron ions at an implantation energy of 140 keV and a dose of 5 Implantation is performed under conditions of about × 10 ¹³ cm ⁻² and heat treatment is performed. As a result, DMOSFE
A body layer 33 of T is formed.

Next, in the step shown in FIG. 11, using the resist film 34 and the polysilicon gate electrode 31 as a mask, a region surrounded by the body layer 33 of the DMOSFET and a region surrounded by the drain offset layer 28 of the DMOSFET are used. In the region surrounded by the intrinsic base layer 29 of the NPN bipolar transistor and the region surrounded by the collector wall layer 27 of the NPN bipolar transistor, for example, arsenic ions are implanted at an energy of 40 keV and a dose of about 1 × 10 ¹⁶ cm ⁻² . Inject under conditions and perform heat treatment.

Thus, the body layer 3 of the DMOSFET
The source layer 35 is formed in a region surrounded by
A drain contact layer 36 is formed in a region surrounded by the drain offset layer 28, and an emitter layer 37 is formed in a region surrounded by the intrinsic base layer 29 of the NPN bipolar transistor.
However, a collector contact layer 38 is formed in a region surrounded by the collector wall layer 27 of the NPN bipolar transistor.

Although not shown in the drawings of the present embodiment, thereafter, a region surrounded by the body layer 25 of the DMOSFET (not shown) and a region surrounded by the intrinsic base layer 29 of the NPN bipolar transistor (see FIG. (Not shown)
For example, BF2 ion is 40 keV and the dose is 3 × 10
After the implantation under the condition of about ¹⁵ cm ^-2 , heat treatment is performed. Thereby, although not shown, the body layer 25 of the DMOSFET is formed.
A body contact layer is formed in a region surrounded by, and a base contact layer is formed in a region surrounded by the intrinsic base layer 29 of the bipolar transistor.

Further, although not shown in the drawings of this embodiment, an NSG film is formed as an interlayer insulating film to a thickness of about 800 nm by using, for example, a low pressure CVD method, and thereafter, for example, using a resist film as a mask, the NSG film is formed. The film is etched by dry etching to form a contact hole. Finally, an Al film is formed by a sputtering method, for example, as a metal wiring, and thereafter, the Al film is etched using, for example, a resist film as a mask to form an Al wiring, whereby the semiconductor device is completed.

According to the present embodiment, a DMOSFET having a high drain withstand voltage and a low drain resistance can be obtained as in the first embodiment. In addition, in this embodiment, the buried collector layer 21 is provided in the NPN bipolar transistor, and the collector wall layer 27 is in contact with the buried collector layer 21, so that a vertical bipolar transistor having good operation characteristics can be obtained. Then, simultaneously with the formation of the collector wall layer 27 necessary for forming the NPN bipolar transistor, the DMO
Since the drain offset layer 28 for reducing the on-resistance of the SFET is formed, it is not necessary to separately provide a step for forming the drain offset layer, and the manufacturing cost can be reduced by reducing the number of steps. Moreover,
This method does not affect the characteristics of the bipolar transistor.

In this embodiment, the DMOSF
The drain offset layer 28 of the ET is not in contact with the polycrystalline silicon gate electrode 31, but this is due to the required breakdown voltage and may be in contact. In that case, DMO
The drain contact layer 36 of the SFET is also
Similarly to the above, the polysilicon gate electrode 31 may be formed in a self-aligned manner.

In this embodiment, the drain contact layer 36 and the collector contact layer 38 are formed, but these may not be formed.

In this embodiment, the DMOSF
Although the buried drain layer 22 of ET is formed, this may not be necessary.

Further, in this embodiment, the DMOS
Although the body contact layer of the FET and the base contact layer of the bipolar transistor are formed, these may not be provided.

In this embodiment, the insulating gate composed of the gate oxide film and the gate electrode is formed after the formation of the intrinsic base layer 29 of the bipolar transistor. However, the insulating gate may be formed first.

In this embodiment, the separation layer 24
After formation of the collector wall layer 27 of the bipolar transistor and the drain offset layer 28 of the DMOSFET
Was formed, the collector wall layer 27 of the bipolar transistor and the drain offset layer 28 of the DMOSFET may be formed first.

Here, a specific preferred range of the impurity concentration of each layer in each of the above embodiments will be described.

In the DMOSFET, the N− type drain layer has an impurity concentration of about 5 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻³ , and the N− type drain offset layer has an impurity concentration of about 1 × 10 ¹⁶ to 1 × 10 ²⁰ cm ^−3. It is preferable that the N + -type drain contact layer has an impurity at a concentration higher than that in the drain contact layer.

In a PNP bipolar transistor,
The collector layer preferably has an impurity concentration of about 5 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻³ , and the intrinsic base layer preferably has an impurity concentration of about 1 × 10 ¹⁶ to 1 × 10 ²⁰ cm ⁻³ .

In an NPN bipolar transistor,
The collector layer in the N-type epitaxial layer is 5 × 10 ^{14 to} 5
About × 10 ¹⁶ cm ^-3 , the collector wall layer is 1 × 10
It is preferable that each impurity has a concentration of about ¹⁶ to 1 × 10 ²⁰ cm ⁻³ .

The effects of the above embodiments can be effectively exhibited by having the impurities in the above-described ranges.

(Other Embodiments) In the first and second embodiments, the DMOSFET
Of these, an N-channel DMOSFET is taken as an example, and among the bipolar transistors, a PNP transistor is taken as an example. In a DMOSFET, the channel polarity may be P-channel. Can be applied. Further, the drain layer of the DMOSFET in the first embodiment may be formed of the N − type drain layer 2 and the separation layer 3 of the bipolar transistor may be formed of the N − type epitaxial growth layer.

In the first and second embodiments, the base contact layer and the collector contact layer are not formed in the bipolar transistor.
It may be formed simultaneously with the source layer of the MOSFET and the emitter layer of the bipolar transistor.

Although the body contact layer is not formed on the DMOSFET in the first and second embodiments, it may be formed simultaneously with the emitter layer of the bipolar transistor.

In the third embodiment, D
Among the MOSFETs, an N-channel DMOSFET is taken as an example, and among the bipolar transistors, an NPN transistor is taken as an example.
In an FET, the polarity of the channel may be P-channel, and the same applies to a PNP transistor for a bipolar transistor.

Further, the DMOSF in the third embodiment
The drain layer 25 of the ET and the collector layer 26 of the bipolar transistor are formed of an N- type epitaxial growth layer, but may be formed of a normal diffusion layer.

[0067]

According to the semiconductor device of the present invention, there is provided a semiconductor device having at least one DMOSFET and a bipolar transistor mounted on a semiconductor substrate.
Since the drain offset layer of the ET and the base layer of the bipolar transistor have a structure having impurities introduced at the same time, the number of steps can be reduced and the DMOSFET can be reduced.
Can be reduced.

According to the method of manufacturing a semiconductor device of the present invention,
In a method of manufacturing a semiconductor device having a DMOSFET and a bipolar transistor mounted on a semiconductor substrate, a DMOS
A step of introducing a first conductivity type impurity into a region surrounded by the drain layer of the FET and a region surrounded by the collector layer of the bipolar transistor to simultaneously form a drain offset layer of the DMOSFET and a base layer of the bipolar transistor; Therefore, it is possible to form a semiconductor device equipped with a DMOSFET having a low on-resistance without separately providing a step of forming only the drain offset layer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a process of forming a drain layer of a DMOSFET and an isolation layer and a collector layer of a PNP bipolar transistor in a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 2 shows a drain offset layer of a DMOSFET and a PNP in a manufacturing process of the semiconductor device according to the first embodiment.
FIG. 9 is a cross-sectional view showing a process up to formation of an intrinsic base layer of a bipolar transistor.

FIG. 3 is a cross-sectional view showing a process up to formation of an insulated gate and a body layer of a DMOSFET in a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 4 is a cross-sectional view illustrating a process of forming a source layer and a drain contact layer of a DMOSFET and an emitter layer of a PNP bipolar transistor in a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 5 shows an insulated gate and drain layer of a DMOSFET and N in a manufacturing process of a semiconductor device according to a second embodiment.
FIG. 5 is a cross-sectional view showing a process until a separation layer and a collector layer of a P bipolar transistor are formed.

FIG. 6 is a cross-sectional view illustrating a process of forming a drain contact layer of a DMOSFET and an intrinsic base layer of an NP bipolar transistor in a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 7 is a cross-sectional view showing a process of forming a buried drain layer of a DMOSFET and a buried collector layer of an NPN bipolar transistor in a manufacturing process of the semiconductor device according to the third embodiment.

FIG. 8 is a cross-sectional view illustrating a process of forming a N-type epitaxial layer and an isolation layer in a manufacturing process of the semiconductor device according to the third embodiment.

FIG. 9 shows a drain offset layer of a DMOSFET and an NPN in a manufacturing process of a semiconductor device according to a third embodiment.
FIG. 4 is a cross-sectional view showing a process up to formation of a collector wall layer of a bipolar transistor.

FIG. 10 shows an insulated gate and a body layer of a DMOSFET and N in a manufacturing process of a semiconductor device according to a third embodiment.
FIG. 9 is a cross-sectional view showing a process up to formation of an intrinsic base layer of a PN bipolar transistor.

FIG. 11 is a cross-sectional view illustrating a process of forming a source layer and a drain contact layer of a DMOSFET and an emitter layer and a collector contact layer of an NPN bipolar transistor in a manufacturing process of the semiconductor device according to the third embodiment.

FIG. 12 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 Drain layer 3 Separation layer 4 Collector layer 5 Resist film 6 Drain offset layer 7 Intrinsic base layer 8 Gate oxide film 9 Polycrystalline silicon gate electrode 10 Resist film 11 Body layer 12 Source layer 13 Drain contact layer 14 Emitter Layer 17 resist film 19 resist film 20 P-type semiconductor substrate 21 buried collector layer 22 buried drain layer 23 epitaxial layer 24 separation layer 25 drain layer 26 collector layer 27 collector wall layer 28 drain offset layer 29 intrinsic base layer 30 gate oxide film 31 many Crystal silicon gate electrode 32 Resist film 33 Body layer 34 Resist film 35 Source layer 36 Drain contact layer 37 Emitter layer 38 Collector contact layer Rdmos DMOSFET formation region Rbpnp PNP Lee Paula transistor forming region Rbnpn NPN bipolar transistor forming region

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-176640 (JP, A) JP-A-60-137055 (JP, A) JP-A-4-17364 (JP, A) JP-A-5-176640 198757 (JP, A) JP-A-62-247558 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8248-21/8249 H01L 27/06

Claims (4)

(57) [Claims] At least one DMO on a semiconductor substrate
In a semiconductor device equipped with an SFET and a bipolar transistor, the DMOSFET includes a gate electrode formed on the semiconductor substrate via a gate insulating film, and a region in the semiconductor substrate including at least a region below the gate electrode. A drain layer including a low-concentration first-conductivity-type impurity, a source layer including a high-concentration first-conductivity-type impurity formed in a region in the semiconductor substrate located on one side of the gate electrode; A drain offset which is located on the other side of the gate electrode in a region surrounded by the drain region and is apart from the gate electrode and which has a higher concentration of the first conductivity type impurity than the drain layer; A first conductivity type impurity formed in a region surrounded by the drain offset layer and having a higher concentration than the drain offset layer; A drain contact layer including the source layer, surrounding the source layer, reaching a part of a region below the gate electrode in a region near the surface of the semiconductor substrate, and being separated from the drain contact layer by a predetermined distance with the drain layer interposed therebetween And a body layer containing a second conductivity type impurity having a threshold control level formed as described above. The bipolar transistor is formed in a region surrounded by the collector layer containing the second conductivity type impurity and the collector layer. A base layer containing a first conductivity type impurity; and an emitter layer formed in a region surrounded by the base layer and containing a second conductivity type impurity, wherein the drain offset layer of the DMOSFET and the base layer of the bipolar transistor are provided. Contains the first conductivity type impurity introduced at the same time, and the diffusion depth thereof is
A semiconductor device characterized by being deeper than a diffusion depth of a source layer of an FET. 2. The semiconductor device according to claim 1, wherein the concentration of the first conductivity type impurity in the drain layer of the DMOSFET is 5 × 10 ^{14 to} 5 × 10 ¹⁶ cm ^−3. . 3. A first step of forming a semiconductor substrate having a DMOSFET formation region and a bipolar transistor formation region, and a first step of forming a drain layer of the DMOSFET by introducing a first conductivity type impurity into the DMOSFET formation region. A third step of introducing a second conductivity type impurity into the bipolar transistor forming region to form a collector layer of the bipolar transistor; and a region surrounded by the drain layer of the DMOSFET and the bipolar transistor. A fourth step of introducing a first conductivity type impurity into a region surrounded by the collector layer and then performing a heat treatment to simultaneously form a drain offset layer of the DMOSFET and a base layer of the bipolar transistor; After the step, the semiconductor substrate is oxidized to A fifth step of forming a gate insulating film in the OSFET formation region, and then forming a gate electrode on the gate insulating film in a region apart from the drain offset layer; and forming a gate electrode on one side of the gate electrode. And introducing a second conductivity type impurity into a region surrounded by the drain layer to reach a part of a region below the gate insulating film.
A sixth step of forming a body layer of the SFET; a drain contact layer of a first conductivity type in a region surrounded by the drain offset layer in the DMOSFET formation region; and a source of a first conductivity type surrounded by the body layer. A seventh step of forming a second conductive type emitter layer surrounded by the base layer in the bipolar transistor formation region.
Wherein the drain offset layer of the DMOSFET and the base layer of the bipolar transistor are connected to the DMOSFE
T has a higher impurity concentration than the drain layer and a lower impurity concentration than the drain contact layer.
A method for manufacturing a semiconductor device, wherein the depth is greater than a diffusion depth of a source layer of a MOSFET. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the concentration of the first conductivity type impurity in the drain layer of the DMOSFET is 5 × 10 ^{14 to} 5 × 10 ¹⁶ cm ^−3. A method for manufacturing a semiconductor device.