JP3306691B2 - Wiring method for integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method for an integrated circuit device, and more particularly to a wiring method for a high density CMOS static memory cell.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor memory devices has been increasing, and there is still a strong demand for higher integration.

Conventionally, in a CMOS static memory cell on a silicon substrate, after forming a plurality of CMOS transistor matrices, an interlayer insulating film is formed on a source region, a drain region, and a gate electrode. A contact hole reaching the source region, the drain region, and the gate electrode is formed on the entire surface including the contact hole, and a metal film is formed on the entire surface including the contact hole. By patterning the metal film, the drain region of the nMOS transistor and the drain Between the regions, or between the drain region of the nMOS transistor and the pMOS
The connection is made between the drain region of the transistor and the gate of another CMOS transistor.

In such a conventional wiring method, when forming a contact hole, in addition to the size of the contact hole itself, a margin of the contact hole with respect to a diffusion region such as a source region or a drain region or a gate electrode or a wiring with respect to a wiring. A contact hole margin is required.

[0005] To add a further explanation, for example, if there is no margin when a contact hole is formed with respect to a diffusion layer which is a source region or a drain region and there is misalignment, a field oxide film defining an element formation region is formed. Etching the edge, destroys the pn junction for element isolation underneath, causing leakage current,
In addition, when there is no margin when forming a contact hole with respect to the gate electrode and misalignment occurs, problems such as penetrating the oxide film near the gate electrode and insufficient contact area due to insufficient effective area of the contact hole. Was occurring.

In order to avoid such a problem, it is necessary to secure a sufficient margin for this alignment. In particular, in a large-capacity storage device (memory cell) having a large number of contact holes, a fine structure is required. It is difficult to convert.

Conventionally, as a method of wiring between a source region, a drain region and a gate electrode without forming a contact hole, a method using an auxiliary local wiring in addition to a normal metal wiring has been proposed in T.K. Tang et al. (I
EEE International Electro
n Device Meeting 85 (198
5). Technical Digest pp. 59
0-593).

FIG. 8 shows a conventional wiring method for an integrated circuit device.
It is explanatory drawing, (A) shows a cross section, (B) is the circuit
Is shown. In this figure, 61 is p⁺Type silicon base
Plate, 62 is a p-type silicon crystal layer, 62 ₁Is the p-type region, 6
2_TwoIs an n-type region, 62₁₁, 62_{twenty one}Is the source area, 6
2₁₂, 62 _{twenty two}Is the drain region, 63 is the field oxidation
Film, 64 is a gate insulating film, 65₁, 65_TwoIs the gate
Pole, 65_ThreeIs the wiring, 66₁₁, 66₁₂, 66_{twenty one}, 66_{twenty two},
66₃₁, 66₃₂Is the side wall, 67₁₁, 67₁₂, 6
7₁₃, 67_{twenty one}, 67_{twenty two}, 67_{twenty three}, 67_ThreeIs silicide
The layer 68 is a local wiring.

A wiring method for a conventional integrated circuit device will be described with reference to this explanatory diagram. In this description, a number of steps actually performed are collectively described as appropriate.

First Step First, a p-type silicon crystal layer 62 is epitaxially grown on a p ⁺ -type silicon substrate 61, and p-type impurities and n-type impurities are selectively introduced into the surface of the p-type silicon crystal layer 62. Te to form a p-type region 62 ₁ and the n-type region 62 _2. Then, by forming a field oxide film 63 on the p-type region 62 ₁ and the n-type region 62 _2, p-type region 62 ₁ and the n-type region 62
₂ defines a MOSFET formation region.

Second step The surface of the MOSFET forming region is thermally oxidized to form a gate insulating film 64, a polycrystalline silicon film is formed on the entire surface thereof, and the polycrystalline silicon film is patterned to form a p-type region. 62 form _one n-type region 62 _{and second} MOSFET forming region with the gate electrode 65 _1, 65 ₂ and the wiring 65 _3.

Third Step In a state where the n-type region 62 ₂ is covered, the gate electrode 65 ₁ is used as a mask to form n-type regions 62 ₁ on both sides of the gate electrode 65 _1.
Type impurity to form a source region 62 ₁₁ and the drain region 62 ₁₂ n-type by ion implantation. Conversely, the p-type region 6
Forming a p-type source region 62 ₂₁ and the drain region 62 ₂₂ by ion implantation of p-type impurities using the gate electrode ₆₅₂ as a mask to n-type region 62 ₂ on both sides of the gate electrode ₆₅₂ while covering the 2 ₁ I do.

Fourth Step An SiO ₂ film is formed on the entire surface by CVD, and this SiO ₂ film is formed.
Sidewall 6 ₂ film on the side surfaces of the gate electrodes 65 _1, 65 ₂ by anisotropic etching by RIE
6 _11, 66 _12, 66 _21, 66 ₂₂ is formed, to form a side wall 66 _31, 66 ₃₂ on the side surfaces of the wires 65 _3.

Fifth step Then, the source region 62 ₁₁ , the drain region 62 ₁₂ , the source region 62 ₂₁ , and the drain region 62 which are single crystal silicon
₂₂ , the surface of the gate electrode 65 ₁ , the gate electrode 65 ₂ , and the wiring 65 ₃ , which are polycrystalline silicon, are silicided to form low-resistance silicide layers 67 ₁₁ , 67 ₁₂ , 67 ₁₃ , 67 ₂₁ , 6.
7 _22, 67 _23, 67 ₃ to form a.

Sixth Step Subsequently, a titanium nitride film is formed on the entire surface, and is patterned to include the silicide layers 67 ₁₂ , 67 ₂₂ , and 67 ₃ and the gates of the other CMOS transistors P ₂ and N _2. The wiring 68 is formed. Next, an interlayer insulating film is deposited by a conventionally known process, contact holes are opened, and a metal wiring is formed through these contact holes.

According to this method, no contact hole for the metal wiring layer is required at the cross connection portion of the inverter, and the cell area can be reduced accordingly.

[0017]

The method using the local wiring, which has been conventionally proposed, can certainly reduce the number of contact holes and is effective in reducing the size of an integrated circuit device. In addition, since the silicide layer is exposed on the surface of the wiring and the wiring, the wiring cannot be crossed with the gate electrode, and the applicable range is considerably limited.
In view of this disadvantage, the present invention provides an integrated circuit device having a local wiring which can be arbitrarily crossed or contacted with a gate electrode, and which does not impair the advantage of area reduction by reducing contact holes. The purpose is to provide.

[0018]

In the method of wiring an integrated circuit device according to the present invention, a step of forming a wiring material film on a substrate and a step of forming an insulating material film on the wiring material film And a step of selectively removing a part of the insulating material film on which a wiring is to be formed by the wiring material film, and then, the insulating material film and the wiring material partially removed. Forming a wiring by patterning the film with the same mask, then forming an insulating film on the side surface of the wiring, and then selectively removing the surface of the substrate and part of the insulating material film A step of forming a local wiring connecting the surfaces of the wirings exposed as a result.

In this case, the insulating material film formed on the wiring material film is made of a material substantially transparent to the wavelength of exposure light used when patterning the wiring material film and the insulating material film by a photolithography process. And the film thickness can be an integral multiple of a half wavelength of the exposure light in the insulating material film.

In another wiring method for an integrated circuit device according to the present invention, a step of forming a wiring material film on a substrate;
Next, a step of forming an insulating material film on the wiring material film, and then forming a wiring by patterning the insulating material film and the wiring material film with the same mask,
Next, a step of removing a part of the insulating material film on the wiring, a step of forming an insulating film on a side surface of the wiring, and then, the surface of the substrate and a part of the insulating material film Forming a local wiring for connecting the surface of the wiring exposed by the selective removal.

In these cases, the surface of the substrate can be a source region or a drain region, and the wiring can be a gate electrode or the like.

[0022]

FIG. 1 is a view for explaining the principle of a wiring method for an integrated circuit device according to the present invention, wherein (A) and (B) show respective steps. With reference to this figure, steps in the case where the present invention is applied to the manufacture of a CMOS static memory cell will be described.

In this figure, 1 is a p ⁺ type silicon substrate,
2 is a p-type silicon layer, 2 ₁ is a p-type region, 2 ₂ is an n-type region, 2 ₁₁ and 2 ₂₁ are source regions, 2 ₁₂ and 2 ₂₂ are drain regions, 3 is a field oxide film, 4 ₁ and 4 ₂ Is a gate oxide film, 5 is a polycrystalline silicon film, 6 is a silicon oxide film,
5 _1, 5 ₂ gate electrode, 5 ₃ wire, 6 _1, 6 _2, 6
₃ is an opening, 7 ₁₁ , 7 ₁₂ , ₇₂₂ , ₇₂₁ , 7 ₃₁ , and 7 ₃₂ are sidewalls, 8 ₁₁ , 8 ₁₂ , 8 ₁₃ , 8 ₂₁ , 8 ₂₂ , 8 ₂₃ , 8
₃ is a metal silicide layer, 9 is a local wiring, 10 is an interlayer insulating film, 10 ₁₁ , 10 ₁₂ , 10 ₂₂ and 10 ₂₁ are contact holes, and 11 ₁₁ , 11 ₁₂ , 11 ₂₂ and 11 ₂₁ are metal wirings.

[0024] First, p ⁺ -type silicon p-type silicon layer 2 is deposited on the substrate 1, the active layer of the n-channel MOSFET by selectively introducing an n-type impurity and the p-type impurity p-type regions 2 ₁ And n serving as an active layer of a p-channel MOSFET.
-Type region 2 _2, then a field oxide film 3 on the periphery of p-type region 2 ₁ and n-type regions 2 ₂ of the MOSFET formation region.

P-type region 2₁And n-type region 2_TwoHot acid surface
Into a gate oxide film 4₁, 4_TwoForming the whole surface on it
A polycrystalline silicon film 5 is formed on the
An oxide film 6 is grown, and the polysilicon film 5
Electrode 5₁, 5_TwoAnd wiring 5_ThreeThe area that will form the
A portion of the silicon oxide film 6 is selectively removed to form an opening.
6 ₁, 6_Two, 6_Three(Refer to FIG. 1A)
See).

Next, the opening 6₁, 6_Two, 6_ThreeWith
A two-layer film composed of the silicon oxide film 6 and the polycrystalline silicon film 5
Patterned gate electrode 5₁, 5_TwoAnd wiring 5_ThreeThe shape
To form an n-type region 2_TwoWith the gate electrode 5
₁Is used as a p-type region 2 ₁N-type impurities
Enter source area 2₁₁And drain region 2₁₂Form
Conversely, p-type region 2₁With the gate
Pole 5_TwoIs used as a mask to form an n-type region 2_TwoP-type impurities
Implant and drain region 2_{twenty two}And source area 2_{twenty one}Form
You.

[0027] Then sidewall 7 ₁₁ on the side surfaces of the gate electrode 5 _1, 5 ₂ and the wiring 5 _3, 7 _12, 7 _22, 7 _21, 7 _31,
7 ₃₂ is formed, is exposed to the surface, the source region 2 ₁₁ made of single crystal, the drain region 2 _12, the drain region 2 _22,
Source region 2 _21, and the polycrystalline silicon film gate electrode 5 ₁ consisting of 5, 5 _2, the metal silicide layer 8 ₁₁ on the upper surface of the wiring _3, 8 _12, 8 _13, 8 _21, 8 _22, 8 _23, 8 ₃ is formed, a tungsten film is deposited on the entire surface, and the tungsten film is patterned so as to remain on the region including the metal silicide layers 8 ₁₂ , 8 ₂₂ , and 8 ₃ to form the local wiring 9. The interlayer insulating film 10 is deposited by the steps described above, and the contact hole 1 formed in the interlayer insulating film 10 is formed.
Metal wiring 1 through 0 ₁₁ , 10 ₁₂ , 10 ₂₂ and 10 ₂₁
1 ₁₁ , 11 ₁₂ , 11 ₂₂ and 11 ₂₁ are formed (see FIG.
(B)).

As described above, the polycrystalline silicon film 5
After selectively removing a part of the silicon oxide film 6 formed thereon, the two-layer film composed of the silicon oxide film 6 and the polycrystalline silicon film 5 is patterned to form the gate electrode 5.
_1, 5 ₂ and instead of forming the wiring _3, after forming the gate electrode 5 _1, 5 ₂ and the wiring 5 ₃ by patterning the two-layer film composed of a silicon oxide film 6 of a polycrystalline silicon film 5 Alternatively, a part of the silicon oxide film 6 can be selectively removed by etching.

When an insulating film is deposited on a wiring material film formed on a substrate as in the wiring method of the integrated circuit device according to the present invention, the insulating portion at the connection between the wiring formed by the wiring material film and the local wiring is formed. Regardless of whether the step of selectively removing the film is before or after the patterning of the wiring, the thickness of this insulating film does not need to be as large as that of the interlayer insulating film. By forming an excessive opening in this insulating film,
Alternatively, even if an opening is formed at a position deviating from the wiring pattern, etching through the thick field oxide film or the like does not occur in the step of forming this opening.

In this case, when the wiring is a gate electrode of a MOSFET, it is not necessary to take a margin for alignment required in the prior art, and if the insulating film is removed to be larger than the wiring pattern. Good. Therefore, when forming a contact hole, there is no increase in area due to a processing margin, and it is possible to cross another wiring in a portion where the insulating film is left without being removed.

[0031]

Embodiments of the present invention will be described below. (First Embodiment) FIGS. 2 and 3 are views for explaining the manufacturing process of the CMOS static memory cell of the first embodiment.
(A)-(F) have shown each process.

In this figure, 1 is a p ⁺ type silicon substrate,
2 is a p-type silicon layer, 2 ₁ is a p-type region, 2 ₂ is an n-type region, 2 ₁₁ and 2 ₂₁ are source regions, 2 ₁₂ and 2 ₂₂ are drain regions, 3 is a field oxide film, 4 ₁ and 4 ₂ Is a gate oxide film, 5 is a polycrystalline silicon film, 5 ₁ and 5 ₂ are gate electrodes,
5 ₃ is a wiring, 6 is a silicon oxide film, 6 ₁ , 6 ₂ , 6 ₃ are openings, 7 ₁₁ , 7 ₁₂ , 7 ₂₁ , 7 ₂₂ , 7 ₃₁ , 7 ₃₂ are sidewalls, 8 ₁₁ , 8 ₁₂ , 8 ₁₃ , 8 ₂₁ , 8 ₂₂ , 8 ₂₃ , and 8 ₃ are metal silicide layers, 9 is a local wiring, 10 is an interlayer insulating film,
10 ₁₁ , 10 ₁₂ , 10 ₂₁ , 10 ₂₂ are contact holes,
11 ₁₁ , 11 ₁₂ , 11 ₂₁ , and 11 ₂₂ are metal wirings.
The manufacturing method of the CMOS static memory cell according to the first embodiment will be described with reference to this process explanatory diagram.

First Step (See FIG. 2A) A p-type silicon layer 2 is deposited on a p ⁺ -type silicon substrate 1 by epitaxial growth, and an n-type impurity is introduced to
The p-type region 2 ₁ as the active layer of the channel MOSFET is formed, to form an n-type region 2 ₂ to be the active layer of the p-channel MOSFET by introducing a p-type impurity. Then, a field oxide film 3 by a LOCOS method on the periphery of p-type region 2 ₁ and n-type regions 2 ₂ of the MOSFET formation region.

The second step to form a (see FIG. 2 (B) refer) gate oxide film of thickness 7nm by a p-type region 2 ₁ and n-type regions 2 ₂ of the surface is thermally oxidized 4 _1, 4 _2,
A polycrystalline silicon film 5 having a thickness of 180 nm is formed on the entire surface by chemical vapor deposition (CVD), and a silicon oxide film 6 having a thickness of 100 nm is grown on the entire surface by CVD.

The third step (FIG. 2 (C) see) the fourth gate electrode 5 ₁ is formed by a polycrystalline silicon film 5 in step 5 ₂ and a portion of the silicon oxide film 6 on the wiring 5 ₃ after Are selectively etched away by a photolithography process to form openings 6 ₁ , 6 ₂ , 6 ₃ .

Fourth step (see FIG. 3D)₁, 6_Two, 6_ThreeSilicon formed
The oxide film 6 and the polycrystalline silicon film 5 are patterned to
Port electrode 5₁, 5_TwoAnd wiring 5_ThreeTo form Then, n
Mold area 2_TwoWith the gate electrode 5₁The trout
And p-type region 2₁Ion implantation of n-type impurities into
Source area 2₁₁And drain region 2₁₂To form Also reverse
The p-type region 2₁With the gate electrode 5_Two
Is used as a mask to form an n-type region 2_TwoImplant p-type impurities
And drain region 2_{twenty two}And source area 2 _{twenty one}To form

Fifth Step (See FIG. 3E) A silicon oxide film having a thickness of 100 nm is deposited on the entire surface by the CVD method, and the silicon oxide film is etched by an anisotropic reactive ion etching (RIE). ,
Only leaving selectively on the side surfaces of the gate electrode 5 _1, 5 ₂ and the wiring 5 _3, side walls 7 _11, 7 _12, 7 _22, 7 _21,
7 ₃₁ and 7 ₃₂ are formed. Then, exposed on the surface,
Source region 2 ₁₁ made of single crystal, the drain region 2 _12, the drain region 2 _22, the source region 2 _21, and the gate electrode 5 ₁ made of polycrystalline silicon film 5, 5 _2, a refractory metal on the top surface of the wiring ₃ For example, by selectively reacting cobalt, metal silicide layers 8 ₁₁ , 8 ₁₂ , 8 ₁₃ , 8 ₂₂ , 8 ₂₁ ,
8 _23, to form the 8 _3.

Sixth step (see FIG. 3F) A tungsten film having a thickness of, for example, 80 nm is deposited on the entire surface.
This tungsten film is formed into a metal silicide layer 8 ₁₂ , 8 ₂₂ , 8
_The local wiring 9 is formed by patterning so as to remain on the region including ₃ . Next, an interlayer insulating film 10 is deposited by a conventionally known process to form contact holes 10 ₁₁ , 10 ₁₂ , 10 ₂₂ , and 10 ₂₁ .
Through these contact holes, metal wirings 11 ₁₁ , 1
1 ₁₂ , 11 ₂₂ and 11 ₂₁ are formed.

(Second Embodiment) FIGS. 4 and 5 show a second embodiment.
Of manufacturing process of CMOS static memory cell
And (A) to (F) show the respective steps. This figure
Where 21 is p⁺Type silicon substrate, 22 is p-type silicon
Layer, 22₁Is a p-type region, 22_TwoIs an n-type region, 22₁₁,
22_{twenty one}Is the source region, 22₁₂, 22_{twenty two}Is the drain region,
23 is a field oxide film, 24₁, 24_TwoIs the gate oxidation
Film 25, polycrystalline silicon film, 25₁, 25_TwoIs the gate
Electrode, 25_ThreeIs wiring, 26, 26 ₁, 26_Two, 26_ThreeIs
Silicon nitride film, 26₁₁, 26_{twenty one}, 26₃₁Is an opening, 27
₁₁, 27₁₂, 27_{twenty one}, 27_{twenty two}, 27₃₁, 27₃₂Is the side
Wall, 28₁₁, 28₁₂, 28₁₃, 28_{twenty one}, 28_{twenty two},
28_{twenty three}, 28_ThreeIs a metal silicide layer, 29 is a local wiring,
30 is an interlayer insulating film, 30₁₁, 30₁₂, 30_{twenty one}, 30_{twenty two}Is
Contact hole, 31₁₁, 31₁₂, 31_{twenty one}, 31_{twenty two}Is
Metal wiring. According to FIG.
A method for manufacturing a CMOS static memory cell will be described.
You.

First step (see FIG. 4A) A p-type silicon layer 22 is deposited on a p ⁺ -type silicon substrate 21 by epitaxial growth, and an n-type impurity is introduced to form a p-type silicon layer 22 serving as an active layer of an n-channel MOSFET. Mold area 22
₁ to form a p-channel MOSF
Forming an n-type region 22 ₂ the ET active layer. Then, a field oxide film 23 by the LOCOS method on the periphery of p-type region 22 ₁ and the n-type region 22 _{and second} MOSFET forming region.

The second step to form a (see FIG. 4 (B) refer) gate oxide film thickness 7nm by a p-type region 22 ₁ and the n-type region 22 _{and second} surface thermally oxidized film 24 _1, 24 _2, the 180n film thickness on the entire upper surface by CVD
m of polycrystalline silicon film 25 is deposited, and C
Silicon nitride (Si ₃
N ₄ ) Grow the film 26.

Third Step (See FIG. 4C) The silicon nitride film 26 and the polycrystalline silicon film 25 are patterned
The silicon nitride film 26₁, 26_Two, 26_ThreeIs covered
Covered gate electrode 25₁, 25_TwoAnd wiring 25 _ThreeForm
I do.

[0043] In the fourth step a state of covering the top (FIG. 5 (D) refer) n-type region 22 _2, a silicon nitride film 2
6 ₁ The n-type impurity ions are implanted using the gate electrode 25 ₁ is coated on the mask to the p-type region 22 ₁ the source region 2
2 ₁₁ and a drain region 22 ₁₂ are formed. Conversely, p
While covering over the mold area 22 _1, a silicon nitride film 26
₂ a p-type impurity is ion implantation with a mask of the gate electrode 25 ₂ which is coated on the n-type region 22 _second drain region 2
2 ₂₂ and a source region 22 ₂₁ are formed. Then, the silicon nitride film 26 ₁ covering the gate electrode 25 _1, the silicon nitride film 26 ₂ covering the gate electrode 25, the wiring 2
5 ₃ selectively etched by a photolithography process a part of the silicon nitride film 26 ₃ covering the forming the opening 26 _11, 26 _21, 26 _31.

Fifth step (see FIG. 5E) A 100 nm-thick silicon oxide film is formed on the entire surface by CVD.
Deposit a film and react this silicon oxide film with anisotropy
Etched by reactive ion etching (RIE)
Gate electrode 25₁, 25_TwoAnd wiring 25_ThreeLeft only on the side of
Then, the side wall 27₁₁, 27₁₂, 27_{twenty two}, 2
7_{twenty one}, 27₃₁, 27₃₂To form Then exposed on the surface
Source region 22 made of single crystal₁₁,drain
Region 22₁₂, Drain region 22_{twenty two}, Source region 22_{twenty one},
And gate electrode 25 made of polycrystalline silicon film 25
₁, 25_Two, Wiring 25_ThreeRefractory metal, for example,
Selective reaction of baltic, titanium, and tungsten
Metal silicide layer 28 ₁₁, 28₁₂, 28₁₃, 28_{twenty one}, 28
_{twenty two}, 28_{twenty three}, 28_ThreeTo form

Sixth step (see FIG. 5F) A tungsten film having a thickness of, for example, 80 nm is deposited on the entire surface.
This tungsten film is formed into a metal silicide layer 28 ₁₂ , 2
8 _22, 28 ₃ is patterned to leave on a region including the forming the local interconnection 29. Next, an interlayer insulating film 30 is deposited by a conventionally known process to form contact holes 30 ₁₁ , 30 ₁₂ , 30 ₂₂ , and 30 _21, and metal wirings 31 ₁₁ , 3 through these contact holes.
Forming one _12, 31 _22, 31 _21.

(Third Embodiment) In the wiring method for an integrated circuit device described in the first embodiment, the third step (see FIG. 2C) to the fourth step (see FIG. 3D). ), The region where the polycrystalline silicon film 5 is exposed and the region where the silicon oxide film 6 is formed on the polycrystalline silicon film 5 are patterned by a single exposure and development photolithography process. , Gate electrodes 5 ₁ , 5
To form a ₂ and the wiring 5 _3.

Usually, in such a fine pattern exposure step, in order to suppress the standing wave generated by the exposure light and the reflected light in order to increase the patterning accuracy,
The anti-reflection film is coated on the material to be patterned, but the optimum conditions for this anti-reflection film vary depending on conditions such as the amplitude of reflected light from the underlying patterned material and the phase shift between exposure light and reflected light. I do.

In other words, when patterning a region having a different underlying optical state, the same patterning accuracy cannot be expected over the entire region. In this embodiment, for example, in the first embodiment, a region where the polysilicon film 5 is exposed and a region where the silicon oxide film 6 is formed on the polysilicon film 5 are exposed once. An object is to realize highly accurate patterning over the entire area even when patterning is performed by development.

FIGS. 6 and 7 are views for explaining the manufacturing process of the CMOS static memory cell of the third embodiment, and FIG.
(E) show each step.

[0050] 41 p ⁺ -type silicon substrate in this figure, 42 is a p-type silicon layer, 42 ₁ p-type region, 42 ₂
Is an n-type region, 42 ₁₁ and 42 ₂₁ are source regions, 42 ₁₂ and 4
2 ₂₂ is a drain region, 43 is a field oxide film, 4
4 _1, 44 ₂ is gate oxide film, 45 is a polycrystalline silicon film, 45 _1, 45 ₂ a gate electrode, 45 ₃ wire, 46
Silicon oxide film, 46 _1, 46 _2, 46 ₃ opening, 4
7 is an amorphous carbon film, 48 is a photoresist film, 49 ₁₁ ,
49 ₁₂ , 49 ₂₁ , 49 ₂₂ , 49 ₃₁ , and 49 ₃₂ are sidewalls, 50 ₁₁ , 50 ₁₂ , 50 ₁₃ , 50 ₂₁ , 50 ₂₂ , and 50.
_23, 50 ₃ metal silicide layer, 51 is a local interconnect, 52
Interlayer insulating film, 52 _11, 52 _12, 52 _21, 52 ₂₂ contact holes, 53 _11, 53 _12, 53 _21, 53 ₂₂ is a metal wire. According to this process explanatory diagram, the CM of the third embodiment is shown.
A method for manufacturing an OS static memory cell will be described.

First Step (See FIG. 6 (A)) A p-type silicon layer 42 is deposited on a p ⁺ -type silicon substrate 41 by epitaxial growth, and an n-type impurity is introduced to form a p-type active layer of an n-channel MOSFET. Mold area 42
₁ to form a p-channel MOSF
Forming an n-type region 42 ₂ the ET active layer. Then, a field oxide film 43 by the LOCOS method on the periphery of p-type region 42 ₁ and the n-type region 42 _{and second} MOSFET forming region.

[0052] The second step is formed (FIG. 6 (B) refer) p-type region 42 ₁ and the n-type region 42 a gate oxide film 44 ₁ having a thickness 7nm by the _second surface is thermally oxidized, 44 _2, the A polycrystalline silicon film 45 having a thickness of 180 nm is formed on the entire upper surface by a chemical vapor deposition (CVD) method.
A silicon oxide film 46 is grown on the entire surface by CVD.

[0053] The silicon oxide film 46 is later selectively etched and exposure of the resist film 48 is performed in the step of forming the gate electrode 45 _1, 45 ₂ and the wiring 45 ₃ polycrystalline silicon film 45 in the fourth step It is substantially transparent to the wavelength of the light, and its film thickness is an integral multiple of a half wavelength of the exposure light in the silicon oxide film 46.

That is, when a KrF excimer laser having a wavelength of 248 nm in a vacuum is used as the exposure light, the silicon oxide film 46 is transparent without substantial absorption. In general, the wavelength of light transmitted through a medium is a value obtained by dividing the wavelength in a vacuum by the refractive index of the medium.
Assuming that the refractive index of the silicon oxide film 46 is 1.48, the wavelength in the silicon oxide film 46 is 248 nm / 1.
48 ≒ 168 nm. Therefore, the thickness of the silicon oxide film 46 is set to 84 nm which is a half wavelength of the KrF excimer laser light in the silicon oxide film 46.

Next, in a later fourth step, a polycrystalline silicon film is formed.
Gate electrode 45 formed by 45₁, 45_TwoAnd
And wiring 45_ThreePhoto of part of silicon oxide film 46 on top
Selective etching removal by lithography process
Opening 46₁, 46_Two, 46 _ThreeTo form

Third Step (See FIG. 6C) An amorphous carbon film 47 having a film thickness of 45 nm is formed thereon as an antireflection film by a CVD method. The amorphous carbon film 47 can control the refractive index and the absorption coefficient of light to some extent under the film formation conditions of the CVD method. In this embodiment, the refractive index is 1.58 and the absorption coefficient is 1.58. Was 0.75.

A photoresist film 48 is formed on the amorphous carbon film 47, and the photoresist film 48 is patterned on the polycrystalline silicon film 45 to form the gate electrode 4
5 _1, 45 to form a ₂ and the wiring 45 _3, wavelength selectively exposed using a KrF excimer laser of 248 nm, is patterned and developed.

[0058] patterning the fourth step (FIG. 7 (D) refer) silicon oxide film 46 and the polycrystalline silicon film 45 with an opening 46 ₁ in the second step, 46 _2, 46 ₃ is formed, is formed in the third step The gate electrode 45 is patterned by using the patterned photoresist film 48.
Forming a _1, 45 ₂ and the wiring 45 _3. After formation of the gate electrode 45 _1, 45 ₂ and the wiring 45 _3, the photoresist film 48 and the amorphous carbon film 47 is removed by etching with a plasma.

[0059] Then, while covering over the n-type region 42 _2, the source region 42 ₁₁ and the drain region 42 ₁₂ is ion implanted n-type impurity into the p-type region 42 ₁ and the gate electrode 45 ₁ to the mask Form. Conversely, the p-type region 42 ₁
While covering over, the p-type impurity ions are implanted to form the drain region 42 ₂₂ and the source region 42 ₂₁ in the n-type region 42 ₂ and the gate electrode 45 ₂ as a mask.

Fifth step (see FIG. 7E) A 100 nm-thick silicon oxide film is formed on the entire surface by CVD.
A silicon oxide film is deposited and anisotropic RI
The gate electrode 45 is etched by E.₁, 45_TwoWhen
Wiring 45_ThreeSelectively leaving only the sides
Le 49₁₁, 49 ₁₂, 49_{twenty two}, 49_{twenty one}, 49₃₁, 49₃₂To
Form. Next, from the single crystal exposed on the surface,
Source region 42₁₁, Drain region 42₁₂, Drain area
Area 42_{twenty two}, Source region 42_{twenty one}And polycrystalline silicon
Gate electrode 45 composed of film 45₁, 45_Two, Wiring 45_Three
Refractory metal, such as cobalt, is selectively reacted on the upper surface of
Metal silicide layer 50₁₁, 50₁₂, 50₁₃, 5
0_{twenty two}, 50_{twenty one}, 50_{twenty three}, 50_ThreeTo form

Sixth step (see FIG. 7F) A tungsten film having a thickness of, for example, 80 nm is deposited on the entire surface.
This tungsten film is formed into a metal silicide layer 50 ₁₂ , 5
By patterning 0 _22, so as to leave on the region including the 50 ₃ to form a local interconnect 51. Then
An interlayer insulating film 52 is deposited, and contact holes 52 ₁₁ , 5
2 _12, 52 _22, 52 ₂₁ is formed, the metal wiring 53 ₁₁ through these contact holes 53 _12, 53 _22, 53 ₂₁
To form

As in this embodiment, the gate electrodes 45 ₁ ,
45 ₂ and the thickness of the silicon oxide film 46 is formed on the polycrystalline silicon film 45 for forming the wiring 45 _3,
Assuming that the wavelength is half the wavelength of the exposure light in the silicon oxide film 46, the light travels through the silicon oxide film 46, is reflected by the interface with the underlying polycrystalline silicon film 45, and
The optical state of the reflected light returning to the photoresist film 48 on the top 6 is exactly the same as the optical state of the reflected light on a region where the silicon oxide film 46 is not covered and the polycrystalline silicon film 45 is exposed. .

Therefore, the optimum condition of the antireflection film made of the amorphous carbon film 47 can be realized over the entire exposure range, and the standing wave can be reduced or the waveform of the standing wave can be designed. It should be noted that even if the thickness of the silicon oxide film 46 formed on the polycrystalline silicon film 45 is set to an integral multiple of half the wavelength of the exposure light in the silicon oxide film 46, the same effect as described above can be obtained. It is clear in principle.

In the fifth step of the first embodiment, a silicon oxide film having a thickness of 100 nm is deposited on the entire surface by the CVD method, and the silicon oxide film is subjected to reactive ion etching (RIE) having anisotropy. etched by only leaving selectively on the side surfaces of the gate electrode 5 _1, 5 ₂ and the wiring 5 _3, side walls 7 _11, 7 _12, 7 _22, 7 _21,
7 _31, 7 ₃₂ after forming (see FIG. 3 (E)), is deposited on the entire surface insulating film, is deposited the insulating film, the insulating film, a source region 2 _11, 2 _21, the drain region 2 ₁₂ , 2 ₂₂ , wiring 5
A groove having a local wiring shape reaching ₃ is formed by a photolithography process, a local wiring material such as tungsten is deposited on the entire surface including the groove with the local wiring shape, and the surface is polished by a chemical mechanical polishing method (CMP method). Then, the local wiring material can be left only in the groove having the local wiring shape to form a local wiring.

This method uses damascene.
Inlay method), but also in the second embodiment,
After the fifth step (see FIG. 5E), a local wiring can be formed by applying a similar step.

[0066]

As described above, according to the present invention,
Since wiring can be performed by local wiring without using a contact hole, high integration can be achieved without increasing the required area of the integrated circuit device, and an insulating film can be formed on the gate electrode and the wiring. Therefore, it is possible to arbitrarily intersect and connect with other wirings in a state of being insulated by the insulating film. In particular, the area of the SRAM cell can be reduced to achieve high integration, and in general, the height of the integrated circuit device can be increased. It greatly contributes to performance improvement.

When the thickness of the silicon oxide film formed on the polycrystalline silicon film forming the gate electrode is set to a half wavelength of the exposure light in the silicon oxide film or an integral multiple thereof, the silicon oxide film In the case where the region coated with and the region where the silicon oxide film is not coated are simultaneously patterned by the photolithography process, the reflection state of the exposure light generated in both regions is the same, and the standing wave is reflected to one of the regions. When the anti-reflection film or the like is set under such a condition that the value is minimized, the other condition is also optimized at the same time, and there is no difference in patterning accuracy between the two regions.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of a wiring method for an integrated circuit device according to the present invention, wherein (A) and (B) show respective steps.

FIG. 2 is an explanatory view (1) of a manufacturing process of the CMOS static memory cell of the first embodiment, and (A) to (C) show each process.

FIG. 3 is an explanatory view (2) of the manufacturing process of the CMOS static memory cell of the first embodiment, and (D) to (F) show each process.

FIG. 4 is an explanatory view (1) of a manufacturing process of the CMOS static memory cell according to the second embodiment, and (A) to (C) show each process.

FIG. 5 is an explanatory view (2) of a manufacturing process of the CMOS static memory cell according to the second embodiment, and (D) to (F) show each process.

FIG. 6 is an explanatory view (1) of a manufacturing process of the CMOS static memory cell of the third embodiment, and (A) to (C) show each process.

FIG. 7 is an explanatory view (2) of a manufacturing process of the CMOS static memory cell according to the third embodiment, and (D) to (F) show each process.

8A and 8B are explanatory diagrams of a wiring method of a conventional integrated circuit device, where FIG. 8A shows a cross section and FIG. 8B shows the circuit.

[Explanation of symbols]

1 p ⁺ -type silicon substrate 2 p-type silicon layer 2 ₁ p-type region 2 ₂ n-type region 2 _11, 2 ₂₁ source region 2 _12, 2 ₂₂ drain region 3 field oxide film 4 _1, 4 ₂ gate oxide film 5 polycrystal silicon film 5 _1, 5 ₂ gate electrode ₃ wiring 6 silicon oxide film 6 _and 62, 6 ₃ openings 7 _11, 7 _12, 7 _21, 7 _22, 7 _31, 7 ₃₂ sidewall 8 _11, 8 _12, 8 _13, 8 _21, 8 _22, 8 _23, 8 ₃ metal silicide layer 9 local wiring 10 interlayer insulating film 10 _11, 10 _12, 10 _21, 10 ₂₂ contact holes 11 _11, 11 _12, 11 _21, 11 ₂₂ metal wires Reference Signs ^List 21 p ⁺ type silicon substrate 22 p type silicon layer 22 ₁ p type region 22 ₂ n type region 22 ₁₁ , 22 ₂₁ source region 22 ₁₂ , 22 ₂₂ drain region 23 field oxide film 24 ₁ , 24 ₂ gate oxide film 25 polycrystalline Silicon film 25 ₁ , 25 ₂ gate electrode 25 ₃ wiring 26, 26 ₁ , 26 ₂ , 26 ₃ silicon nitride film 26 ₁₁ , 26 ₂₁ , 26 ₃₁ opening 27 ₁₁ , 27 ₁₂ , 27 ₂₁ , 27 ₂₂ , 27 ₃₁ , 27 ₃₂ side wall 28 ₁₁ , 28 ₁₂ , 28 ₁₃ , 28 ₂₁ , 28 ₂₂ , 28 ₂₃ , 2
8 ₃ metal silicide layer 29 local wiring 30 interlayer insulating film 30 ₁₁ , 30 ₁₂ , 30 ₂₁ , 30 ₂₂ contact hole 31 ₁₁ , 31 ₁₂ , 31 ₂₁ , 31 ₂₂ metal wiring 41 p ⁺ type silicon substrate 42 p type silicon layer 42 ₁ p-type region 42 ₂ n-type region 42 ₁₁ , 42 ₂₁ source region 42 ₁₂ , 42 ₂₂ drain region 43 field oxide film 44 ₁ , 44 ₂ gate oxide film 45 polycrystalline silicon film 45 ₁ , 45 ₂ gate electrode 45 ₃ wiring 46 silicon oxide films 46 ₁ , 46 ₂ , 46 ₃ openings 47 amorphous carbon film 48 photoresist films 49 ₁₁ , 49 ₁₂ , 49 ₂₁ , 49 ₂₂ , 49 ₃₁ , 49 ₃₂ side walls 50 ₁₁ , 50 ₁₂ , 50 ₁₃ , 50 ₂₁ , 50 ₂₂ , 50 ₂₃ , 5
0 ₃ metal silicide layer 51 local wiring 52 interlayer insulating film 52 _11, 52 _12, 52 _21, 52 ₂₂ contact holes 53 _11, 53 _12, 53 _21, 53 ₂₂ metal wires

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8244 H01L 21/336 H01L 21/768 H01L 27/11 H01L 29/78

Claims (4)

(57) [Claims] A step of forming a wiring material film on the substrate; a step of forming an insulating material film on the wiring material film; and a step of forming a wiring by the wiring material film. A step of selectively removing a part of the insulating material film, and a step of forming a wiring by patterning the insulating material film and the wiring material film partially removed with the same mask, Forming an insulating film on the side surface of the wiring; and connecting the surface of the substrate and the surface of the wiring exposed by selectively removing a part of the insulating material film.
A wiring method for an integrated circuit device, comprising a step of forming a local wiring. 2. An insulating material film formed on a wiring material film,
The wiring material film and the insulating material film are made of a material that is substantially transparent to the wavelength of the exposure light used for patterning by the photolithography process, and the thickness thereof is set in the insulating material film of the exposure light. 2. The wiring method for an integrated circuit device according to claim 1, wherein the wiring length is an integral multiple of a half wavelength. A step of forming a wiring material film on the substrate; a step of forming an insulating material film on the wiring material film; and forming the same insulating material film and the wiring material film on the same mask. Forming a wiring by patterning in a step, then, removing a part of the insulating material film on the wiring, and then forming an insulating film on a side surface of the wiring, Connecting the surface of the substrate and the surface of the wiring exposed by selectively removing a part of the insulating material film;
A wiring method for an integrated circuit device, comprising a step of forming a local wiring. 4. The wiring method of an integrated circuit device according to claim 1, wherein the surface of the substrate is a source region or a drain region.