JP3397986B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
The present invention relates to a semiconductor device for a vertical power MOS with a control circuit function for low voltage, which has a reduced on-resistance and an improved avalanche withstand capability, and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 7 is a sectional view of a conventional power MOSFET having a general control section and a power section. N +
The type semiconductor substrate 1 has an N − type epitaxial layer 2 on its surface, and constitutes a part of the drain region of the power section. The drain region 2 of the power portion is provided with a large number of regularly arranged P type body regions 6, and in the body region 6, a ring-shaped N + type source region is formed. A gate electrode 8 made of polycrystalline silicon is formed on the body region 6 to be the channel region 3 via an insulating layer.

On the other hand, the N-type epitaxial layer 2 serving as a control portion is electrically isolated by a P-type diffusion layer, and a control circuit including a transistor and the like is formed in the isolation region.
The control circuit formed in the control unit detects the current, voltage, etc. flowing through the power MOSFET formed in the power unit, and protects the power MOSFET from overcurrent, overvoltage, and the like. The above-mentioned similar technique is described in, for example, Japanese Patent Laid-Open No. 7-231090.

Since the above-mentioned power MOSFET handles a large current, it is desired to reduce the on resistance as much as possible. On the other hand, in the power MOSFET, a parasitic bipolar transistor is formed in the source region, the body region, and the drain region due to the device structure of the power section. When used in an inductance load such as switching power supply motor control, energy stored in the inductance during avalanche operation improves the avalanche resistance so that the parasitic bipolar transistor operates and local current flows so that semiconductor elements are not destroyed. Is also desired.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Conventional power MOSFE described in Japanese Patent No. 31090
In T, since the isolation diffusion layer for forming the control portion is formed deeply, the thickness of the epitaxial layer of the current path of the current flowing in the power portion also becomes large, and there is a problem that the on-resistance becomes large. According to the invention described in the publication,
It is described that N + -type high-concentration impurities are diffused into the N-type epitaxial layer in the current path of the power section to reduce the on-resistance. However, the epitaxial layer itself is still thick and is not suitable for further reduction of the on-resistance. Further, the publication does not describe how to improve the avalanche resistance.

By the way, Japanese Patent Laid-Open No. 7-263667 discloses a technique for improving the avalanche resistance. The technique described in the publication will be described with reference to FIG. 7, in which the depth b of the high concentration impurity region 6 is set to be 1/2 or more of the width a of the channel impurity region 3 in which a channel is formed. , An avalanche current generated between the source and drain in an avalanche state is passed through the high-concentration impurity region 6 to the source electrode 11 as it is to suppress the operation of the parasitic bipolar transistor.

However, although it is possible to improve the avalanche resistance by deepening the high-concentration impurity region 6 as in the structure, the substrate 1 is exposed from the bottom of the high-concentration diffusion region 6.
Considering the breakdown voltage up to and including the epitaxial layer 2 between
The minimum effective thickness is required. As a result, ON
The thickness of the epitaxial layer in the path through which the current flows becomes thicker, the on-resistance increases, and another means for newly reducing the on-resistance becomes necessary.

Power MOSF with control circuit function described above
A structure such as ET is often used as a device for high withstand voltage of 100 V or more. As shown in FIG. 8, a general device structure of a power MOSFET with a control circuit function for a low withstand voltage of 100 V or less is, for example, as shown in FIG. High concentration impurity region 6 is formed, a ring-shaped source region 5, a gate electrode 8 and a source electrode 11 are formed around the high concentration impurity region 6, and a P-type well region is formed for control. Is formed to provide a low voltage power MOSFET with a control function. The above-mentioned similar technique is described in, for example, Japanese Patent Laid-Open No. 5-267672.

Power MOS with control function for this low breakdown voltage
Also in the FET, as described above, reducing the on-resistance is an important technical element. JP-A-5-26767 mentioned above
Although not described in Japanese Patent Laid-Open No. 2), the high-concentration impurity region 6 formed in the channel impurity region of the power section is not deeply formed unlike the high breakdown voltage power MOSFET. This is because in a low breakdown voltage device, sufficient breakdown voltage characteristics can be obtained without forming a high concentration impurity region deep.

Therefore, the depth of the channel impurity region can be made as small as possible, the film thickness of the epitaxial layer can be made thin, and the reduction of the on-resistance can be realized. However, the high-concentration impurity region formed in the channel impurity region is formed by diffusing the high-concentration impurity region after forming the channel impurity region. That is, it is difficult to improve the avalanche resistance because the high-concentration impurity regions cannot be formed too deep because the diffusion steps are performed separately.

If the diffusion temperature is raised to diffuse the high-concentration impurity region deeply and diffusion is performed for a long time, the previously diffused channel impurity region is further diffused and the withstand voltage characteristic is deteriorated and the channel length is increased, so that the current characteristic is increased. There is also a problem that makes it worse. Further, in the invention described in the above-mentioned JP-A-5-267672, since the channel impurity region and the well region are formed by the thermal diffusion process of the same impurity, the other diffusion process after the diffusion process is performed. Diffusion in each region remarkably progresses, and as a result, the thickness of the epitaxial layer must be increased, and the on-resistance cannot be reduced.

The present invention has been made in view of the above-mentioned circumstances, and the control section extends the bottom portion of the high-concentration impurity region to the bottom portion of the shallow channel impurity region formed in the power portion. By forming the bottom portion of the formed well region to be shallower than the bottom portions of the channel impurity region and the high concentration impurity region, the overall thickness of the epitaxial layer can be minimized and the on-resistance can be reduced. Another object of the present invention is to provide a power MOS semiconductor device with a control function for improving the avalanche withstanding capability, particularly for low breakdown voltage.

[0013]

The present invention adopts the following configurations and methods in order to solve the above problems. That is,
A semiconductor device of the present invention is a semiconductor substrate of one conductivity type, an epitaxial layer of one conductivity type formed on the semiconductor substrate, and an opposite conductivity type that forms channel regions regularly arranged in the epitaxial layer. A channel impurity region, a high-concentration impurity region formed in the channel impurity region, having a higher concentration than that of the channel impurity region and having an opposite conductivity type, and diffused to substantially the same surface as a bottom surface of the channel impurity region; A reverse conductivity in which a power part including a source region of one conductivity type formed in a ring shape in the channel impurity region and a gate electrode arranged on the channel region, and a control circuit for controlling the power part are formed. The bottom portion of the well region of the mold has a control portion which is substantially the same as or shallower than the bottom portion of the high concentration impurity region.

The method of manufacturing a semiconductor device according to the present invention is
An epitaxial layer of one conductivity type is formed on a semiconductor substrate of one conductivity type, impurities of opposite conductivity type are diffused in the epitaxial layer to form a well region, the well region is formed, and then the epitaxial layer is regularly formed. Reverse conductivity type impurities that will become channel impurity regions forming the channel regions arranged in the above are diffused and high concentration impurity of reverse conductivity type that will become high concentration impurity regions will be diffused in the preliminary diffusion region, The high-concentration impurity is diffused until the bottom surface of the impurity region and the bottom surface of the channel impurity region are substantially flush with the bottom surface of the well region.

As described above, the bottom surface portion of the well region of the opposite conductivity type in which the control portion is formed is substantially the same as the bottom surface portion of the high-concentration impurity region and the bottom surface portion of the channel impurity region formed on substantially the same surface of the power portion. By making the surfaces flush or shallow, the thickness of the epitaxial layer, which is the drain region of the power MOSFET, can be minimized, the on-resistance can be reduced, and the avalanche withstand capability can be improved.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a power MOSFET with a control circuit function according to an embodiment of the present invention. An N − type epitaxial layer 12 is formed on one main surface of the N + type semiconductor substrate 11, and constitutes a part of the drain region 13 of the MOSFET of the power section P. In the drain region 13 of the power part P, shallow P-type channel impurity regions 14 forming a channel are regularly arranged. The channel impurity region 14
A high concentration impurity region 15 having a concentration higher than that of the channel impurity region 14 is formed therein. Channel impurity region 1
The bottom portion of the high-concentration impurity region 15 formed in the trench 4 is formed to be substantially flush with the bottom portion of the shallow channel impurity region 14.

Further, a ring-shaped N + type source region 16 is formed in the channel impurity region 14, and a gate electrode 18 is formed on a region of the channel impurity region 14 which becomes a channel with an insulating layer 17 interposed therebetween. The source region 16 and the channel impurity region 14 are connected to a source electrode 19 which is a metal electrode made of a vapor deposited aluminum film, and a drain electrode 20 which is a metal electrode is formed on the back surface of the semiconductor substrate 11.

On the other hand, in the epitaxial layer 12 of the control section C adjacent to the power section P, a well region 21 in which a P-type impurity having a lower concentration than that of the channel impurity region 14 is diffused is formed. In this well region 21,
For controlling the power part P, for example, an N channel EM
A control circuit including a plurality of elements such as OS and N-channel DMOS is formed to protect the power MOSFET formed in the power section P from overcurrent and overvoltage.

The feature of the present invention resides in that the power portion P
The control part in which the bottom part of the high-concentration impurity region 15 formed in the channel impurity region 14 formed in the above is formed to be substantially flush with the bottom part of the channel impurity region 14, and a control circuit is formed. The bottom surface of the C well region 21 is formed to be substantially the same as or shallower than the bottom surfaces of the channel impurity region 14 and the high concentration impurity region 15.

The bottom surfaces of the impurity regions 14 and 15 of the power portion P are substantially the same plane, and the bottom surface of the well region of the control portion C is substantially the same as the bottom surfaces of both impurity regions 14 and 15, or By forming the power portion P shallower than
And the single epitaxial layer 12 on which the control part C is formed
It is possible to form an epitaxial layer having a minimum film thickness without increasing the thickness of, and it is possible to reduce the on-resistance. Further, the current flowing through the power section P during the avalanche operation flows through the high concentration impurity region 15,
The source region 16 and the high concentration impurity region 15 of the power portion P
The operation of the parasitic bipolar transistor formed of (and the channel impurity region 14) and the drain region 13 can be suppressed, and the avalanche withstand capability can be improved.

The semiconductor device of the above embodiment will be described below in detail based on the manufacturing method. 2 to 6 are sectional views showing a method for manufacturing a semiconductor device of the present invention. First, as shown in FIG. 1, for example, an N + type semiconductor substrate 11
A substrate on which the N − type epitaxial layer 12 is grown is prepared. The surface of the epitaxial layer 12 is thermally oxidized in an oxidizing atmosphere to form an insulating film 17 having a predetermined thickness. After forming the insulating film 17, a resist mask selectively exposed and developed is formed on the insulating film 17, and boron (B) which is a P − -type impurity is injected and diffused into the epitaxial layer 12 to become the control portion C. A P well region 21 is formed. Although the resist mask is used here, for example, the well region 2
If the film thickness of the insulating layer 17 forming 1 is thin, the resist mask is not used.

Here, it is important to make the diffusion concentration of the well region 21 lower than that of the channel impurity region 14 and the high concentration impurity region 15 which will be described later, and perform the thermal diffusion process for a long time to stabilize the well region 21. The progress of diffusion in the well region is suppressed in the subsequent thermal diffusion process. If the well region 21 is not sufficiently diffused in this step, the diffusion of the well region 21 will proceed in the subsequent diffusion steps, and the epitaxial layer 1
2 must be made thicker, and the thickness of the epitaxial layer in the power MOSFET region formed on the common substrate also becomes thicker, which hinders the reduction of the on-resistance and therefore diffuses sufficiently for a long time. This is very important. Further, the depth of the well region 21 is formed so as to be substantially flush with the bottom surfaces of the channel impurity region 14 and the high-concentration impurity region 15 formed in the next step, or to be slightly shallow.

Specifically, for example, boron having a dose energy of 1 × 10 −13 to 3.5 × 10 −13 is implanted with a driving energy of 70 KeV, and at a temperature of about 1100 ° C. to 1200 ° C., about 500 ° C.
Well to 800 minutes to form a well region. The dose amount of the well region 21 is not limited to the above-mentioned specific example, and may be appropriately selected depending on the concentration of the epitaxial layer, that is, the breakdown voltage value to be set.
Vth of the N-channel EMOS formed in 1 is controlled.

After the well region 21 is formed, arsenic (As) which is an N − type impurity for controlling Vth of the N-channel DMOS of the control circuit element is implanted / diffused in the well region 21 to form the Vth control region. 31
To form. Then, polysilicon is deposited on the insulating film 17 by a CVD method or the like, and predetermined photo-etching is performed.
Gate electrodes 18 and 18A are selectively formed on the insulating layer 17. That is, in the power portion P region, the power MOSFET
Of the lateral MOS such as N-channel EMOS and N-channel DMOS is formed in the control section C region.

Next, as shown in FIG. 3, a resist mask A is formed on the surface of the region to be the control portion C, and P-type impurities are implanted. In the power region P region, the gate electrode 18 acts as a mask, boron (B), which is a P-type impurity, is implanted into the surface of the epitaxial layer 12 at a predetermined dose amount, and the first thermal diffusion process under a predetermined temperature condition is performed. An extremely shallow channel impurity region 14 to be a channel region is formed. Specifically, for example, boron having a dose amount of 3 × 10 −13 to 5 × 10 −13 is implanted with an implantation energy of 70 KeV to obtain about 11
The first heat treatment step is performed at 00 ° C. to 1200 ° C. for about 100 to 200 minutes to perform the pre-diffusion channel impurity region 14
To form. In the same step of forming the channel impurity region 14, a P + type impurity may be diffused into the well region 21 as needed.

Next, as shown in FIG. 4, the resist mask A is exposed and developed so as to selectively remain on the surfaces of the gate electrode 18 and the control portion C in the power portion P region. With the width of the resist mask A on the side surface of the gate electrode 18, power MOSFE
The width of the T channel region will be controlled. After forming the resist mask A, P-type boron (B) having a higher concentration than the concentration of the channel impurity region 14 to be the high concentration impurity region 15 is implanted into the exposed surface of the channel impurity region 14. Specifically, for example, the channel impurity region 1
The dose amount of boron (B) of 4 is 3 × 10 −13 to 5 × 10 −.
In the case of 13, boron having a dose energy of 80 KeV and a dose amount of 8 × 10 −14 to 1 × 10 −15 is implanted. Here, what is important is the bottom portion of the channel impurity region 14 formed by the preliminary diffusion performed previously in the second diffusion step described below, and the high-concentration impurity region diffused in the second thermal diffusion step. It is necessary to set the dose amount to be injected into both regions so that the bottom surface of 15 is substantially flush with the surface. In the same step of forming the high-concentration impurity region 15, a P ++-type high-concentration impurity may be diffused into the well region if necessary.

Next, as shown in FIG. 5, after a high-concentration impurity to be the high-concentration impurity region 15 is implanted, a second thermal diffusion process for diffusing the high-concentration impurity is performed. This second diffusion step is performed by using the bottom portion of the high-concentration impurity region 15 and the above-mentioned first diffusion step.
This is performed so that the bottom surface portion of the channel impurity region 14 diffused in the diffusion step is substantially flush with the bottom surface portion. If the bottom of the high-concentration impurity region 15 and the bottom of the channel impurity region 14 are not substantially flush with each other, the following problem occurs. For example, when the bottom of the high-concentration impurity region 15 is formed shallower than the bottom of the channel impurity region 14, the avalanche current flowing during the avalanche operation causes a voltage drop in the channel impurity region serving as the base of the parasitic bipolar transistor. It becomes impossible to further improve the avalanche withstand capability for operating the bipolar transistor.

If the bottom of the high-concentration impurity region 15 is formed deeper than the bottom of the channel impurity region 14, the N − type epitaxial layer 12 immediately thereunder is thinned and the withstand voltage characteristic deteriorates. Therefore, the high concentration impurity region 15
As described above, it is important that the bottom surface of the channel impurity region 14 and the bottom surface of the channel impurity region 14 are substantially flush with each other.

Generally, in the impurity diffusion, the impurity diffusion depth is determined by the impurity concentration, the diffusion temperature, and the diffusion time. Since the impurity concentration of the channel impurity region and the impurity concentration of the high concentration impurity region have the difference in concentration as described above, the diffusion of the high concentration impurity region is faster than the diffusion of the channel impurity region. Therefore, if the concentration of the impurities injected into the high concentration impurity region 15 and the concentration of the impurities injected into the channel impurity region 14 are set in advance, the second concentration is obtained.
By setting the temperature and time of the thermal diffusion step of, the high-concentration impurity region 15 and the channel impurity region 14 are diffused at the same time, and the bottom portion of the high-concentration impurity region 15 and the bottom surface of the channel impurity region 14 in the diffusion proceeding direction. The part and the part can be formed on substantially the same surface.

In the present embodiment, as described above, the dose amount of boron (B), which is the impurity which becomes the channel impurity region 14, is 3 × 10 −13 to 5 × 10 −13, and the dose is about 1100 ° C.
After performing the first preliminary heat treatment step at 1200 ° C. for 100 minutes to 200 minutes, the dose amount of boron (B), which is an impurity to be the high-concentration impurity region 15, is 8 × 10 −14 to 1 × 10 −15.
By performing the second heat treatment step at about 1100 ° C. to 1200 ° C. for about 30 minutes to 90 minutes, as described above, the bottom surface portion of the high concentration impurity region 15 and the bottom surface portion of the channel impurity region 14 are substantially removed. It can be formed on the same surface.

Here, the important thing is, as described above,
Both bottom surface portions of the channel impurity region 14 and the high-concentration impurity region 15 are diffused so as to be substantially the same, and the bottom surface portion of the P-type well region 21 serving as the control portion C is substantially flush with both bottom surface portions. It is to be formed so as to be shallower than both bottom portions. As described above, the well region 21 has a low concentration and is subjected to a diffusion process for a long time to diffuse to near the depths of the channel impurity region 14 and the high concentration impurity region 15 which are designed in advance. Well region 21 having a low concentration in the diffusion process of the region 14 and the high concentration impurity region 15
The diffusion does not proceed, and the bottom portion of the well region 21 can be made substantially flush with both bottom portions. As a result, the thickness of the epitaxial layer 12 can be minimized in the entire region of the substrate, that is, the power portion P region where the power MOSFET is formed and the control portion C region where the control circuit is formed.

Therefore, the channel impurity region 14 is diffused by the two-step diffusion process of the first thermal diffusion process which is the preliminary diffusion and the second thermal diffusion process which diffuses the high concentration impurity region 15, and the channel impurity region 14 is diffused. With the optimum depth, the bottom surfaces of both impurity regions 14 and 15 can be the same, and the bottom surface of the well region of the control portion C can be substantially the same as the bottom surface of both impurity regions. Power MO formed
It is possible to reduce the on-resistance of the SFET and improve the avalanche resistance. The resist mask A formed on the gate electrode 18 and the control portion C is removed after implanting impurities into the high-concentration impurity region, and the above diffusion process is performed.

Next, as shown in FIG. 6, the channel impurity region 14 and the control region C are formed on the region to be the source region of the well region of the control region C so as to expose the channel region of the channel impurity region 14 of the power region P region. A resist mask A is formed, and the resist mask A and the gate electrodes 18, 18A are formed.
The N + -type impurities to be the source regions 16 and 16A are implanted and diffused into the exposed channel impurity region 14 and the well region by using the and. As the N-type impurity that becomes the source region 16, phosphorus (P), arsenic (As), or the like can be used,
Here, arsenic (As) with a dose amount of 5 × 10 −15 to 1 × 10 −16 is implanted with an implantation energy of 100 to 150 KeV, and a thermal diffusion process is performed at about 900 ° C. to 1100 ° C. for about 30 minutes to 60 minutes. The source regions 16 and 16A are formed.

After forming the source regions 16 and 16A, an insulating layer 17 such as SiO 2 is deposited on the surfaces of the gate electrodes 18 and 18A by atmospheric pressure or low pressure CVD method and photoetched to form the insulating layers 17 on the surfaces of the gate electrodes 18 and 18A. To cover. Then, a source electrode 19 commonly connected to the source region 16 formed in the power region P region is formed by sputtering or vapor deposition of an aluminum film on the exposed surface, and the source and drain electrodes 22 of the MOS formed in the control region C region are formed. 23 is formed. Further, a power MOSF is provided on the back surface of the semiconductor substrate 11.
A metal layer to be the drain electrode 20 of the ET is formed, and the power MOSFET with a control circuit function shown in FIG. 1 is completed.

In the above description, the power MOS formed in the power region-P region is an N-channel type, but it goes without saying that the present invention is similarly applied to a P-type channel power MOSFET.

[0036]

As described above in detail, according to the present invention, the bottom portion of the well region of the opposite conductivity type in which the control portion is formed is the high concentration impurity region formed on the substantially same surface of the power portion. By making the bottom surface and the bottom surface of the channel impurity region substantially flush or shallow, the thickness of the epitaxial layer, which is the drain region of the power MOSFET, can be minimized to reduce the on-resistance and improve the avalanche withstand capability. Power MO with highly reliable control circuit function
An SFET can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 7 is a sectional view showing a conventional semiconductor device.

FIG. 8 is a sectional view showing a conventional semiconductor device.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Aki Ariyama 2-5-5 Keihan Hon-dori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (56) Reference JP-A-8-204175 (JP, A) Kai 64-48464 (JP, A) JP 4-180238 (JP, A) JP 2-58371 (JP, A) JP 5-267672 (JP, A) JP 5-283628 ( JP, A) Tokuheiyo Hyo 6-508958 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (4)

(57) [Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of one conductivity type formed on the semiconductor substrate, and a channel impurity of an opposite conductivity type that forms regularly arranged channel regions in the epitaxial layer. A region, a high-concentration impurity region formed in the channel impurity region, having a higher concentration than that of the channel impurity region and having an opposite conductivity type, and a high-concentration impurity region diffused to substantially the same plane as the bottom surface of the channel impurity region;
A power part including a source region of one conductivity type formed in a ring shape in the channel impurity region and a gate electrode arranged on the channel region, and a control circuit for controlling the power part are formed in reverse. The bottom of the conductivity type well region is formed to have substantially the same depth as the bottom of the high concentration impurity region.
The semiconductor device is characterized in that a control unit formed so that. 2. A semiconductor device according to claim 1, wherein the bottom portion of the high impurity concentration region and bottom portion of the channel impurity regions are substantially coplanar. 3. An epitaxial layer of one conductivity type is formed on a semiconductor substrate of one conductivity type, an impurity of opposite conductivity type is diffused into the epitaxial layer to form a well region, and the well region is formed, and then the well region is formed. Reverse-conductivity type impurities that will become channel impurity regions that form regularly arranged channel regions in the epitaxial layer are pre-diffused, and reverse-conductivity high concentration impurities that will become high concentration impurity regions are diffused in the preliminary diffusion regions. Then, the method of manufacturing a semiconductor device, wherein the high-concentration impurity is diffused until the bottom of the high-concentration impurity region and the bottom of the channel impurity region are substantially flush with the bottom of the well region. . 4. The method of manufacturing a semiconductor device according to claim 3 , wherein a bottom surface of the channel impurity region and a bottom surface of the high-concentration impurity region are formed to be substantially flush with each other.