JP3377858B2 - Clock recovery circuit and demodulator using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit and a demodulator using the same, and more particularly to a clock recovery circuit capable of high-speed acquisition for synchronously detecting a phase-modulated wave and a demodulator using the same. Regarding

[0002]

2. Description of the Related Art In recent years, digital mobile communications have been actively developed, and they adopt the TDMA system. Therefore, the demodulator provided in such a digital mobile communication terminal needs to instantaneously pull in the burst signal.

On the other hand, in mobile communication, a differential detection method, which is generally less deteriorated by fading, is adopted. Recently, however, a synchronous detection method (carrier recovery method), which is excellent in anti-fading characteristics, is drawing attention.

However, the clock recovery circuit of the demodulator adopting the synchronous detection system has a very disadvantageous condition in terms of high-speed pull-in.

That is, in TDMA communication, a redundant bit (preamble) is added for pulling in a burst signal. For example, since synchronous detection is generally used in satellite communication, data of all 0s or 1s continues for several tens of bits as a preamble for carrier (reproduction of carrier wave), and for clock reproduction, for example, in case of QPSK, several tens of bits of 1001 pattern are added. Has been done.

Therefore, for the above reason, in the satellite communication, the carrier recovery circuit and the clock recovery circuit can be easily pulled in this order.

On the other hand, in mobile communication, for example, the standard STD
In some cases, the preamble of 1001 patterns is only added with tens of bits as specified by -27, 28 and the like. In such a case, unlike satellite communication, carrier reproduction and clock reproduction must be performed simultaneously using only this preamble.

However, since the carrier frequency error is large at the beginning of the burst, the clock cannot be easily reproduced, and since the clock is not reproduced, the preamble 100 is not reproduced.
A vicious cycle occurs in which the carrier cannot be easily reproduced for one pattern.

Conventionally, that is, in the clock recovery circuit of the demodulator adopting the differential detection method, since the error of the carrier frequency of the input signal is canceled by the differential detection, such a problem has not been emphasized. On the other hand, when the synchronous detection method is adopted, it becomes a big problem.

FIG. 5 shows a configuration example of a conventional demodulator using synchronous detection. In the figure, reference numeral 4 denotes a quadrature detector, which detects a quadrature-phase modulated signal with a carrier frequency from a voltage controlled oscillator 90 and outputs a quadrature detection signal having an I component and a Q component.

Each of the I component and the Q component of the quadrature detection signal is passed through the low pass filters 50 and 51, and the A / D conversion circuit 6 is provided.
Input 0 and 61. The A / D conversion circuits 60 and 61 convert the I component and Q component of the quadrature detection signal into digital signals in synchronization with the clock output of the clock recovery circuit 10.

Further, in the circuit 7, the A / D conversion circuit 6
The tan ⁻¹ (θ / I) is calculated from the I and Q components converted into digital signals by 0 and 61, and the phase detection signal θ (t) is output.

Next, digital data of I component and Q component is detected from the phase detection signal θ (t) in the data judging circuit 8.

On the other hand, the carrier wave is reproduced by the carrier wave reproducing circuit 9 based on the phase detection signal θ (t). Further, the output of the carrier recovery circuit 9 controls the oscillation frequency of the voltage controlled oscillator 90. The output of the voltage controlled oscillator 90 is input to the quadrature detector 4.

Here, the clock recovery circuit 10 is composed of a change point extraction circuit 2 for detecting a change point of the phase detection signal θ (t) and a digital PLL 3, and as described above, the phase detection signal θ (t) is obtained. Has a carrier frequency error, and it is difficult to pull in the clock at high speed.

[0016]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a clock recovery circuit which can solve the conventional problems and which can be pulled in at a high speed.

A further object of the present invention is to provide a clock recovery circuit which enables high speed clock recovery in the initial pull-in state where the carrier frequency error is large.

It is another object of the present invention to provide a demodulator using the clock reproduction circuit which enables the high speed reproduction of the clock.

Still another object of the present invention is to provide a demodulator which has a simplified structure and uses the clock recovery circuit capable of high-speed clock recovery, which has a simplified structure.

It is another object of the present invention to provide a demodulator having a simplified configuration, in which the output of the differential decoding circuit is used as the input of the clock recovery circuit for the signal in which the differential code is phase-modulated. .

[0021]

A clock recovery circuit according to the present invention inputs a phase-detected signal θ (t) and outputs the signal θ (t) and a signal θ (t-Ts) one symbol before. Difference Δθ
A difference circuit that outputs (t), a change point detection circuit that detects a change point of the output of this difference circuit, and a reproduction clock signal that is synchronized with the difference Δθ (t) based on the output of the change point detection circuit. It is configured by a digital PLL circuit that operates.

Further, the demodulator according to the present invention is a quadrature detector for inputting a quadrature-phase modulated signal and outputting a quadrature detection signal having I and Q components, and a clock recovery circuit according to the present invention. In synchronization with the clock output of
An A / D conversion circuit for converting the I component and Q component of the quadrature detection signal into a digital signal, and the I and Q components converted into digital signals by this A / D conversion circuit tan ^-1
A circuit that calculates (θ / I) and outputs the phase detection signal θ (t), a data determination circuit that detects I component and Q component data from the phase detection signal θ (t), and a phase detection signal θ (t)
And a voltage-controlled oscillator whose oscillation frequency is controlled by this output. Further, the output of the voltage-controlled oscillator is input to the quadrature detector.

In one aspect of the demodulator according to the present invention, a quadrature-phase modulated signal is input, and a quadrature detection signal having an I component and a Q component is output by the output of a fixed oscillator having a carrier frequency. A / D for converting the I and Q components of the quadrature detection signal into digital signals in synchronization with the quasi-synchronous detector and the clock output of the clock recovery circuit
A conversion circuit, a circuit that calculates tan ^-1 (θ / I) from the I and Q components converted into digital signals by this A / D conversion circuit, and outputs a phase detection signal θ (t), and a phase The phase detection signal θ (t) has a data determination circuit for detecting I component data and Q component data from the detection signal θ (t) and a carrier recovery circuit for reproducing a carrier wave from the phase detection signal θ (t). ) To a circuit for subtracting the carrier wave reproduced by the carrier wave reproduction circuit between the circuit for outputting the phase detection signal θ (t) and the data determination circuit.

Furthermore, the demodulator according to the present invention has, as one aspect thereof, a quadrature detector which inputs a signal obtained by quadrature phase modulating a differential code and outputs a quadrature detection signal having an I component and a Q component, Tan ^-1 (θ / I) is calculated from the A / D conversion circuit that converts the I and Q components of the quadrature detection signal into a digital signal, and the I and Q components that are converted into digital signals by the A / D conversion circuit. Then, the phase detection signal θ
A circuit for outputting (t) and the phase detection signal θ (t) are input, and the phase detection signal θ (t) and the signal θ (tT
s) and a differential decoding circuit that outputs a difference Δθ (t), a data determination circuit that detects I component and Q component data based on the output of the differential decoding circuit, and an output of the differential decoding circuit. Change point detection circuit for detecting the change point and a digital PLL that outputs a reproduction clock signal synchronized with the difference Δθ (t) based on the output of the change point detection circuit and sends the clock signal to the A / D conversion circuit. It has a circuit, a carrier wave regeneration circuit that regenerates a carrier wave by inputting the phase detection signal θ (t), and a voltage-controlled oscillator whose oscillation frequency is controlled by the output of this carrier wave regeneration circuit. It has a carrier wave reproducing circuit for reproducing a carrier wave and a voltage controlled oscillator whose oscillation frequency is controlled by the output of the carrier wave reproducing circuit.
The output of the voltage controlled oscillator is configured to be input to the quadrature detector.

[0025]

As described above, in the present invention, the clock recovery circuit inputs the phase-detected signal θ (t) and outputs the signal θ (t).
The differential circuit outputs a difference Δθ (t) between (t) and the signal θ (t-Ts) one symbol before.

That is, in this difference circuit, if the phase-detected signal is θ (t), then θ (t) = 2πΔft + ψ (t) (1) where 2πΔft: frequency error, ψ (t): It is information.

This and the signal θ (t-Ts) one symbol before θ (t-Ts) = 2πΔf (t-Ts) + ψ (t-Ts) (2) The difference Δθ (t) is calculated as follows.             Δθ (t) = 2πΔft-2πΔ f (t-Ts) + ψ (t) − ψ (t-Ts)                     = 2πΔfTs + ψ (Ts)                     = 2πΔf / fs + ψ (Ts) (3)

In this way, the carrier frequency error which hinders the clock reproduction is calculated by taking the difference, and thus 2πΔf / fs
Since it is sufficiently small, the clock can be easily reproduced.

[0029]

1 is a block diagram of an embodiment of a clock recovery circuit of the present invention. In the figure, 1 is a difference circuit,
A delay circuit 11 for one symbol and an addition circuit 12 are provided.

Θ (t) is input to the phase-detected signal,
This and the delay circuit 11 delays one symbol by θ (tT
The polarity of (s) is inverted and added by the adder circuit 12. Therefore, the difference Δθ (t) is calculated and output as shown in the above equation (3).

This difference Δθ (t) is input to the change point extraction circuit 2. The change point extraction circuit 2 outputs 0 and “10” when the difference input signals are “11” and “00”, for example.
Alternatively, when "01", the output is 1. That is, the exclusive OR of the differential input signals is output. This indicates that the differential input signal is changing.

The output of the change point extraction circuit 2 is further led to the digital PLL 3. In the digital PLL 3, the input is input to the phase comparison circuit 30. The phase comparison circuit 30 takes the difference between the input phase and the phase of the oscillation frequency signal of the oscillator 32 divided by the frequency dividing circuit 33, and outputs the difference.

The output of the phase comparison circuit 30 is input to the loop filter 31 composed of a low frequency filter. Here, the carrier frequency component and its harmonic components are blocked,
Is output.

The output of the loop filter 31 is the frequency divider 33.
The frequency division ratio of the oscillation frequency signal of the oscillator 32 is controlled according to the output level. The output of the frequency divider 33 is input to the phase comparison circuit 30 and also output as a reproduction cook signal.

The clock regenerating circuit according to the present invention having the above-mentioned configuration can regenerate the clock by reducing the carrier frequency error.

FIG. 2 shows the clock recovery circuit 10 of FIG.
FIG. 3 is a block diagram of a configuration example of a demodulator using The configuration of the embodiment shown in FIG. 2 is a configuration for feeding back the reproduced carrier to the quadrature detector 4, similarly to the conventional demodulator shown in FIG. The different point is characterized in that the clock reproduction circuit 10 according to the present invention of FIG. 1 is used as the clock reproduction circuit 10.

The other structure is similar to that of the circuit of FIG. Therefore, the description of the operation again will be omitted here.

The clock recovery circuit 10 of the present invention applied to this embodiment is provided with the differential circuit 1 according to the principle of the present invention. As a result, the carrier frequency error is reduced, so that the clock recovery circuit 10 can be pulled in at high speed.

Therefore, it is possible to convert the I and Q components into digital signals at the correct clock timing in the A / D converters 60 and 61.

FIG. 3 further shows a clock recovery circuit 1 of the present invention.
It is a block diagram of a configuration example of a demodulator using 0. The feature of this embodiment is that the quadrature detector 4 is a quasi-coherent detector 41, and the quasi-coherent detection is performed to reproduce the carrier signal in the baseband section.

That is, the phase detection signal θ (t) is quasi-coherently detected by the reference frequency from the reference frequency oscillator 40. Further, in the carrier wave reproducing circuit 9, the carrier wave signal is reproduced from the phase detection signal θ (t) which is the base band signal, and the carrier component is removed by the adding circuit 91.

Further, in this embodiment, in comparison with the embodiment of FIG. 2, the output of the carrier recovery circuit 9 controls the voltage controlled oscillator 90, which is not shown in FIG.
Since the / A converter is not required, the structure is simple.

Further, in the present embodiment as well as in the previous embodiment, the clock recovery circuit 10 can be pulled in at high speed by removing the carrier frequency error by the difference circuit 1.

FIG. 4 shows still another embodiment according to the present invention, in particular, an application example in the case where a differential coded signal specified in the regulations STD-27 and 28 is transmitted.

If the information signal is differentially encoded,
It is necessary to differentially decode the original information on the receiving side. This differential decoding is just finding the difference between the received signals.

Therefore, in FIG. 4, the decoded output from the differential decoding circuit 1, that is, the difference between the received signals is guided to the change point extraction circuit 2 of the clock recovery circuit 10.
Therefore, in this embodiment, in the clock recovery circuit 10,
The difference circuit is omitted, and is composed only of the change point extraction circuit 2 and the digital PLL 3.

[0047]

As described above according to the embodiments,
Since the carrier frequency error is reduced by the difference circuit,
In the demodulator using the synchronous detection method, the use of the present invention facilitates high-speed pulling of the clock recovery circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a clock recovery circuit of the present invention.

FIG. 2 is a block diagram of a configuration example (No. 1) of a demodulator using the clock recovery circuit of the present invention.

FIG. 3 is a block diagram of a configuration example (No. 2) of a demodulator using the clock recovery circuit of the present invention.

FIG. 4 is a block diagram of a configuration example of a demodulator of the present invention for differentially encoded signals.

FIG. 5 is a block diagram of a configuration example of a conventional demodulator.

[Explanation of symbols]

1 differential circuit, differential decoding circuit 2 change point extraction circuit 3 digital PLL 4 quadrature detector 50, 51 low-pass filter 60, 61 A / D converter 7 tan ^-1 (θ / I) circuit 8 data determination circuit 9 carrier recovery circuit 10 clock recovery circuit 11 1 symbol delay circuit 12 addition circuit 30 phase comparison circuit 31 loop filter 32 oscillator 33 frequency divider

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-6-30063 (JP, A) JP-A-5-48666 (JP, A) JP-A-6-152673 (JP, A) JP-A-63- 252014 (JP, A) JP 61-274458 (JP, A) JP 64-12646 (JP, A) Yuri Yamamoto, A study on π / 4 shift QPSK base band delay detector, 1992 Electronic Information IEICE Spring Conference, Volume 2, 1992, 2-342 Koji Matsuyama, π / 4 shift QPSK demodulator for microcell mobile communications, 1992 IEICE Spring Conference, Volume 2, 1992, 2-343 (58) ) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 27/22 H04L 7/033

Claims (2)

(57) [Claims] 1. A quadrature carrier is input by inputting a quadrature phase modulated signal.
Due to the output of the fixed wave number oscillator,
A quasi-synchronous detector that outputs a quadrature detection signal that outputs a digital signal
A / D conversion circuit for converting to I and a digital signal converted by the A / D conversion circuit
Tan-1 (θ / I) is calculated from the component and the Q component, and the phase
A circuit for outputting the detection signal θ (t), a circuit for subtracting the carrier from the phase detection signal θ (t) , and a circuit for re-generating the carrier from the phase detection signal θ (t) with the carrier subtracted.
Carrier recovery circuit that returns to the circuit that reduces the carrier wave
Path and the I component from the phase detection signal θ (t) obtained by subtracting the carrier wave and
A data judgment circuit for detecting the data of the Q component and the phase detection signal θ (t) with the carrier wave subtracted are input and
Applied phase detection signal θ (t) and signal one symbol before θ (t-
Difference circuit that outputs a difference Δθ (t) from Ts), and the difference circuit
Change point detection circuit for detecting the change point of the output of the
Based on the output of the point detection circuit, it is synchronized with the difference Δθ (t).
And a digital PLL circuit for outputting a reproduced clock signal
And a clock recovery circuit configured to include the clock recovery circuit from the clock recovery circuit.
I component of the quadrature detection signal in synchronization with the raw clock signal
And it is characterized by converting the Q component to a digital signal
Demodulator. 2. A signal obtained by quadrature phase modulating a differential code is input.
And quadrature detection having I and Q components depending on the carrier wave
Quadrature detector for outputting the signal and a digital signal for the I and Q components of the quadrature detection signal
A / D conversion circuit for converting to I and a digital signal converted by the A / D conversion circuit
Tan-1 (θ / I) is calculated from the component and the Q component, and the phase
A circuit that outputs the detection signal θ (t) and the phase detection signal θ (t) are input, and the phase detection signal θ (t) is input.
(t) and 1 symbol before the signal θ a (t-Ts) and the difference Δθ of (t)
Based on the output of the differential decoding circuit and the output of the differential decoding circuit , the I component and the Q component are decoded.
Data detection circuit for detecting data, and change point detection for detecting change point of output of the differential decoding circuit
Circuit, and the difference based on the output of the change point detection circuit.
Digit that outputs the recovered clock signal synchronized with Δθ (t)
Clock recovery circuit configured with a digital PLL circuit
And a carrier for reproducing the carrier by inputting the phase detection signal θ (t).
And transmitting reproduction circuit, the oscillation frequency is controlled by the output of the carrier recovery circuit
A voltage controlled oscillator, wherein the A / D conversion circuit outputs from the clock recovery circuit
The quadrature detection signal in synchronization with the reproduced clock signal
Of the voltage-controlled oscillator is converted into a digital signal, and the output of the voltage-controlled oscillator is fed to the quadrature detector.
A demodulator characterized by being input as a carrier wave.