JP3366613B2 - Active matrix display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active electro-optical device, and more particularly to an image display method for an active liquid crystal electro-optical device. According to the present invention, a voltage (analog signal) whose magnitude changes with time is applied to one input terminal of an active element, and a control signal voltage (digital signal) is applied to another input terminal at an arbitrary timing. By generating an arbitrary voltage from the output terminal,
The present invention relates to an analog / digital gradation image display method capable of setting a clear gradation level in an electro-optical device.

[0002]

2. Description of the Related Art Liquid crystal compositions have different dielectric constants in the horizontal and vertical directions with respect to the molecular axis because of their material properties. Therefore, liquid crystal compositions may be aligned horizontally or vertically with respect to an external electric field. It can be done easily. The liquid crystal electro-optical device utilizes this anisotropy of the dielectric constant to control the amount of transmitted light or the amount of dispersion of light, thereby performing ON / OFF display.

FIG. 3 shows electro-optical characteristics of a nematic liquid crystal which is a typical liquid crystal material. Small applied voltage V
At a (point A), the transmitted light amount is almost 0%, at Vb (point B) is about 20%, at Vc (point C) is about 70%, and at Vd (point D).
Then, the transmitted light amount changes with the voltage, such as 100%. In other words, if only points A and D are used, black and white 2
If the gradation display uses the rising portion of the electro-optical characteristics such as points B and C, intermediate gradation display can be performed.

Conventionally, in the case of gradation display of a liquid crystal electro-optical device using a TFT, in an active matrix type liquid crystal electro-optical device, a thin film transistor (TFT) is used as an active element, and a gate applied voltage of the TFT or between a source and a drain is used. The voltage applied to the liquid crystal was changed in an analog manner to adjust the voltage applied to the liquid crystal, and gradation display was performed.

[0005]

However, when actually manufacturing such a liquid crystal electro-optical device, a TFT is formed.
In the conventional gradation display method, 16 gradations are the limit. Therefore, a completely new gradation method was required.

[0006]

Therefore, in the present invention, in order to clarify the liquid crystal applied voltage level, an uncertain analog value as in the prior art is not applied to the gate or the source / drain, but is kept constant. A universal voltage that changes with time is repeated between the source and drain, and the image information signal is transformed into a digital pulse and applied to the gate at an appropriate timing to apply the desired voltage to the liquid crystal. It is characterized by utilizing a completely innovative image display method of applying a voltage.

FIG. 2 shows an example of an active matrix circuit of a liquid crystal display device necessary for implementing the present invention.
In the present invention, the active element is required to respond in a short time of 100 nsec or less, so that it is necessary to build a circuit that operates at high speed. For that purpose, switching is not performed only by the conventional N-channel type thin film transistor (NTFT) or P-type thin film transistor (PTFT), but as shown in FIG.
It is necessary to use a modified transfer gate type circuit configuration in which T is configured to operate in a complementary manner.

In this example, a matrix of N rows and M columns is formed, but in order to avoid complexity, FIG. 2 shows only the vicinity of the elements of n rows and m columns of the matrix. , If you expand the same thing up, down, left and right, you can get the perfect one.

As shown in the figure, four modified transfer gates are drawn, but the source of each modified transfer gate is connected to Y _m or Y _{m + 1} (hereinafter, collectively referred to as Y line), Further, the gate of the modified transfer gate is connected to X _n or X _{n + 1} (hereinafter collectively referred to as X-ray). Also, transformation transfer
The drain of the gate is a liquid crystal pixel Z _{n, m} , Z _{n, m + 1} , Z
It is connected to _{n + 1, m} and Z _{n + 1, m + 1} . In the modified Tonsfer Gate, NTFT and PTFT are symmetrical, so their positions may be interchanged.

Next, an operation example of the circuit using such a circuit will be described with reference to FIG. Hereinafter, V _Ym and V _Xn mean potentials applied to Y _m and X _n , respectively,
Further, V _{Zn, m} means the potential of the liquid crystal pixel Z _{n, m} shown in FIG. 2 on the TFT side. For simplicity, if the potential of the counter electrode of the liquid crystal pixel is 0 V, V _{Zn, m} is
It means a voltage applied to a liquid crystal pixel.

First, a half wave of a sine wave as shown in FIG. 1 is applied to the Y ₁ line. Then, while the sine wave continues, a pulse signal (hereinafter referred to as a bipolar pulse) whose polarity is inverted is intentionally applied to each X-ray at arbitrary timing, as shown in the figure. It

At this time, the liquid crystal pixels Z _{n, m} , Z _{n, m + 1} , Z
_{Focusing on n + 1, m} and Z _{n + 1, m + 1} , it can be seen that no voltage is applied to any pixel. This voltage also Y _{m + 1} to Y _m is because not supplied. At this stage, the pixels to which some voltage may be applied are the pixels in the first column, namely Z ₁₁ , Z ₂₁ , _.. Z _N1 . Then, a similar half-wave is applied to Y ₂ , and a bipolar pulse is applied to each X-ray. At this time, a voltage is applied to the pixels in the second column, and an image in the second column is obtained.

In this way, the voltages are sequentially applied,
Eventually, a voltage is applied to Y _m . Then, again, the bipolar pulse is applied to the X-ray. At this time, the timing (starting time) of the pulse applied to each X-ray is not the same. For example, a pulse is applied to X _{n + 1} earlier than X _n . The voltage of the Y line when the pulse is applied is the output voltage of the modified transfer gate, which charges the capacitor of the liquid crystal pixel. As a result, the voltage of pixel Z _{n + 1, m} is
smaller than that of _nm . Here, the time required to charge the capacitor of the liquid crystal pixel is neglected.
The time constant of the FT and the capacitor is at most several nsec, while the width of the bipolar pulse is several hundreds.
Since it is nsec, it can be sufficiently ignored.

Next, a sine wave voltage is applied to Y _{m + 1} . Then, again, the bipolar pulse is applied to the X-ray. At this time, if attention is paid to the pixels Z _nm and Z _{n + 1, m} , the charges accumulated therein are discharged. This is because no voltage is applied to Y _m , but a voltage is applied to the gate, and at the moment when the voltage is applied, the charge leaks from the liquid crystal pixel through Y _m . On the other hand, in the case, Y m _{+ 1} pixel Z _n as shown in FIG. Since the voltage is applied _{to, m + 1} and the charge on Z _{n + 1, m + 1} are accumulated.

In this way, the voltage is sequentially applied to Y _M , and one screen (also called a frame) is formed. At this time, it should be noted that the images are displayed in a so-called dynamic mode in which the image appears in each column in sequence and then disappears when the image in the next column appears. However, it is possible to prevent the loss of charge, for example by connecting a diode in series with the transfer gate, and consequently into a static mode, such as a normal active matrix. Also, for example, in parallel with the liquid crystal pixel,
It is also possible to hold a charge of the liquid crystal pixel by connecting a capacitor made of a ferroelectric substance and utilizing the hysteresis of the electrostatic characteristic of the ferroelectric substance.

As has been clarified in the above example, gradation display can be performed, but the accuracy of gradation is obtained by dividing the time width of the signal voltage applied to the Y line by the width of the bipolar pulse. It is considered to be about the same. Of course, strictly speaking, the non-linearity of the electric characteristics of the liquid crystal must be taken into consideration as shown in FIG. The time required to form one screen is usually about 30 msec. In the example of FIG. 1, the time is the time from the application of the voltage to Y ₁ to the application of the voltage to Y _M and the application of the voltage to Y ₁ again. In the case of a display device having a screen time of 30 msec and M = 480, that is, a display device having 480 lines, the bipolar pulse must be 250 nsec to achieve 256 gray levels. At this time, the voltage continues to the liquid crystal for several tens of seconds.

[0017]

[Embodiment 1] In this embodiment, a wall-mounted television is manufactured by using a liquid crystal display device having a circuit configuration as shown in FIG. Also TF at that time
T is polycrystalline silicon using laser annealing.

FIG. 4 shows the actual arrangement of electrodes and the like corresponding to this circuit structure for one pixel. First, a method for manufacturing a liquid crystal panel used in this example will be described with reference to FIGS. In FIG. 5A, a magnetron RF (high frequency) is formed on a glass 50 such as quartz glass which can withstand a heat treatment at 700 ° C. or less, for example, about 600 ° C., which is not expensive.
A silicon oxide film as the blocking layer 51 is formed to a thickness of 1000 to 3000 Å by using the sputtering method. Process conditions are 100% oxygen atmosphere, film formation temperature 15 ° C., output 4
The pressure was set to 00 to 800 W and the pressure was set to 0.5 Pa. The deposition rate using quartz or single crystal silicon for the target is 30 to 1
It was 00Å / min.

A silicon film 52 was formed on this by a plasma CVD method. The film forming temperature is 250 ° C. to 35
The temperature is set to 0 ° C., and in this embodiment, the temperature is set to 320 ° C. and monosilane (SiH
₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (Si ₂
H ₆ ) Alternatively, trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD device at a pressure of 3 Pa, and 13.56M
A high frequency power of Hz was applied to form a film. At this time, the high frequency power is suitably 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the film formation rate at that time was about 120 Å / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be approximately the same, boron is used in an amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm by using diborane.
^-3 may be added during film formation. Further, not only the plasma CVD but also the sputtering method or the low pressure CVD method may be used for forming the silicon layer to be the channel region of the TFT. The method will be briefly described below.

In the case of the sputtering method, the back pressure before sputtering was set to 1 × 10 ^-5 Pa or less, the single crystal silicon was used as the target, and the atmosphere was mixed with hydrogen of 20 to 80% in argon. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When formed by a reduced pressure vapor phase method, the temperature is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 5
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The film forming rate was 50 to 250 Å / min. In order to control the threshold voltage (Vth) of the PTFT and that of the NTFT to be approximately the same, boron may be added during film formation using diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. .

The coating formed by these methods is
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration is 7 × 10 ¹⁹ cm ^-3 or less,
It is preferable that the size is 1 × 10 ¹⁹ cm ^-3 or less,
If the amount is too small, the leak current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, it is difficult to crystallize, and the laser annealing temperature must be high or the laser annealing time must be long. Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon is 4 × 10 ²²
It was 1 atom% when compared as cm ^-3 .

In order to further promote crystallization of the source and drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ^-3 or less, preferably 1 × 10 ¹⁹ cm ^-3 or less, and the TF for forming a pixel is set.
Oxygen may be added only to the channel forming region of T by the ion implantation method so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .

By the above method, a silicon film in an amorphous state was formed to a thickness of 500 to 5000 Å, 1000 Å in this embodiment.

Then, as shown in FIG. 5B, a pattern was formed in the photoresist 53 by using the mask P1 to open only the source / drain regions. A silicon film 54, which will be an n-type active layer, was formed thereon by a plasma CVD method. The film formation temperature is 250 ° C. to 350 ° C., and in this embodiment, it is 320 ° C., and monosilane (SiH ₄ ) and monosilane-based phosphine (PH ₃ ) having a concentration of 3% were used. These are introduced into the PCVD apparatus at a pressure of 5 Pa, and 13.56
A high frequency power of MHz was applied to form a film. At this time, the high-frequency power is suitably 0.05~0.20W / cm ^2, in this embodiment using 0.120W / cm ^2.

The specific conductivity of the n-type silicon layer produced by this method was about 2 × 10 ^-1 [Ωcm ^-1 ]. The film thickness was 50Å. After that, the lift-off method is used to remove the resist 53, and the source / drain regions 5 are removed.
5, 56 were formed.

A p-type active layer was formed using the same process. The gas introduced at this time was a monosilane (SiH ₄ ) and monosilane-based diborane (B ₂ H ₆ ) concentration of 5%. These were introduced into a PCVD device at a pressure of 4 Pa, and high frequency power of 13.56 MHz was applied to form a film.
At this time, the high-frequency power is suitably 0.05~0.20W / cm ^2, in this embodiment using 0.120W / cm ^2. The specific conductivity of the p-type silicon layer produced by this method was about 5 × 10 ^-2 [Ωcm ^-1 ]. The film thickness was 50Å. After that, the source / drain regions 59 and 60 were formed by using the lift-off method similarly to the N-type region.
Then, the silicon film 52 was removed by etching using the mask P3 to form an N-channel type thin film transistor island region 63 and a P-channel type thin film transistor island region 64.

After that, the source / drain / channel regions were laser-annealed using a XeCl excimer laser, and at the same time, laser doping was performed on the active layer. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 for melting the entire film thickness.
mJ / cm ² is required. However, 220m from the beginning
When the energy of J / cm ² or more is applied, hydrogen contained in the film is rapidly released, so that the film is broken. Therefore, it is necessary to first drive out hydrogen with low energy and then melt it. In this embodiment, first 150 m
After ejecting hydrogen at J / cm ² , 230mJ
Crystallization was performed at / cm ² .

The annealing causes the silicon film to shift from an amorphous structure to a highly ordered state, and a part thereof exhibits a crystalline state. In particular, a region having a relatively high degree of ordering after the film formation of silicon tends to be crystallized and become a crystalline state. However, since silicon existing between these regions is bonded to each other, the silicon members pull each other. Peak 522 of single crystal silicon as measured by laser Raman spectroscopy
Peaks shifted to lower frequencies than cm ^-1 are observed. The apparent particle size is 50 to 5 when calculated from the full width at half maximum.
Although it is 00 Å, in reality there are many regions with high crystallinity and they have a cluster structure, and it was possible to form a film with a structure in which the clusters are mutually anchored (anchoring) between silicon clusters. .

As a result, the film exhibits a state in which it can be said that it is substantially free of grain boundaries (hereinafter referred to as GB). Since the carriers can easily move between the clusters through the anchored portions, the carrier mobility is higher than that of polycrystalline silicon in which so-called GB is clearly present. That is, hole mobility (μh) = 10 to ²⁰⁰ cm ² /
VSec, electron mobility (μe) = 15 to 300 cm ² / V
Sec is obtained.

A silicon oxide film was formed thereon as a gate insulating film to a thickness of 500 to 2000Å, for example, 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of fluorine may be added to immobilize sodium ions.

After this, 1-5 × 10 ²¹ cm of phosphorus is placed on the upper side.
^-3 concentration silicon film or this silicon film with molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned with a fourth photomask P4 to obtain FIG. 7 (E). A gate electrode 66 for NTFT and a gate electrode 67 for PTFT were formed. For example, the channel length is 7 μm, the gate electrode is 0.2 μm of phosphorus-doped silicon, and 0.3 molybdenum is formed thereon.
It was formed to a thickness of μm.

When aluminum (Al) is used as the gate electrode material, the self-alignment method can be applied by patterning this with the fourth photomask 69 and then anodizing the surface. Since the source / drain contact holes can be formed at positions closer to the gate, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

In this way, a C / TFT can be manufactured without applying a temperature above 400 ° C. in all steps. Therefore, an expensive substrate such as quartz does not have to be used as the substrate material, and it can be said that the process is extremely suitable for the large-screen liquid crystal display device of the present invention.

In FIG. 5F, the inter-layer insulator 68 was formed as a silicon oxide film by the above-mentioned sputtering method. This silicon oxide film is formed by LPCVD method, photo CVD method.
Method, atmospheric pressure CVD method may be used. For example, 0.2-0.
Formed to a thickness of 6 μm, and then a fifth photomask P
5 was used to form the window 79 for the electrode. After that, aluminum is further formed on the entire surface to a thickness of 0.3 μm by a sputtering method, and a lead 74 and contacts 73 and 75 are formed using a sixth photomask P6.
An organic resin 77 for flattening the surface, for example, a translucent polyimide resin was applied and formed, and the electrode hole was formed again using the seventh photomask P7. Further, ITO (Indium Tin Oxide) was formed on the whole of these by a sputtering method to a thickness of 0.1 μm, and the pixel electrode 71 was formed using the eighth photomask P8. This ITO film is formed at room temperature to 150 ° C.
Fulfilled by oxygen at 0-400 ° C or anneal in air.

The electrical characteristics of the obtained TFT are PTFT.
The mobility is 40 (cm ² / Vs), Vth is -5.9 (V),
Mobility is 80 (cm ² / Vs) and Vth is 5.0 with NTFT
(V).

It was possible to obtain one substrate for a liquid crystal electro-optical device manufactured according to the method as described above.

The arrangement of the electrodes and the like of this liquid crystal display device is shown in FIG. N-channel thin film transistor and P
The channel type thin film transistor is connected to the first signal line 3 and the second signal line 3.
Are provided at the intersections of the signal lines 4 and. A matrix structure using such C / TFT is provided. NT
The FT is connected to the second end via the contact at the input end of the drain 10.
Of the signal line 4 and the gate 9 is connected to the first signal line 3. The output end of the source 12 is connected to the pixel electrode 17 via a contact.

On the other hand, in the PTFT, the input end of the drain 20 is connected to the second signal line 4 via the contact, the gate 21 is connected to the signal line 3, and the output end of the source 18 is connected via the contact in the same manner as the NTFT. Is connected to the pixel electrode 17.
By repeating this structure horizontally and vertically, 640
A liquid crystal display device having a large pixel size of x480 or 1280x960 can be obtained. In this embodiment, 1920 × 40
It was set to 0. Thus, the first substrate was obtained.

A method for manufacturing the other substrate is shown in FIG. A polyimide resin in which a black pigment is mixed with polyimide is formed on a glass substrate to a thickness of 1 μm by a spin coating method,
Black stripe 8 using the ninth photomask P9
1 was produced. Then, a polyimide resin mixed with a red pigment is formed into a film having a thickness of 1 μm by a spin coating method,
Red filter 8 using the tenth photomask P10
3 was produced. Similarly, using the masks P11 and P12, a green filter 85 and a blue filter 86 were produced. During manufacture of these filters, each filter was baked at 350 ° C. in nitrogen for 60 minutes. After that, the leveling layer 89 was made of transparent polyimide by using the spin coating method.

After that, ITO (Indium Tin Oxide) was formed on the whole of the above to a thickness of 0.1 μm by the sputtering method, and the common electrode 90 was formed using the fifth photomask 91. This ITO film is formed at room temperature to 150 ° C.
Achieved by oxygen at 300 ° C or annealing in the atmosphere,
A second substrate was obtained.

A polyimide precursor was printed on the substrate by the offset method, and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere such as nitrogen. Then, a known rubbing method was used to modify the surface of the polyimide, and a means for orienting liquid crystal molecules in a certain direction was provided at least in the initial stage.

Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A TAB-shaped drive IC, a PCB having a common signal and a potential wiring were connected to the leads on the substrate, and a polarizing plate was attached to the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves, to complete a wall-mounted TV. Compared with the conventional CRT type TV, the device has a planar shape, so that it can be installed on a wall or the like. The operation of this LCD TV is shown in Fig. 1.
It was confirmed by applying to the liquid crystal pixel a signal substantially equivalent to that shown in FIG.

[Embodiment 2] In this embodiment, a viewfinder for a video camera using a liquid crystal electro-optical device having a diagonal of 1 inch was manufactured and the present invention was carried out.

In this embodiment, a viewfinder is constructed by forming a device having a high mobility TFT by a low temperature process with a structure of 387 × 128 pixels. FIG. 4 shows the arrangement of the active elements on the substrate of the liquid crystal display device used in this embodiment.
The fabrication process showing the -B 'cross section is depicted in FIG.

In FIG. 7A, a silicon oxide film as a blocking layer 51 is formed on a glass 50, which is resistant to a heat treatment at 700 ° C. or lower, for example, about 600 ° C., by a magnetron RF (radio frequency) sputtering method as a blocking layer 51. ~ 300
It is made to a thickness of 0Å. The process conditions were an atmosphere of 100% oxygen, a film forming temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The film formation rate using quartz or single crystal silicon for the target was 30 to 100 Å / min.

A silicon film was formed thereon by LPCVD (Low Pressure Vapor Phase) method, sputtering method or plasma CVD method. When forming by the reduced pressure vapor phase method, it is 1
450-550 ° C, which is low by 00-200 ° C, for example, 530 ° C
CVD of disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ )
The film was supplied to the apparatus to form a film. The reactor pressure is 30-300
It was Pa. The film forming rate was 50 to 250 Å / min.
Threshold voltage (Vt) between PTFT and NTFT
In order to control the concentration to be substantially the same as that of h), boron may be added during the film formation with diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ .

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ^-5 Pa or less, the single crystal silicon is used as the target, and the atmosphere is mixed with 20 to 80% of hydrogen in argon. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. These were introduced into a PCVD apparatus, and high-frequency power of 13.56 MHz was applied to form a film.

The film formed by these methods is
5 × 10 oxygen^{twenty one}cm^-3The following is preferable. This acid
When the elemental concentration is high, it is difficult to crystallize and the thermal annealing temperature is
Higher or longer thermal anneal times must be provided.
If it is too small, the backlight will turn off the light.
The current will increase. Therefore 4 × 10¹⁹~ 4 x 10 ^{twenty one}
cm^-3And the range. 4 × 10 for hydrogen²⁰cm^-3And silicon 4
× 10^{twenty two}cm^-3Was 1 atom%.

By the above method, an amorphous silicon film having a thickness of 500 to 5000 Å, for example 1500 Å, is formed, and then heat treatment at a temperature of 450 to 700 ° C. for 12 to 70 hours in a non-oxide atmosphere at a medium temperature, For example, it was held at a temperature of 600 ° C. in a hydrogen atmosphere. Since the amorphous silicon oxide film is formed on the surface of the substrate below the silicon film, no specific nuclei are present in this heat treatment, and the whole is uniformly annealed. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

The annealing causes the silicon film to shift from an amorphous structure to a highly ordered state, and a part thereof assumes a crystalline state. In particular, a region having a relatively high degree of ordering after the film formation of silicon tends to be crystallized and become a crystalline state. However, since silicon existing between these regions is bonded to each other, the silicon members pull each other. Peak 522 of single crystal silicon as measured by laser Raman spectroscopy
Peaks shifted to lower frequencies than cm ^-1 are observed. The apparent particle size is 50 to 5 when calculated from the full width at half maximum.
Although it is a microcrystal like 00Å, in reality there are many highly crystalline regions with a cluster structure, and each cluster has a semi-amorphous structure in which silicon is bonded (anchoring) with each other. Could be formed.

As a result, the coating film is in a state in which it can be said that there is substantially no grain boundary (hereinafter referred to as GB). Since the carriers can easily move between the clusters through the anchored portions, the carrier mobility is higher than that of polycrystalline silicon in which so-called GB is clearly present. That is, hole mobility (μh) = 10 to ²⁰⁰ cm ² /
VSec, electron mobility (μe) = 15 to 300 cm ² / V
Sec is obtained.

On the other hand, when the film is polycrystallized by a high temperature anneal of 900 to 1200 ° C. instead of the anneal at a medium temperature as described above, segregation of impurities in the film occurs due to solid phase growth from nuclei. , GB have a large amount of impurities such as oxygen, carbon, and nitrogen, and have a large mobility in the crystal, but they form a barrier in GB and hinder the movement of carriers there. As a result, it is difficult to obtain a mobility of 10 cm ² / Vsec or more. That is, in this embodiment, the silicon semiconductor having the semi-amorphous or semi-crystal structure is used for the reason as described above.

In FIG. 7 (A), the silicon film is photoetched by using a first photomask, and an NTFT region 13 (channel width 20 μm) is formed on the AA ′ cross section side of the drawing, and a PTFT region. 22 was produced on the BB ′ cross section side.

On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000Å, for example, 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of fluorine may be added to immobilize sodium ions.

After this, 1-5 × 10 ²¹ cm of phosphorus is placed on the upper side.
^-3 concentration silicon film or this silicon film with molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned with a second photomask to obtain FIG. 7 (B). A gate electrode 9 for NTFT and a gate electrode 21 for PTFT were formed. In this embodiment, the NTFT channel length is 10 μm.
m, the channel length for the PTFT is 7 μm, the gate electrode is made of 0.2 μm of phosphorus-doped silicon, and molybdenum is formed thereon to a thickness of 0.3 μm.

In FIG. 7C, 1 to 5 × 10 ¹⁵ cm ^{-2 of} boron is added to the source 18 drain 20 for PTFT.
Was added by the ion implantation method.

Next, as shown in FIG. 7D, the photoresist 6 is used.
1 was formed using a photomask. Source 10 for NTFT and phosphorus 1 to 5 × 10 ¹⁵ cm as drain 12
^It was added by the ion implantation method at a dose amount of ^-2 .

When aluminum (Al) is used as the gate electrode material, the self-alignment method can be applied by patterning this with a second photomask and then anodizing its surface. Since the source / drain contact hole can be formed at a position closer to the gate, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

Next, heating anneal was performed again at 600 ° C. for 10 to 50 hours. The source 10 and the drain 12 of the NTFT, the source 18 and the drain 20 of the PTFT were produced as P ⁺ and N ⁺ by activating impurities. Channel forming regions 19 and 11 are formed as semi-amorphous semiconductors below the gate electrodes 21 and 9.

By doing so, it is possible to fabricate a C / TFT without applying a temperature above 700 ° C. in all steps even though it is a self-aligned method. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material, and the process is very suitable for the large-pixel liquid crystal display device of the present invention.

In this embodiment, the thermal anneal is as shown in FIG.
Done twice in (D). However, the anneal shown in FIG. 7A may be omitted depending on the desired characteristics, and both may be combined with the anneal shown in FIG. 7D to reduce the manufacturing time. In FIG. 7E, an interlayer insulator 65 was formed as a silicon oxide film by the above-described sputtering method. The silicon oxide film may be formed by using the LPCVD method, the photo CVD method, or the atmospheric pressure CVD method. For example, it is formed to have a thickness of 0.2 to 0.6 μm, and then a window 66 for an electrode is formed using a photomask. Further, as shown in FIG. 7 (F), aluminum is formed on all of them by a sputtering method, and a lead 71 and a contact 72 are formed using a photomask, and then,
An organic resin 69 for flattening the surface, for example, a translucent polyimide resin was applied and formed, and another electrode hole was formed using a photomask.

ITO (indium tin oxide film) was formed by the sputtering method in order to connect two TFTs with a complementary structure and to connect the output end thereof to the transparent electrode of one pixel of the liquid crystal device. . It was etched with a photomask to form the electrode 17. This I
The TO film was formed at room temperature to 150 ° C. and was accomplished by oxygen at 200 to 400 ° C. or anneal in the atmosphere. In this way, the NTFT 13, the PTFT 22, and the transparent conductive film electrode 17 were formed on the same glass substrate 50. Obtained T
The electrical characteristics of FT are PTFT and the mobility is 20 (cm ² / V
s), Vth is -5.9 (V), and the mobility is 4 with NTFT.
It was 0 (cm ² / Vs) and Vth was 5.0 (V).

One substrate for a liquid crystal device was manufactured according to the method as described above. FIG. 4 shows the arrangement of electrodes and the like of this liquid crystal display device. A matrix structure using such C / TFT is provided.

Next, as a second substrate, an ITO (indium) film was also formed by sputtering on a substrate in which 2,000 liters of silicon oxide film was laminated on soda-lime glass by sputtering.
A tin oxide film) was formed. This ITO is room temperature ~ 15
The film was formed at 0 ° C. and was accomplished by oxygen at 200 to 400 ° C. or annealing in the atmosphere. A color filter was formed on this substrate using the same method as in "Example 1" to obtain a second substrate.

A polyimide precursor was printed on the substrate by the offset method, and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere such as nitrogen. After that, a known rubbing method was used to modify the surface of the polyimide, and at least in the initial stage, a means for orienting liquid crystal molecules in a certain direction was provided to obtain first and second substrates.

Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. Since the pitch of the leads on the substrate was as fine as 46 μm, the COG method was used for connection. In this embodiment, the gold bumps provided on the IC chip are connected by an epoxy-based silver-palladium resin, and the IC chip and the substrate are embedded and fixed by epoxy modified acrylic resin for the purpose of fixing and sealing. I was there. After that, a polarizing plate was attached to the outside to obtain a transmissive liquid crystal display device.

FIG. 8 shows drive waveforms used in this embodiment.
Instead of the sine wave used in Example 1, a ramp waveform was used.
The ramp wave has an advantage in that the structure is simple and that the gradation data can be easily converted into Δt. The operation is almost the same as that described with reference to FIG. In FIG. 8, as in FIG. 1, the analog voltage applied to the pixel can be digitally obtained. For example, in the pixel A, although the voltage is low, the voltage is applied to the pixel for a long time. Although a high voltage is applied, the time is shorter than that of the pixel A. Therefore, visually, the difference in shade between the pixel A and the pixel B may be smaller than expected. In order to overcome the difficulty, the time when no voltage is applied to any of the Y lines may be set longer than the time when a voltage is applied, as shown in FIG.
For example, if the time is set to be the same as the voltage application time, theoretically the maximum time when the voltage is applied to each pixel is three times the minimum time and actually about two times. Further, as shown in FIG. 9, if the time in which no voltage is applied to any of the Y lines is twice the time in which voltage is applied, for example, the pixel Z _{m, n}
Is only 40% longer than the pixel Z _{n, m + 1} . Therefore, in addition to the pixel voltage, the visual shading error due to the voltage applied to the pixel can be greatly improved.

For example, 49,15 of 384 × 128 dots
Two sets of TFT are 50mm square (36mm from 300mm square substrate)
When a normal analog gradation display is performed on a liquid crystal electro-optical device formed in a multi-layered manner, 16 gradation display is the limit because there is about ± 10% variation in TFT characteristics. . However, when the digital gray scale display according to the present invention is performed, it is possible to display up to 128 gray scales because it is not easily affected by the characteristic variation of the TFT element, and in the color display, 2,097,152 colors are various and delicate. Color display is realized.

In the case of displaying software such as a television image, for example, even "rock" of the same color has a slightly different shade due to the adjustment of the light hitting the minute depressions. If an attempt is made to display a color that is close to the natural color, 16 gradations are difficult and it is not suitable for expressing these subtle depressions. The gradation display according to the present invention makes it possible to impart these minute color tone changes.

The present embodiment is characterized in that digital gradation display is performed in contrast to the conventional pure analog gradation display. The effect is, for example, 640 ×
Assuming a liquid crystal electro-optical device having a number of pixels of 400 dots, it is extremely difficult to manufacture all 256,000 TFTs in total without variation.
Considering mass productivity and yield, in reality, 16-gradation display is considered to be the limit, whereas in order to clarify the applied voltage level, the reference voltage value, not the analog value, is used as a signal from the controller side. Input the reference signal
By controlling the voltage applied to the TFT by controlling the timing for connecting to the FT with a digital value,
Since the present invention is characterized in that the method of covering the characteristic variation of the TFT is adopted, a clear digital gradation display is possible.

[Embodiment 3] In this embodiment, a wall-mounted television is manufactured by using a liquid crystal display device having a circuit configuration as shown in FIG. Also T at that time
FT was polycrystalline silicon using laser annealing.

In the following, a method of manufacturing the TFT portion will be described with reference to FIG. In FIG. 10 (A),
Not expensive, such as quartz glass 700 ° C or less, eg about 60
The blocking layer 10 is formed on the glass 100 that can withstand heat treatment at 0 ° C. by using a magnetron RF (radio frequency) sputtering method.
A silicon oxide film as No. 1 is formed to a thickness of 1000 to 3000Å. The process conditions were an atmosphere of 100% oxygen, a film forming temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The film formation rate using quartz or single crystal silicon for the target was 30 to 100 Å / min.

A silicon film 102 was formed on this by a plasma CVD method. Film formation temperature is 250 ° C to 3
It is carried out at 50 ° C., and in this embodiment 320 ° C., and monosilane (S
iH ₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (S
i ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD device at a pressure of 3 Pa, and 13.56
A high frequency power of MHz was applied to form a film. At this time, the high frequency power is suitably 0.02 to 0.10 W / cm ² , and in this example, 0.055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the film formation rate at that time was about 120 Å / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be approximately the same, boron is used in an amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ by using diborane.
It may be added as a concentration of cm ⁻³ during film formation. Also TFT
In addition to the plasma CVD, a sputtering method or a low pressure CVD method may be used for forming the silicon layer to be the channel region of the above. The method will be briefly described below.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ^-5 Pa or less, the single crystal silicon is used as the target, and the atmosphere is mixed with 20% to 80% of hydrogen in argon. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

In the case of forming by the reduced pressure vapor phase method, it is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 5
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The film forming rate was 50 to 250 Å / min. In order to control the threshold voltage (Vth) of the PTFT and that of the NTFT to be approximately the same, boron may be added during film formation using diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. .

The coatings formed by these methods are
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration is 7 × 10 ¹⁹ cm ^-3 or less,
It is preferable that the size is 1 × 10 ¹⁹ cm ^-3 or less,
If the amount is too small, the leak current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, it is difficult to crystallize, and the laser annealing temperature must be high or the laser annealing time must be long. Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon is 4 × 10 ²²
It was 1 atom% when compared as cm ^-3 .

In order to further promote crystallization of the source and drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ^-3 or less, preferably 1 × 10 ¹⁹ cm ^-3 or less, and the TF for forming a pixel is set.
Oxygen may be added only to the channel forming region of T by the ion implantation method so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .
By the above method, an amorphous silicon film is formed into 500
The film was formed to a thickness of ˜5000 Å, 1000 Å in this example.

After that, the photoresist 103 is used as a mask P.
1 should be used as the source / drain region of NTFT
A pattern was formed in which only the area was opened. And Regis
Ion implantation of phosphorus ions using mask 103 as mask
From 2 x 10¹⁴~ 5 x 10 ¹⁶cm^-2, Preferably 2x
10¹⁶cm^-2Just implant and form the n-type impurity region 104.
I made it. After that, the resist 103 was removed.

Similarly, a resist 105 was applied, and a mask P3 was used to form a pattern in which only the regions to be the source / drain regions of the PTFT were opened. Then, using the resist 105 as a mask, a p-type impurity region was formed. As the impurity, boroso was used, and the ion implantation method was also used to introduce the impurity in an amount of 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻² , preferably 2 × 10 ¹⁶ cm ⁻² . In this way. FIG. 10B was obtained.

After that, a thickness of 50 to 3 is formed on the silicon film 102.
00 nm, for example, 100 nm of silicon oxide film 107
Was formed by the RF sputtering method described above. And
Source / drain / channel regions are crystallized by laser annealing using a XeCl excimer laser.
Activated. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 mJ / cm ² is required for melting the entire film thickness. However, when the energy of 220 mJ / cm ² or more is applied from the beginning, the hydrogen contained in the film is rapidly released, so that the film is broken. Therefore, it is necessary to first drive out hydrogen with low energy and then melt it. In this embodiment, first 1
After expulsion of hydrogen at 50 mJ / cm ² , 23
Crystallization was performed at 0 mJ / cm ² . Further, the silicon oxide film 107 was removed after the laser annealing was completed.

After that, the island-shaped NTFT region 111 and the PTFT region 112 were formed by the photomask P3. A silicon oxide film 108 is formed thereon as a gate insulating film with a thickness of 500 to 2000Å, for example, 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of fluorine may be added to immobilize sodium ions.

Then, phosphorus is added to the upper side in an amount of 1 to 5 × 10 ²¹ cm.
^-3 concentration silicon film or this silicon film with molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned with a fourth photomask P4 to obtain FIG. 10 (D). NTFT
Gate electrode 109 for PTFT and gate electrode 110 for PTFT
Was formed. For example, the channel length is 7 μm, the gate electrode is 0.2 μm of phosphorus-doped silicon, and molybdenum is 0.3 μm thick thereon.

When aluminum (Al) is used as the gate electrode material, the self-alignment method can be applied by patterning this with the fourth photomask P4 and then anodizing the surface. Since the source / drain contact holes can be formed at positions closer to the gate, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

In this way, a C / TFT can be manufactured without applying a temperature above 400 ° C. in all steps. Therefore, an expensive substrate such as quartz does not have to be used as the substrate material, and it can be said that the process is extremely suitable for the large-screen liquid crystal display device of the present invention.

In FIG. 10E, the interlayer insulator 113
Was formed as a silicon oxide film by the above-mentioned sputtering method. This silicon oxide film is formed by LPCVD method, photo CVD method.
Method, atmospheric pressure CVD method may be used. For example, 0.2-0.
Formed to a thickness of 6 μm, and then a fifth photomask P
5 was used to form the window 117 for the electrode. After that, aluminum is further formed on the entire surface to a thickness of 0.3 μm by a sputtering method to form a lead 116 and contacts 114 and 115 using a sixth photomask P6, and then the surface is flattened with an organic resin. 119, for example, a translucent polyimide resin was applied and formed, and the electrode hole was formed again using the seventh photomask P7. In addition, I
TO (indium tin oxide) was formed to a thickness of 0.1 μm by a sputtering method, and the pixel electrode 118 was formed using the eighth photomask P8. This ITO film is formed at room temperature to 150 ° C., and oxygen at 200 to 400 ° C. or an atmosphere in the atmosphere is used.
Fulfilled by Le.

The electrical characteristics of the obtained TFT are PTFT.
The mobility is 35 (cm ² / Vs), Vth is -5.9 (V),
Mobility is 90 (cm ² / Vs) and Vth is 4.8 with NTFT
(V).

It was possible to obtain one substrate for a liquid crystal electro-optical device manufactured by the above method. Since the method for manufacturing the other substrate is the same as that in the first embodiment, it will be omitted.
Then, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A TAB-shaped drive IC, a PCB having a common signal and a potential wiring were connected to the leads on the substrate, and a polarizing plate was attached to the outside to obtain a transmissive liquid crystal electro-optical device. This was connected to a rear lighting device in which three cold cathode tubes were arranged, and a tuner for receiving TV radio waves, to complete a wall-mounted TV. Compared with the conventional CRT type TV, the device has a planar shape, so that it can be installed on a wall or the like. The operation of this LCD TV is the same as that shown in FIG.
It was confirmed by applying a substantially equivalent signal to the liquid crystal pixel.

[0090]

The present invention is characterized in that the gradation display of the digital method is performed in contrast to the gradation display of the conventional pure analog method. The effect is, for example, 640 ×
Assuming a liquid crystal electro-optical device having a number of pixels of 400 dots, it is extremely difficult to manufacture all 256,000 TFTs in total without variation.
In reality, considering the mass productivity and the yield, it is considered that 16 gradation display is the limit, but unlike the present invention, the gradation is purely digitally controlled without adding any analog signal. By displaying, gradation display of 256 gradations or more became possible. Since it is a completely digital display, gradation ambiguity due to variations in TFT characteristics is completely eliminated. Therefore, even if there are slight variations in TFT, extremely uniform gradation display was possible. Therefore, in the past, the yield was extremely poor in order to obtain a TFT with little variation, but the yield of the TFT was not so much a problem according to the present invention, so that the yield of the liquid crystal device was improved and the manufacturing cost was significantly suppressed. I was able to.

For example, 256,0 of 640 × 400 dots
When normal analog gradation display is performed on a liquid crystal electro-optical device in which 00 sets of TFTs are formed in a 300 mm square,
Since there is about ± 10% variation in TFT characteristics, 1
6 gradation display was the limit. However, when the digital gray scale display according to the present invention is performed, it is possible to display up to 256 gray scales because it is hardly affected by the characteristic variation of the TFT element, and the color display is 16,777,2.
A wide variety of 16 colors and subtle colors can be displayed. When displaying software such as a television image, for example, even "rocks" of the same color have slightly different shades due to their fine depressions. If you try to display something close to the natural color,
16 gradations are difficult. The gradation display according to the present invention makes it possible to impart these minute color tone changes.

In the embodiment of the present invention, T using silicon is used.
I explained mainly about FT, but T using germanium
FT can be used as well. In particular, single crystal germanium has an electron mobility of 3600 cm ² / Vs and a hole mobility of 1800 cm ² / Vs, which is the value of single crystal silicon (electron mobility is 1350 cm ² / Vs, hole mobility is 480 c).
Since it exceeds the characteristic of m ² / Vs), it is an extremely excellent material for carrying out the present invention which requires high-speed operation. Further, germanium has a lower transition temperature from an amorphous state to a crystalline state than silicon, and is suitable for a low temperature process. Further, the nucleus generation rate during crystal growth is small, and therefore, generally, large crystals are obtained when polycrystal growth is performed. Thus, germanium has characteristics comparable to those of silicon.

In order to explain the technical idea of the present invention, an electro-optical device mainly using liquid crystal, particularly a display device has been described as an example. However, to apply the idea of the present invention, any display device is used. However, it may be a so-called projection type television, other optical switch, or optical shutter. Further, the electro-optical material is not limited to liquid crystal, and it will be apparent that the present invention can be applied as long as the optical characteristics change due to electrical influences such as electric field and voltage.

[Brief description of drawings]

FIG. 1 shows a driving waveform according to the present invention.

FIG. 2 shows an example of a matrix configuration according to the present invention.

FIG. 3 shows electro-optical characteristics of nematic liquid crystal.

FIG. 4 shows a planar structure of a device according to an example.

FIG. 5 shows a process of a TFT according to an example.

FIG. 6 shows a process of a color filter according to an example.

FIG. 7 shows a process of a TFT according to an example.

FIG. 8 shows an example of another drive waveform according to the present invention.

FIG. 9 shows an example of another drive waveform according to the present invention.

FIG. 10 shows a manufacturing process of an example.

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-6-43434 (JP, A) JP-A-2-234134 (JP, A) JP-A-3-34434 (JP, A) JP-A-63- 283068 (JP, A) JP 1-289917 (JP, A) JP 3-50528 (JP, A) JP 62-143524 (JP, A) JP 1-92797 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/133

Claims (4)

(57) [Claims] 1. A pixel electrode, and a P-type thin film transistor and N connected to the pixel electrode.
A thin film transistor and a circuit for generating a half-wave voltage signal of a sinusoidal wave which is repeated at a constant cycle, wherein the P type thin film transistor and the N type thin film transistor have a channel forming region and impurities. A semiconductor film having a region, a gate insulating film formed over the semiconductor film, and a gate electrode provided through the gate insulating film, and the impurity region is formed through the gate insulating film. While overlapping the gate electrode and applying the voltage signal between the source and drain of the P-type thin film transistor and the N-type thin film transistor, a pulse signal whose polarity is inverted is applied to the gates of the P-type thin film transistor and the N-type thin film transistor. By converting the voltage signal into a digital gradation display signal, An active matrix type display device characterized by applying an indicating signal to the pixel electrode. 2. A pixel electrode, a P-type thin film transistor and an N connected to the pixel electrode.
An active matrix type display device having a P type thin film transistor and a circuit for generating a voltage signal of a ramp wave repeated at a constant cycle, wherein the P type thin film transistor and the N type thin film transistor have a channel forming region and an impurity region. A semiconductor film, a gate insulating film formed over the semiconductor film, and a gate electrode provided through the gate insulating film, and the impurity region is formed through the gate insulating film and the gate electrode. By applying the voltage signal between the source and drain of the P-type thin film transistor and the N-type thin film transistor while applying the pulse signal whose polarity is inverted to the gates of the P-type thin film transistor and the N-type thin film transistor, The voltage signal is converted into a digital gradation display signal, and the digital gradation display signal is converted. Signal is applied to the pixel electrode. 3. The channel forming region according to claim 1 or 2, wherein the concentration of boron is 1 × 10 ¹⁵ to 10.
An active matrix type display device having a size of 1 × 10 ¹⁸ cm ⁻³ . 4. The active matrix display device according to claim 1, wherein the semiconductor film is silicon that is melted and crystallized by irradiation with laser light.