JP3356580B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device having an image display device having display pixels arranged in a matrix, and more particularly to an image display device in which a driving circuit and an image display device are formed monolithically. Things.

[0002]

2. Description of the Related Art Conventionally, as an image display device, for example, an active matrix type liquid crystal display device has a liquid crystal display element 101, a source driver 102 and a gate driver 1 for driving the liquid crystal display element 101, as shown in FIG.
03 and a frequency dividing circuit 104 for dividing the frequency of the clock signal CLK to generate the timing signals CLKS and CLKG.

[0003] The source driver 102 is, for example, shown in FIG.
3, the shift register 105 and the video signal line 1
06, a sampling switch 107, a sampling capacitor 108, a transfer signal line 109, a transfer switch 110, and a buffer circuit 111. The source driver 102 operates by line-sequential scanning.

That is, in the source driver 102, when the timing signal CLKS and the start pulse SPS are input to the shift register 105, the timing signal CLKS
, The shift register 105 sequentially generates sampling pulses.

When a sampling pulse is input to a gate terminal of a sampling switch 107 composed of a transistor, a video signal supplied from a video signal line 106 connected to a source terminal of the sampling switch 107 is sampled. The above operations are sequentially performed in a horizontal scanning period corresponding to the horizontal direction of the display screen of the liquid crystal display element 101, so that the horizontal video signals are sequentially stored in the sampling capacitors 108.

Thereafter, when the transfer signal supplied from the transfer signal line 109 is input to all the gate terminals of the transfer switch 110 composed of the next stage transistor, the video stored in the sampling capacitors 108 at this timing. The sampling data of the signals are simultaneously output to the buffer circuits 111. Thus, the sampling data is supplied as a source bus line signal to the source bus line 112 connected to the liquid crystal display element 101 via the buffer circuit 111.

The buffer circuit 111 is provided, for example, in FIG.
As shown in (1), it is composed of a first-stage NMOS linear circuit 113 and a second-stage PMOS linear circuit 114.

The NMOS linear circuit 113 includes two n-channel MOSs (Metal Oxide Semiconductors) connected in series between a high potential power supply Vdd and a low potential power supply Vss.
r) Transistors (hereinafter referred to as NMOS transistors) Tr1 and Tr2. The above NMOS
The video signal Vin output from the transfer switch 110 is input to the gate electrode of the transistor Tr1,
A bias voltage VBN is applied to the gate electrode of the NMOS transistor Tr2. Also,
An output node Vo of the next-stage PMOS linear circuit 114 is connected to a connection point between the two transistors.

The PMOS linear circuit 114 is composed of two p-channel MOS transistors (hereinafter, referred to as a series) connected in series between a high potential power supply Vdd and a low potential power supply Vss.
(Referred to as PMOS transistors) Tr3 and Tr4. The output node Vo of the preceding NMOS linear circuit 113 is connected to the gate electrode of the PMOS transistor Tr4.
Is applied with a bias voltage VBP. The connection point between the two transistors of the PMOS linear circuit 114 is connected to the output terminal Vout of the buffer circuit 111, and the output from the PMOS linear circuit 114 is supplied to the liquid crystal display element 101 via the source bus line 112. It has become.

Therefore, if the buffer circuit 111 as described above is used for the source driver 102, a video signal can be written to the pixel even if the additional capacitance and the parasitic capacitance of the source bus line 112 increase. Therefore, in the line sequential scanning as described above, the buffer circuit 111 as described above is particularly required. The buffer circuit 1
Reference numeral 11 includes not only the above configuration but also, for example, a so-called operational amplifier (OP amplifier).

In the above configuration, the source driver 10
2. In order to drive the gate driver 103, it is necessary to supply a timing signal CLKS and a timing signal CLKG.

However, in general, one horizontal scanning period of a video signal includes a horizontal video signal output period for outputting a video signal containing video information and a horizontal synchronization signal for synchronizing the horizontal video signal. There is a horizontal blanking period.

On the other hand, also in one vertical scanning period, a vertical blanking period including a vertical synchronizing signal is performed during a period from the output of the last horizontal video signal to the input of the first horizontal video signal of the next vertical scanning period. Exists.

Therefore, in the conventional configuration, the output circuit for generating the clock signal CLK and the clock signal CL are also provided during the horizontal blanking period and the vertical blanking period.
The K frequency dividing circuit 104 was operating.

The vertical and horizontal blanking periods are periods in which each signal does not include video information.
The timing signals CLKS and CLKG obtained by dividing the frequency of the clock signal CLK also operated during this period. Therefore, because of the unnecessary timing signal output operation,
Useless power consumption is increased in the drive circuit.

For example, Japanese Patent Application Laid-Open No. 3-56992 discloses a shift register for sequentially forming a scanning line selection signal by a shift operation, setting of an initial value for the shift register according to a start signal, and an internal shift clock pulse. And a control circuit for starting supply of the shift clock pulse and stopping supply of the shift clock pulse in response to a carry output from the last stage of the shift register.

According to the above publication, the supply of the shift clock pulse is stopped and the shift register stops the shift operation during the period from when the carry signal is transmitted from the last stage of the shift register to when the start signal is input. In addition, power consumption for the shift operation of the shift register can be reduced.

[0018]

By the way, in the conventional active matrix type liquid crystal display device, an amorphous silicon thin film formed on a transparent substrate is used as a substrate material of the pixel transistor SW, and the source driver 102 and the gate are used. Each of the drivers 103 has been constituted by an external IC.

On the other hand, in recent years, in response to demands such as improvement in driving power of pixel transistors accompanying a large screen and reduction in mounting cost of a driving IC, a pixel array and a driving circuit are monolithically formed on a polycrystalline silicon thin film. Methods of forming have been proposed. Further, a method of forming an element on a polycrystalline silicon thin film on a glass substrate at a process temperature equal to or lower than a glass distortion point (about 600 ° C.) has been attempted in order to achieve a larger screen and lower cost.

However, the driving circuit formed monolithically on the polycrystalline silicon thin film has a longer signal wiring than the driving circuit formed on the single-crystal Si substrate. As a result, a voltage drop due to an increase in wiring resistance and power consumption due to charging and discharging of wiring capacitance cannot be ignored. In particular, the power consumption of the clock signal line which supplies the clock signal among the above signal wirings is large, and the power consumption of the driving circuit is mainly caused by the source driver whose driving frequency is higher than the gate driver by two digits or more. I have.

The buffer circuit 111 of the source driver 102 operates as a constant current source.
In 02, the ratio of power consumed is large.

Further, the "liquid crystal driving circuit" disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 3-56992 is limited to reducing the power consumption of a gate driver for driving a scanning line. Since no consideration has been given to the reduction of power consumption in a monolithically formed driving circuit, it has been insufficient to reduce the power consumption of an image display device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide a driving method such as an image display device in which a pixel array and a driving circuit are monolithically formed on a polycrystalline silicon thin film. In an image display device that consumes a large amount of power in a circuit, supply of a signal to a drive circuit or supply of a signal to a data signal line is stopped in synchronization with vertical and horizontal blanking periods included in a video signal. Another object of the present invention is to provide an image display device capable of greatly reducing power consumption in a driving circuit.

[0024]

According to another aspect of the present invention, there is provided an image display device having display pixels arranged in a matrix.
When an image signal including a synchronization signal is
The image display element depends on the input timing of the clock signal.
Data signal lines connected to the
Display device with a driving circuit driven through the
In the vertical and horizontal blanking periods of the video signal,
A control signal output unit that outputs a control signal in synchronization with the
The analog buffer circuit includes a high-potential power supply and a low-potential power supply.
And two n-channel MOS transistors connected in series between
An NMOS linear circuit composed of a transistor, a high-potential power supply,
Two p-channels connected in series with the low-potential power supply
From a PMOS linear circuit composed of MOS transistors
Connected to the high potential power supply of the NMOS linear circuit.
An image is applied to the gate electrode of the n-channel MOS transistor.
Connect the image signal input terminal and the low-potential power supply.
Gate electrode of n-channel MOS transistor connected
Has a control signal input from the control signal output means,
When this control signal is at a high level,
Turn off the connected n-channel MOS transistor
A first buffer stop circuit for connecting to the
P-channel M connected to the high potential power supply of the OS linear circuit
The control signal output is provided to the gate electrode of the OS transistor.
The control signal is input from the
P-channel connected to the low potential power supply when
Second buffer for turning off MOS transistor
Stop circuit connected and connected to low potential power supply
The above is applied to the gate electrode of the p-channel MOS transistor.
The output node of the NMOS linear circuit is connected .

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS. In this embodiment, an active matrix type liquid crystal display device is described as an image display device, and the same applies to the following embodiments.

As shown in FIG. 1, the liquid crystal display device according to this embodiment has a liquid crystal display element (image display element) 1 and a source driver 2 as a drive circuit for driving the liquid crystal display element 1.
And a gate driver 3 and a frequency dividing circuit 4 for dividing the frequency of the clock signal CLK into timing signals CLKS, CLKS ', and CLKG. In the above-described liquid crystal display device, the driving power of the pixel transistor is improved with the enlargement of the screen.
In order to reduce the mounting cost of the drive IC, the liquid crystal display element 1 and the source driver 2 and the gate driver 3 as the drive circuit are formed monolithically on a polycrystalline silicon thin film.

Although not shown, the liquid crystal display element 1 is composed of, for example, an active matrix type liquid crystal display in which pixels arranged in a matrix are driven by switching elements such as active elements (active elements).

As the active element, for example, a thin film transistor (TFT) or MIM (Metal
An Insulator Metal element is used, and is driven by a data signal from the source driver 2 and a scanning signal from the gate driver 3.

The source driver 2 has a timing signal C
LKS · CLKS ′ and a video signal are input, and a timing signal CLKG is input to the gate driver 3. That is,
The source driver 2 receives the input timing signal CLK
A video signal is sampled according to S · CLKS ′, and the sampled video signal is output to the liquid crystal display element 1.
Further, the gate driver 3 outputs a scanning signal to the liquid crystal display element 1 according to the input timing signal CLKG.

As the source driver 2, for example, as shown in FIG. 2, a two-phase shift register 5, a video signal line 6,
Sampling switch 7 ..., sampling capacitor 8
..., transfer signal line 9, transfer switch 10
, And a buffer circuit 11, and there is a so-called driver sample hold type source driver. The sampling switch 7, the sampling capacitor 8, the transfer switch 10, and the buffer circuit 11 are operated by sampling pulses output from each phase of the shift register 5.

The shift register 5 is constituted by an inverter (clocked inverter) composed of, for example, a TFT. The timing signal CLKS and the start pulse SPS are input to one phase, and the timing signal CLKS 'is input to the other phase. And a start pulse SPS '. That is, the shift register 5
When the timing signals CLKS and CLKS 'are input together with the start pulses SPS and SPS', the sampling pulse is transmitted to the TF whose source electrode is connected to the video signal line 6.
The signal is output to the gate electrode of the sampling switch 7 composed of a transistor such as T. When the sampling switches 7 are sequentially turned on by the sampling pulses, the video signals supplied from the video signal lines 6 are sequentially stored in the sampling capacitors 8 connected to the drain electrodes of the sampling switches 7.

The sampling capacitors 8 are connected to the source electrodes of the transfer switches 10 respectively, and the gate electrodes of the transfer switches 10 are connected to
The transfer signal line 9 is connected. That is, when the transfer switches 10 are turned on by the transfer signal supplied from the transfer signal line 9, the video signals accumulated in the sampling capacitor 8 are transferred to the buffer circuits 11 connected to the respective drain electrodes of the transfer switches 10. Source bus line 1 via ...
2 are supplied to the liquid crystal display element 1 from the source bus lines 12.

Although the present embodiment employs a source driver of a driver sample hold system for holding a video signal on the source driver side, the present invention is not limited to this. May be employed as a panel sample-and-hold type source driver that holds the data.

The gate driver 3 is provided with a shift register (not shown) as in the case of the source driver 2. As shown in FIG. 1, the display is controlled according to the timing signal CLKG supplied from the frequency dividing circuit 4. A scanning signal for selecting a pixel is output to the liquid crystal display element 1.

The frequency dividing circuit 4 generates a clock signal CLK selectively output from a clock signal selecting circuit 14 described later.
Are divided in multiple stages to generate a timing signal CLKS · CLKS ′ to be supplied to the source driver 2 and a timing signal CLKG to be supplied to the gate driver 3. The frequency dividing operation includes a multivibrator method, a blocking oscillation method, and the like.

The video signal is supplied to the source driver 2.
And a control signal generating circuit (control signal output means) 13 to detect vertical and horizontal blanking periods included in the video signal. The control signal generation circuit 13 detects the vertical and horizontal blanking periods,
Control signal to clock signal selection circuit (clock stop means)
14.

That is, the control signal generation circuit 13 receives a video signal and outputs a signal during a period included in the input video signal.
For example, as shown in FIG. 3, a control signal is detected by detecting a horizontal video signal period A including video information and a horizontal blanking period B including a horizontal synchronizing signal for synchronizing the video signal. Output.

The control signal generation circuit 13 controls the clock signal selection circuit 14 by outputting a binary control signal as a control signal. That is, the control signal generation circuit 13 outputs a control signal of “Lo” level when detecting the horizontal video signal period A of the video signal, and outputs a “Hi” level when detecting the horizontal blanking period B of the video signal. Is output.

As shown in FIG. 1, the clock signal selection circuit 14 comprises a NOR circuit as a logic circuit, and selectively outputs the clock signal CLK by a binary control signal output from the control signal generation circuit 13. It is supposed to.

That is, in the clock signal selection circuit 14,
When the input control signal is at the “Hi” level, the output is set to the “Lo” level to invalidate the input of the clock signal CLK.
The signal at the “Lo” level is input to the input side of the, and the frequency dividing operation of the frequency dividing circuit 4 is stopped. Therefore, since the operation of the frequency dividing circuit 4 is stopped, the clock signal becomes “L”.
Since the signal at the “o” level is supplied to the source driver 2 and the gate driver 3 as it is, the timing signal CLKS ·
The operation of the source driver 2 and the gate driver 3 by CLKS ′ · CLKG is also stopped. At this time, the liquid crystal display element 1 is in a lighting state, that is, in an image display state at the end of scanning in the previous stage, and is held until the start of scanning of a video signal in the next stage.

In the clock signal selection circuit 14, when the input control signal is at the "Lo" level, the output is set to "H".
The clock signal CLK is output to the frequency dividing circuit 4 as it is at the “i” level.

That is, as shown in FIG. 3, during the horizontal blanking period B of the video signal, the control signal is at "Hi" level, and during that period, the clock signal CLK is at "Lo" level.
Level. On the other hand, in the horizontal video signal output period A of the video signal, the control signal is at the “Lo” level, and during that period, the clock signal CLK is a normal pulse signal.
Note that, also in the vertical blanking period of the video, the clock signal CLK becomes “L” as in the horizontal blanking period.
The level becomes the “o” level, and the frequency dividing operation in the frequency dividing circuit 4 is stopped.

The clock signal selection circuit 14 includes:
Although the NOR circuit is used as the logic circuit, the present invention is not limited to this. For example, an AND circuit may be used. In this case, the clock signal selection circuit 14
The signal at the “Hi” level is output, and the frequency dividing operation of the frequency dividing circuit 4 is stopped.

As described above, the clock signal selection circuit 14
Converts the input clock signal according to the control signal according to the binary control signal output from the control signal generation circuit 13 and outputs the converted signal, thereby dividing the frequency divider circuit 4, the source driver 2, and the gate driver 3 Is stopped. In particular, by stopping the driving of the source driver 2 that consumes a large amount of power, the power consumption of the entire device can be significantly reduced.

Therefore, at least the source driver 2
Is stopped. That is, in the conversion of the clock signal by the control signal, any value can be used as long as the inverter (clocked inverter) constituting the shift register 5 can be reliably turned on / off. The power supply potential may be higher or lower than the power supply potential, or may be different from the above power supply potential.

When the converted clock signal is shifted from the power supply potential, the shift register 5
The transistor forming the inverter has a gate potential Vg.
= 0, if there is a characteristic that a subthreshold current or ON current flows, Vg = 0 or a potential shifted from the power supply voltage by the threshold potential of the transistor so that the drain current Id is minimized. Is more desirable. This is because the transistor constituting the inverter is turned off when the drain current Id is minimized.

[0056] Thus, to select the control signal from <br/> control signal generating circuit 13 by the clock signal selection circuit 14, is selected
The clock signal (timing signal CLKS / CLKS ′) obtained by dividing the control signal obtained by the frequency dividing circuit 4 is shifted by a threshold voltage of the sampling switch 7 of the shift register 5 from the power supply voltage, or the shift register 5 The high-potential power supply Vdd and the low-potential power supply Vss are converted to have the same potential and output to the shift register 5, so that the shift register 5 can be reliably turned ON / OFF.

As a result, the shift operation by the clock signal can be reliably stopped, and as a result, power consumption due to unnecessary shift operation can be eliminated.

In this embodiment, a logic circuit such as a NOR circuit is used as the clock signal selection circuit 14. However, the present invention is not limited to this. The frequency divider 4, the source driver 2, and the gate What is necessary is to stop the operation of the driver 3 based on the clock signal.
As shown in (1), a clock signal selection circuit 15 including a clock signal line switching circuit for switching the clock signal line may be used.

In this case, the clock signal selection circuit 15
The clock signal line is opened and closed by a binary signal from the control signal generation circuit 13, and the clock signal CLK is selectively output to the frequency dividing circuit 4. That is, the clock signal selection circuit 15 is turned on when the control signal is at the “Lo” level, that is, when the horizontal video signal period of the video signal is detected, and when the control signal is at the “Hi” level, that is, When the horizontal blanking period is detected, it is turned off.

The switching circuit of the clock signal selection circuit 15 is a p-channel MOS (Metal Ox
ide Semiconductor) -FET (hereinafter, pMOS-FET)
) And an n-channel MOS-FET (hereinafter referred to as nM
CMOS (Conp. OS-FET)
complementary metal oxide semiconductor) -a CMOS circuit composed of an IC, or the above pMOS-FET, nMOS
-A MOS circuit composed of a single FET may be used. However, using a CMOS circuit has advantages such as lower power consumption and a very small time constant than using a single-channel MOS circuit. It is desirable to use a CMOS circuit as the switching circuit.

Further, the above-described clock signal selection circuit 1
4 and 15 are arranged between the input clock signal CLK and the frequency dividing circuit 4, and the clock signal CL is supplied to the frequency dividing circuit 4.
Although K can be selectively output, the present invention is not limited to this. For example, K may be arranged between the frequency divider 4 and the source driver 2 and the gate driver 3.

In this case, since the clock signal selection circuit 14 or the clock signal selection circuit 15 is arranged close to the source driver 2 and the gate driver 3, it is easy to make the liquid crystal display element 1 and each of the drivers 2 and 3 monolithic. can do.

According to the above configuration, the operation of the drive circuit such as the source driver 2 by the clock signal is stopped by the clock signal selection circuits 14 and 15 in synchronization with the vertical and horizontal blanking periods of the video signal. During the vertical and horizontal blanking periods of the video signal,
In the state where is turned on, unnecessary power consumption by the clock signal can be reduced.

As a result, the power consumption of the driving circuit such as the source driver 2 in the liquid crystal display device can be reduced. Therefore, an image display device having a large power consumption in the driving circuit as in the present embodiment, particularly, The present invention can be suitably used for an image display device in which an image display element and a drive circuit are monolithically formed.

The clock signal selection circuit 14.1
5, the multi-phase shift register 5 of the source driver 2
Clock signal (timing signal CLKS · C
LKS ') is stopped in the order of earlier phases, so that the driving circuit is stopped compared with the conventional case where the output of the clock signal is stopped based on the signal from the last stage of the multi-phase shift register. The supply of the clock signal to the CPU can be stopped without waste and quickly.

As a result, the power consumption of the unnecessary clock signal can be further reduced, so that the power consumption of the driving circuit in the liquid crystal display device can be reduced.

In the above description, a clock signal and a clock signal are supplied to both the source driver 2 and the gate driver 3.
That is, the timing signals CLKS and CLKG are stopped. However, in the case where the display pixels and the driver are made monolithic as in the present embodiment, even if the clock signal of only the source driver 2 having a high drive frequency is stopped, The object of the present invention, that is, reduction of power consumption in a driving circuit can be sufficiently achieved.

Here, the control signal generation circuit 13 will be described with reference to FIGS. In this description, the horizontal synchronizing signal is at the “Lo” level.

The control signal generating circuit 13 includes a synchronizing signal detecting circuit 16 for detecting horizontal and vertical synchronizing signals from the video signal.
(FIG. 5) and a signal conversion circuit 17 for converting a pulse width of a signal output from the synchronization signal detection circuit 16 so as to correspond to an output period (a blanking period) of a blanking signal.
(FIG. 6).

As shown in FIG. 5, the synchronization signal detection circuit 16 has one pnp transistor 18 whose collector is grounded. The emitter electrode E of the pnp transistor 18 is connected in parallel to a high potential power supply Vdd via a resistor R1 and a resistor R2 connected in series and a capacitor C1. A video signal is input to the base electrode B of the pnp transistor 18 via the resistor R3. A GND power supply is connected to the collector electrode C of the pnp transistor 18 via a resistor R4.
Is connected to an inverting circuit 19 composed of an inverter or the like for inverting the polarity of the signal output from the inverter.

As shown in FIG. 7, the pnp transistor 18 turns on when the base-emitter voltage VBE becomes lower than the base-emitter reverse bias Vbe.
And the collector current Ic flows. That is, the collector current Ic flows into the base electrode B through the resistor R2 and the capacitor C1 shown in FIG.

Therefore, by adjusting the resistance values of the resistors R1 and R4, the potential of the horizontal blanking signal including the horizontal synchronizing signal of the video signal is changed to the reverse bias Vbe between the base and the emitter as shown in FIG. Pnp during the video signal period of the video signal.
The collector current Ic is prevented from flowing through the transistor 18.

In this case, when switching from the video signal period of the input video signal to the horizontal blanking period, the potential in the horizontal blanking period becomes lower than the potential in the video signal period, so that the horizontal synchronization in the horizontal blanking period is performed. Since the potential of the signal is lower than the reverse bias Vbe between the base and the emitter, the collector current Ic is supplied to the pnp transistor 18.
Flows. The collector current Ic is output from the collector electrode c to the inverting circuit 19, the polarity of which is inverted by the inverting circuit 19, and the signal conversion circuit 17 outputs the detection signal SYC.
(FIG. 6). The detection signal SYC is a pulse having a waveform synchronized with the horizontal synchronization signal of the video signal, as shown in FIG. Note that the detection signal SYC becomes a pulse having a waveform synchronized with the vertical synchronizing signal even when switching to the vertical blanking period.

In the synchronous signal detecting circuit 16, the pnp transistor 18 whose collector is grounded is used as the switching circuit. However, the present invention is not limited to this. The type of the transistor and the grounding method are not limited.
For example, an npn transistor may be used, or a combination of a common base and a common emitter may be changed.

Here, as shown in FIG. 8, during the blanking period B of the actual video signal, the synchronization signal detection circuit 16
Is longer than the detection signal SYC obtained in
It is necessary to convert the pulse width of the detection signal SYC into a width corresponding to the blanking period B of the video signal. The conversion of the pulse width of the detection signal SYC is performed by the signal conversion circuit 1 shown in FIG.
7 is performed. In this embodiment, the signal conversion circuit 17
Hereinafter, a circuit in which a one-shot multivibrator (monostable multivibrator) and a logic gate are combined will be described.

The signal conversion circuit 17, as shown in FIG.
It comprises two one-shot multivibrators 20 and 21 to which the detection signal SYC is input, respectively, and an OR circuit 22 as a logic gate.

The one-shot multivibrator 20
The detection signal SYC input from the input terminal (input signal D
1), and outputs a binary output signal Q1 to the inverter 23 from the output terminal. The output signal / Q1 whose polarity has been inverted by the inverter 23 is supplied to the OR circuit 22. / Q1 is the same as bar Q1 in FIG.
It is.

That is, the one-shot multivibrator 2
0, as shown in FIG. 8, detects the rising edge of the input signal D1 and generates the "Hi" level of the output signal Q1.

Further, the one-shot multivibrator 2
As shown in FIG. 6, 0 is connected to a high-potential power supply Vdd via an externally provided variable resistor R5 and connected to a variable resistor R5 via a capacitor C2. The length of the "Hi" level period of the output signal Q1 is adjusted by a combination of the resistor R5 and the capacitor C2.

Thus, in this embodiment, the variable resistor R
5 and capacitor C2,
The length of the “Hi” level period of the output signal Q1 is set to be the period (C2R5) until the output of the video signal ends.

The one-shot multivibrator 2
1 processes a detection signal SYC (input signal D2) input from an input terminal and outputs a binary output signal Q2 from an output terminal.
Is output to the OR circuit 22.

That is, the one-shot multivibrator 2
1 detects the falling edge of the input signal D2 and generates the "Hi" level of the output signal Q2, as shown in FIG.

The one-shot multivibrator 2
As shown in FIG. 6, 1 is connected to a high-potential power supply Vdd via an externally provided variable resistor R6 and connected to a variable resistor R6 via a capacitor C3. The length of the "Hi" level period of the output signal Q2 is adjusted by the combination of the resistor R6 and the capacitor C3.

Thus, in this embodiment, the variable resistor R
6 and the capacitor C3,
The length of the “Hi” level period of the output signal Q2 is set to be the period (C3R6) until the output of the video signal starts.

The OR circuit 22 outputs the output signal / Q1 output from the one-shot multivibrator 20 via the inverter 23 and the one-shot multivibrator 21.
And the output signal Q2 output from the
By taking the logical sum of Q1 and the output signal Q2, as shown in FIG. 8, the output signal / Q1 + Q
2 is output. Output signal / Q1 + Q2
Is such that the length of the “Hi” level period corresponds to the horizontal blanking period B of the video signal. / Q1 is
The same as the bar Q1 in FIG.

In this embodiment, the video signal employs horizontal and vertical synchronizing signals having different waveforms as synchronizing signals. For example, a unipolar synchronizing signal obtained by mixing only the horizontal and vertical synchronizing signals is used. You may adopt it. In this case, since the pulse width of the unipolar sync signal is equal to the pulse width of the blanking period, it is not necessary to provide the sync signal detecting circuit 16 shown in FIG. 5, and the configuration of the control signal generating circuit 13 can be simplified.

In this embodiment, the synchronization signal detecting circuit 1
6, the pulse width of the detection signal SYC is adjusted by the one-shot multivibrators 21 and 22,
The present invention is not limited to this. For example, the pulse width may be determined by counting clocks. In this case, the pulse width can be determined more accurately than determined by the time constant of the resistance and the capacitance of the capacitor. This makes it possible to extract a control signal that is reliably synchronized with the blanking period of the video signal.

Further, in this embodiment, the supply of the clock signal input to the source driver 2 and the gate driver 3 is stopped by detecting the blanking period of the video signal, so that the power consumption in the drive circuit is reduced. However, in the following embodiment, the blanking period of the video signal is detected, the buffer circuit 11 of the source driver 2 is directly stopped by the detection signal (control signal), and the power consumption in the source driver 2 is reduced. An image display device to be reduced will be described.

Embodiment 2 Another embodiment of the present invention is described below with reference to FIGS. 9 and 10. For convenience of explanation,
Members having the same functions as those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 9, the image display device according to the present embodiment has a buffer circuit 31 to which a video signal is input and a control signal output from the control signal generation circuit 13 is input. Has a driver.

The buffer circuit 31 includes an initial stage NMOS linear circuit 32 and a subsequent stage PMOS linear circuit 33.

The NMOS linear circuit 32 is connected in series between the high potential power supply Vdd and the low potential power supply Vss.
N-channel MOS (Metal Oxide Semiconductor)
Transistor (hereinafter referred to as NMOS transistor)
Tr1 and Tr2, the input terminal Vin of the video signal is connected to the gate electrode of the NMOS transistor Tr1.
The output node Vo of the OS linear circuit 33 is connected, and a buffer stop circuit 34 is connected to the gate electrode of the NMOS transistor Tr2.
4, a bias voltage VBN for turning on the NMOS transistor Tr2 is applied.

The buffer stop circuit 34 supplies the bias voltage V
BN and the low-potential power supply Vss are input, and these VBN and Vss are selectively applied to the gate electrode of the NMOS transistor Tr2. That is, the buffer stop circuit 34 applies VBN to the gate electrode of the NMOS transistor Tr2 when the “Lo” level control signal is input, and when the “Hi” level control signal is input,
The low potential Vss is applied to the gate electrode of the NMOS transistor Tr2.

The PMOS linear circuit 33 includes two p-channel MOS transistors (hereinafter referred to as P-channel MOS transistors) connected in series between a high potential power supply Vdd and a low potential power supply Vss.
The output node Vo of the preceding NMOS linear circuit 32 is connected to the gate electrode of the PMOS transistor Tr4, and the buffer stop circuit 35 is connected to the gate electrode of the PMOS transistor Tr3. The buffer voltage is supplied from the buffer stop circuit 35 to turn on the PMOS transistor Tr3.

The buffer stop circuit 35 supplies the bias voltage V
BP and the high potential power supply Vdd are input, and these VBP and Vdd are selectively applied to the gate electrode of the PMOS transistor Tr3. That is, when the control signal of the “Lo” level is input, the buffer stop circuit 35 changes the bias voltage VBP to the PMOS transistor Tr3.
When a “Hi” level control signal is input, the high potential Vdd is applied to the PMOS transistor Tr.
3 is applied to the gate electrode.

The output terminal V of the buffer circuit 31 is connected to the connection point of the two transistors of the PMOS linear circuit 33.
out, and the output from the PMOS linear circuit 33 is supplied to the liquid crystal display element 1 via the source bus line 12.

The NMOS transistors Tr1 and T
r2, the element characteristics of the PMOS transistors Tr3 and Tr4 are the same.

The bias voltage VBN is equal to the bias N
The voltage is such that the operation state of the MOS transistor Tr2 is in a saturation region. Vbn is a potential difference between the gate and the source of the NMOS transistor Tr2 when the bias voltage VBN is applied. The bias voltage VBP is a voltage that causes the operation state of the bias PMOS transistor Tr3 to be in a saturation region. Vbp is
This is a potential difference between the gate and the source of the PMOS transistor Tr3 when the bias potential VBP is applied.

Further, the NMOS transistor Tr2
Is the threshold voltage V of the NMOS transistor Tr2.
thn, a margin voltage α for allowing a current to flow to some extent
Is added. That is, Vbn = Vthn + α, and VBN−Vss = Vthn + α.

The Vbp of the PMOS transistor Tr3 is equal to the threshold voltage Vt of the PMOS transistor Tr3.
hp minus a margin voltage α. That is, VbP = Vthp-α, and VBP-Vdd = Vthp-α.

Next, the operation of the buffer circuit 31 will be described below.

First, in the NMOS linear circuit 32, N
The bias Vbn is applied to the MOS transistor Tr2, and the operation state becomes a saturation region.

At this time, the current Isd2 flowing between the source and the drain of the NMOS transistor Tr2 operates in a saturation region.
The current Isd1 flowing between the source and the drain of r1 is Nd
The current does not flow to the MOS transistor Tr2, but flows from the connection point between the NMOS transistor Tr1 and the NMOS transistor Tr2 to the next-stage PMOS linear circuit 33 side.

However, each of the transistors Tr1 and Tr2
The current path branched from the connection point is a PMOS linear circuit 3
Since it is connected to the gate electrode of the third PMOS transistor Tr4, it is almost electrically open. Therefore, in a steady state, Ids1 becomes Ids1 = Ids2.

As described above, the NMOS transistor Tr2
The potential difference between the gate and the source for causing the current Ids2 to flow through is Vbn, and the NMOS transistors Tr1 and Tr2
Are the same, the potential difference between the gate and source of the NMOS transistor Tr1 is also Vbn.
And the output Vo of the NMOS linear circuit 32 is Vo = Vin−Vbn.

Also in the PMOS linear circuit 33 of the next stage, the voltage Vbp is applied between the gate and the source of the PMOS transistor Tr3 so that the operation state is in the saturation region. Performs the same operation except that the signal polarity is different. Therefore,
The potential Vout at the output terminal Vout of the PMOS linear circuit 33 is as follows: Vout = Vo−Vbp. Further, when looking at the relationship with Vin, Vout = Vin−Vbn−Vbp.

Here, when a "Hi" level control signal is input from the control signal generation circuit 13 to the buffer stop circuit 34, a low potential Vss is applied to the gate electrode of the NMOS transistor Tr2. This low potential Vss is
Since the voltage is lower than the threshold voltage Vthn, the NMOS
A current Id flows between the source and the drain of the transistor Tr2.
s2 stops flowing, and the operation of the NMOS linear circuit 32 stops.

Similarly, control signal generation circuit 13 outputs “H”
When an i ″ level control signal is input to the buffer stop circuit 35, the high potential power supply Vdd is applied to the gate electrode of the PMOS transistor Tr3, and the PMOS transistor T3
The current Ids3 stops flowing between the source and the drain of r3, and the operation of the PMOS linear circuit 33 stops.

Therefore, the driving of the buffer circuit 31 provided in the source driver 2 for driving the liquid crystal display element 1 is stopped by the control signal output from the control signal generating circuit 13 during the blanking period of the video signal. Useless power consumption in the source driver 2 can be eliminated. At this time, the liquid crystal display element 1 is in a lighting state, that is, in an image display state at the end of scanning in the previous stage, and is held until the start of scanning of a video signal in the next stage.

Here, the buffer stop circuits 34 and 35 in the buffer circuit 31 will be described below with reference to FIG. Note that any of the buffer stop circuits 34
35, the configuration is basically the same.
In the present embodiment, the buffer stop circuit 35 provided in the PMOS linear circuit 33 will be described.

The buffer stop circuit 35 is provided, for example, in FIG.
0 (a), as shown in FIG.
It consists of Tr6.

A high-potential power supply Vdd is connected to the source electrode of the NMOS transistor Tr5, and N
The drain electrode of the MOS transistor Tr6 is connected, the source electrode of the NMOS transistor Tr6 is connected to the video signal terminal Vin, and the gate electrode of the NMOS transistor Tr6 is connected to the output terminal of the inverter 36.

The control signal from the control signal generation circuit 13 is input to the gate electrode of the NMOS transistor Tr5 and the input terminal of the inverter 36. The connection point between the NMOS transistors Tr5 and Tr6 is connected to the gate electrode of the PMOS transistor Tr3 of the PMOS linear circuit 33.

Therefore, if the control signal input to each of Tr5 and Tr6 is at "Lo" level, NMOS transistor Tr5 is turned off and NMOS transistor Tr6 is turned on. As a result, Vin becomes the bias voltage VBP via the NMOS transistor Tr6.
Is input to the gate electrode of the PMOS transistor Tr3, and the buffer circuit 31 operates.

On the other hand, if the control signal input to each of Tr5 and Tr6 is at "Hi" level, NMOS transistor Tr6 is turned off and NMOS transistor Tr6 is turned off.
5 becomes conductive. As a result, the voltage Vdd from the high-potential power supply Vdd via the NMOS transistor Tr5
Is input to the gate electrode of the PMOS transistor Tr3, and the operation of the buffer circuit 31 stops.

The other circuit of the buffer stop circuit 35 includes PMOS transistors Tr7 and Tr8, as shown in FIG. 10B.

The source electrode of the PMOS transistor Tr7 is connected to the high potential power supply Vdd, and the drain electrode is
The drain electrode of the MOS transistor Tr8 is connected, the source electrode of the PMOS transistor Tr8 is connected to the video input terminal Vin, and the gate electrode of the PMOS transistor Tr7 is connected to the output terminal of the inverter 37.

A control signal from the control signal generation circuit 13 is input to the gate electrode of the PMOS transistor Tr8 and the input terminal of the inverter 37. The connection point of the PMOS transistors Tr7 and Tr8 is connected to the gate electrode of the PMOS transistor Tr3 of the PMOS linear circuit 33.

Therefore, if the control signal input to each of the transistors Tr7 and Tr8 is at "Lo" level, the PMOS transistor Tr7 is turned off and the PMOS transistor Tr8 is turned on. As a result, Vin becomes the bias voltage VBP via the PMOS transistor Tr8.
Is input to the gate electrode of the PMOS transistor Tr3, and the buffer circuit 31 operates.

On the other hand, if the control signal input to each of the transistors Tr7 and Tr8 is at "Hi" level, the PMOS transistor Tr8 is turned off and the PMOS transistor Tr8 is turned off.
7 becomes conductive. As a result, the high potential Vdd is input to the gate electrode of the PMOS transistor Tr3 via the PMOS transistor Tr7, and the operation of the buffer circuit 31 stops.

As another circuit of the buffer stop circuit 35, as shown in FIG. 10C, an NMOS transistor Tr9 and a PMOS transistor Tr10 are used.
Consists of

The high potential power supply Vdd is connected to the source electrode of the NMOS transistor Tr9, and P
The drain electrode of the MOS transistor Tr10 is connected, and the video input terminal Vin is connected to the source electrode of the PMOS transistor Tr10.

The control signal from the control signal generation circuit 13 is input to the gate electrodes of the NMOS transistor Tr9 and the PMOS transistor Tr10. The connection point between the two transistors Tr9 and Tr10 is connected to the gate electrode of the PMOS transistor Tr3 of the PMOS linear circuit 33.

In this case, there is no need to invert the control signal because the Tr9 and Tr10 have different polarities. For this reason, since it is not necessary to provide the inverters 36 and 37 as shown in FIGS. 10A and 10B, the circuit can be simplified.

Therefore, if the control signal input to each of the transistors Tr9 and Tr10 is at the "Lo" level, the NMOS transistor Tr9 is turned off and the PMOS transistor Tr10 is turned on. This allows PMO
Vin is input to the gate electrode of the PMOS transistor Tr3 as the bias voltage VBP via the S transistor Tr10, and the buffer circuit 31 operates.

On the other hand, if the control signal input to each of the transistors Tr9 and Tr10 is at "Hi" level, the PMOS transistor Tr10 is turned off and the NMOS transistor Tr9 is turned on. As a result, the high potential Vdd is input to the gate electrode of the PMOS transistor Tr3 via the PMOS transistor Tr9, and the buffer circuit 3
Operation 1 stops.

Further, in addition to the buffer stop circuit 35 shown in FIGS. 10A to 10C, as shown in FIG. 10D, NMOS transistors Tr11 and Tr12 and PMOS transistors Tr13 and Tr14 are May be connected in parallel. The operation principle at this time is the same as that shown in FIG.

As described above, four circuits have been described as circuit examples of the buffer stop circuit 35, but these are only examples, and a circuit having another configuration can be used by changing the combination of the NMOS transistor, the PMOS transistor, and the inverter. You may.

In this embodiment, the buffer stop circuit 34
Although the above circuit example has not been described, it can be realized by a method similar to that of the buffer stop circuit 35 described above.

The buffer circuit 31 is not limited to the above-described configuration, but may be, for example, a so-called operational amplifier (OP amplifier).

As described above, according to the present invention, the first embodiment
As described above, the clock signals (timing signals CLKS, CLKS ', CLK) of the source driver 2
The operation according to G) is stopped, or the second embodiment is performed.
The liquid crystal display element 1 is turned on during the vertical and horizontal blanking periods of the video signal by stopping the buffer operation of the buffer circuit 11 in the source driver 2 by the control signal from the control signal generation circuit 13 as shown in FIG. In this state, unnecessary power consumption by the clock signal is reduced.

As a result, it is possible to reduce the power consumption of the driving circuit such as the source driver 2 in the liquid crystal display device. Therefore, the image display device which consumes a large amount of power in the driving circuit, particularly, the image display device and the driving circuit Can be suitably used in an image display device formed monolithically.

Further, according to the present invention, as disclosed in, for example, Japanese Patent Application Laid-Open No. Sho 60-35789, low power consumption is achieved without switching the non-lighting / lighting of the liquid crystal without changing the liquid crystal display element. In the state where 1 is turned on, it is possible to reduce power consumption relating to unnecessary clock signals. Accordingly, flicker due to repetition of non-lighting / lighting of the liquid crystal display element 1 does not occur, so that display quality can be improved.

Further, as another prior art disclosed in Japanese Patent Application Laid-Open No. Sho 62-143095, in order to achieve low power consumption, there is a method of activating an analog buffer for a predetermined period and deactivating the analog buffer during the other period. It has been disclosed.

However, in the second embodiment, the buffer is stopped in synchronization with the blanking period by detecting the blanking period of the video signal, so that only the video signal is supplied to the liquid crystal display element 1 without waste. Therefore, as compared with the case where the analog buffer is stopped for a predetermined period irrespective of the video signal as in JP-A-62-143095, the video signal is more stably transmitted to the liquid crystal display element 1. Can be supplied.

In the liquid crystal display device of each of the above embodiments, the driving power of the pixel transistor can be improved with an increase in the screen size, and the driving I / O can be improved.
In order to reduce the mounting cost of C, etc., the liquid crystal display element 1 and the source driver 2 and the gate driver 3 as a drive circuit are formed monolithically on a polycrystalline silicon thin film. However, the power consumption can be sufficiently reduced even if the liquid crystal display element 1 and the source driver 2 and the gate driver 3 are separately formed.

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[Brief description of the drawings]

FIG. 1 is a schematic configuration block diagram of an image display device according to an embodiment of the present invention.

FIG. 2 is a schematic configuration block diagram of a source driver provided in the image display device shown in FIG.

FIG. 3 is a timing chart of the image display device shown in FIG.

FIG. 4 is a schematic block diagram of an image display device according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a synchronization signal detection circuit of a control signal generation circuit provided in an image display device according to still another embodiment of the present invention.

FIG. 6 is a block diagram showing a signal conversion circuit of the control signal generation circuit.

7 is a graph showing a relationship between a collector current of a transistor provided in the synchronization signal detection circuit shown in FIG. 5 and a voltage between a base and an emitter.

8 is a timing chart in the signal conversion circuit shown in FIG.

FIG. 9 is a schematic configuration block diagram of a source driver of an image display device according to still another embodiment of the present invention.

FIG. 10 is a circuit diagram showing a buffer stop circuit provided in the source driver shown in FIG. 9;

FIG. 11 is a schematic block diagram of a conventional image display device.

12 is a block diagram of a buffer circuit of a source driver provided in the image display device shown in FIG.

13 is a schematic configuration block diagram of a source driver provided in the image display device shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display element (image display element) 2 Source driver (drive circuit) 3 Gate driver (drive circuit) 5 Shift register 11 Buffer circuit (analog buffer circuit) 13 Control signal generation circuit (control signal output means) 14 Clock signal selection circuit (Clock stop means) 15 Clock signal selection circuit (Clock stop means) 31 Buffer circuit (Analog buffer circuit) 34 Buffer stop circuit (Buffer stop means) 35 Buffer stop circuit (Buffer stop means) A Horizontal video signal period B Horizontal blanking period

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-32093 (JP, A) JP-A-6-337655 (JP, A) JP-A-6-22165 (JP, A) JP-A-3-32065 259665 (JP, A) Japanese Utility Model 63-40063 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/20 G02F 1/133 505 G09G 3/36

Claims (1)

(57) [Claims] An image display element having display pixels arranged in a matrix and a video signal including a synchronization signal are input, and a data signal line connected to the image display element is input at a clock signal input timing. An image display device having a driving circuit driven through an analog buffer circuit, comprising: a control signal output unit that outputs a control signal in synchronization with a vertical and horizontal blanking period of a video signal. An NMOS linear circuit composed of two n-channel MOS transistors connected in series between a high potential power supply and a low potential power supply, and two NMOS series circuits connected in series between the high potential power supply and the low potential power supply And a n-channel connected to a high potential power supply of the NMOS linear circuit. The gate electrode of the MOS transistor, with the input terminal of the video signal is connected to the gate electrode of the connected n- channel MOS transistor to the low potential power source,
A control signal is input from the control signal output means, and a first buffer stop circuit for turning off an n-channel MOS transistor connected to the low potential power supply when the control signal is at a high level is connected; A control signal is input to the gate electrode of the p-channel MOS transistor connected to the high potential power supply of the PMOS linear circuit from the control signal output means. When the control signal is at a high level, the control signal is supplied to the low potential power supply. Connected p-
A second buffer stop circuit for turning off the channel MOS transistor is connected, and an output node of the NMOS linear circuit is connected to a gate electrode of a p-channel MOS transistor connected to a low potential power supply. An image display device characterized by the above-mentioned.