KR100446391B1 - Driver circuit of liquid crystal display device and its driving method, especially preventing generation of main clock signal - Google Patents

Abstract

PURPOSE: A driver circuit of a liquid crystal display device and its driving method are provided to reduce power consumption by proving a power saving clock signal to a liquid crystal panel driver IC disabled during an inactive period of an image signal. CONSTITUTION: A liquid crystal display device comprises a driver IC driving a liquid crystal panel by generating a control signal using a main clock signal(MLCK). In a clock generation unit(100), A clock signal preventing the generation of the main clock signal is provided by a horizontal synchronous signal(H) and a vertical synchronous signal(V) or a data enable signal. And the driver IC is disabled during an inactive period of an image signal. The inactive period of the image signal is an inactive period of the data enable signal.

Description

Driving circuit and driving method of liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving circuit of a liquid crystal display device having low power consumption and a driving method thereof.

Recently, the demand for portable computers, portable communication devices, and the like with LCD screens is increasing. These portable devices are usually powered by batteries or rechargeable batteries, which have a limited power supply.

Accordingly, there is a demand for a liquid crystal panel that has increased electrical efficiency and reduced power consumption.

The driver IC for driving the liquid crystal panel receives a main clock signal (hereinafter referred to as MCLK), a horizontal sync signal and a vertical sync signal included in an image signal, and a data enable signal DTMG. A drive control signal is provided to each pixel of the panel.

In general, since the video signals provided on the liquid crystal display are in series, a scanning line method for realizing a single image by scanning the video signals in the horizontal and vertical directions using the horizontal and vertical synchronization signals as the control signals is used.

After the serial image signal reaches the end point from the start point of the liquid crystal panel, the return time to the next start point is called a return time. During the return time, the liquid crystal panel should be blanked before being displayed normally.

In order to guarantee the blanking time, a blanking time is set in the video signal. In other words, the normal return time is set so that the horizontal return time takes about 17% of the horizontal scanning time and the vertical return time takes about 8% of the vertical scanning time.

In addition, the data enable signal DTMG is used to prevent malfunction of the liquid crystal panel due to noise or interference signals other than the video signal. This is done by the data enable signal periodically providing a disable signal to the liquid crystal panel driver IC so that no data is accepted during the disable period.

In the conventional general case, the driver IC of the liquid crystal panel is directly controlled by the main clock signal MCLK, and thus the driver IC continuously provides power to the liquid crystal display.

However, since the liquid crystal panel is blanked in the blanking time and the disable period of the data enable signal DTMG, the liquid crystal display does not actually need to be driven.

Therefore, in the present invention, instead of the conventional design method in which MCLK is always supplied to the driver IC even during the blanking time, the MCLK during the inactive period of the video signal such as the horizontal and vertical blanking time or the disable period of the data enable signal (DTMG) It is an object of the present invention to provide a driving method and a driving circuit of a liquid crystal display element that can reduce power consumption by making the non-operating state.

1a to 1c are views for explaining a first embodiment of the present invention,

2a to 2c are views for explaining the first embodiment of the present invention,

(Explanation of symbols for the main parts of the drawing)

100, 200: clock generating means 11: buffer

12, 13, 22: end gate 21: buffer

MCLK: Main clock signal V: Vertical synchronization signal

H: Horizontal sync signal DTMG: Data enable signal

Ma, Mb: Clock signal

In order to achieve the above object of the present invention, the present invention provides a liquid crystal display device comprising a driver IC, wherein the clock signal provided to the driver IC disables the driver IC during an inactive period of the video signal. A driving method of a liquid crystal display device is provided.

In addition, the present invention is a circuit for implementing the driving method, the clock signal which becomes inactive during the retrace time of the horizontal synchronization signal and the vertical synchronization signal, the horizontal synchronous signal, the vertical synchronous signal, and the main clock signal as inputs thereof. It provides a driving circuit of the liquid crystal display device comprising a clock generating means for outputting.

And a clock generating means for inputting a data enable signal and a main clock signal as its inputs, and outputting a clock signal which becomes an inactive section to an inactive section of the data enable signal. To serve.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The driving circuit of the liquid crystal display element of the present invention controls the input data by the horizontal synchronizing signal (H), the vertical synchronizing signal (V), the data enable signal (DTMG), and the main clock signal (MCLK). Data disable time or blanking time using a driver IC (not shown) for displaying an image, a data enable signal DTMG, a vertical sync signal V, or a horizontal sync signal H And a clock signal generator for generating a clock signal for deactivating the main clock signal.

FIG. 1A is a block diagram illustrating the clock signal generator 100 in the driving circuit of the liquid crystal display device according to the first embodiment.

As shown in FIG. 1A, the clock signal generator 100 according to the first embodiment receives the vertical synchronization signal V, the horizontal synchronization signal H, and the main clock signal MCLK as input signals, and FIG. 1B. As shown in FIG. 6, the driver IC is disabled in the inactive period of the data enable signal, thereby outputting a clock signal Ma for reducing power consumption to the driver IC (not shown).

1C shows a detailed circuit diagram of the clock signal generator 100 according to the first embodiment.

As illustrated in FIG. 1C, the clock signal generator 100 may include the first and gate 11 inputting the vertical and horizontal synchronization signals V and H, the output of the first and gate, and the main clock signal MCLK. Is composed of a second end gate 13 having two inputs as an output of the buffer 12 as an input.

Referring to FIG. 1C, when any one of the vertical or horizontal synchronization signals V and H enters an inactive low state, that is, a blanking time, the clock signal Ma that becomes low as shown in FIG. 1B. Output to the driver IC. Therefore, the main clock signal MCLK is inputted during the retrace time to make it inactive by the clock signal Ma from the clock signal generator 100, and the liquid crystal generated by the driver IC by the main clock signal. The display gate and source control signals are also inactive.

As shown in FIG. 1B, when the main clock signal MCLK is compared with the clock signal Ma according to the present embodiment, the logic low state of the clock signal Ma, that is, the inactive section is the main clock signal MCLK. It can be seen that about 25% more than the inactive period of.

This is because a low state is inputted to the clock signal generator 100 as shown in FIGS. 1A and 1B during the blanking time, which accounts for about 17% of horizontal scanning time and about 8% of vertical scanning time. .

2A is a block diagram illustrating a clock signal generator 200 according to a second embodiment of the present invention.

As shown in FIG. 2A, the clock signal generation unit 200 according to the second embodiment receives the data enable signal DTMG and the main clock signal M as inputs, and the clock signal Mb as shown in FIG. 2B. Outputs

2C shows a detailed circuit diagram of the clock signal generator 200 according to the second embodiment.

As shown in FIG. 2C, the clock signal generation unit 200 uses the AND gate 22 having the two inputs as the data enable signal DTMG and the output of the buffer 21 as the main clock MCLK. Consists of

Referring to FIG. 2C, when the data enable signal DTMG becomes logic low, that is, in an inactive state, the clock signal generator 200 may have a logic low state.

As shown in FIG. 2B, when the main clock MCLK signal is compared with the clock signal Mb according to the present embodiment, it can be seen that the inactive section of the clock signal Mb is larger than the inactive section of the main clock signal. have.

The clock signals Ma and Mb of the first and second embodiments are supplied to input terminals of the liquid crystal panel driver IC although not shown. Therefore, the liquid crystal display is driven only during the active period of the clock signals Ma and Mb.

As described in detail above, according to the present invention, the main clock signal does not directly control the liquid crystal panel driver IC as in the conventional case. Instead, the liquid crystal panel uses a power saving type clock signal that is disabled during an inactive period of the video signal. By providing the driver IC, power consumption can be reduced.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (5)

A liquid crystal display device comprising a driver IC for driving a liquid crystal panel by generating a control signal using a main clock signal. Providing the driver IC with a clock signal that blocks the generation of the main clock signal by a horizontal synchronization signal, a vertical synchronization signal, or a data enable signal, thereby disabling the driver IC during an inactive period of the video signal; The inactive section of the signal is an inactive section of the data enable signal. Clock generation means for inputting a horizontal synchronizing signal, a vertical synchronizing signal, and a main clock signal as inputs thereof to generate a clock signal which becomes an inactive section during the blanking time of the horizontal synchronizing signal and the vertical synchronizing signal; And a liquid crystal panel driver IC which is disabled during an inactive period of the video signal by the clock signal generated from the clock generating means. The method of claim 2, The clock signal generating means includes: a first AND gate which receives, as its input, a horizontal synchronous signal and a vertical synchronous signal; A buffer having the main clock signal as its input; And And a second AND gate serving as the input of the first AND gate and the buffer, and serving as an output of the clock signal generating means. Clock generation means for inputting a data enable signal and a main clock signal as inputs thereof to generate a clock signal that becomes an inactive period in an inactive period of the data enable signal; And a liquid crystal panel driver IC which is disabled during the inactive period of the video signal by the clock signal generated by the clock generating means. The method of claim 4, wherein The clock generating means includes a buffer having a main clock signal as its input; And And an AND gate having a data enable signal and an output of the buffer as an input thereof.

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