JP3346810B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS FET.

[0002]

2. Description of the Related Art As a conventional method of manufacturing a silicide transistor, there is a manufacturing method as shown in FIGS. As shown in FIG. 5A, a step of depositing a polycrystalline silicon film 303 on a semiconductor substrate 301 having a field oxide film 302 formed in a predetermined region, and as shown in FIG. Oxide film 30 on silicon film 303
4 is formed, the oxide film 304 and the polycrystalline silicon film 303 in a region to be a channel region of the transistor are etched by RIE until the silicon substrate is exposed, and as shown in FIG. Oxide film 3
05, forming the gate electrode 306 and doping the semiconductor substrate with high-concentration impurity ions of a conductivity type opposite to that of the semiconductor substrate by ion implantation, and as shown in FIG. The source / drain region 308 and the gate electrode 30 are self-aligned by (RTA).
After forming the titanium silicide layer 307 by silicidation of the surface 6, unreacted Ti is selectively removed. (For example, M. Shimizu et al., Symposium
on VLSI Technology Digest of Tchnical Paper
s, p11 (1988))

[0003]

SUMMARY OF THE INVENTION Conventional MOS FET
In the step of etching the oxide film in the region to be the channel region of the transistor and the polycrystalline silicon film until the silicon substrate is exposed by RIE, the silicon substrate is damaged by RIE, In FIG. 5D, since the portions A and B have a sharp acute angle, there is a problem that electrolytic concentration occurs and the transistor characteristics deteriorate. Further, since the impurity diffusion layer is formed before performing the silicidation reaction (before depositing the Ti metal), it is difficult to control the silicidation reaction due to the influence of impurities and the effect of the grains of polycrystalline silicon. There is a problem that the TiSi ₂ C54 crystal cannot be formed stably and the resistance increases.

[0004]

In order to solve the above-mentioned problems, in a transistor of a semiconductor device, a gate electrode with a gate insulating film interposed between an active region surrounded by an element isolation region and the element isolation region is provided. A source between the region and the gate electrode,
A word line is provided on the element isolation region, a side wall and an upper portion of the gate electrode and the word line are covered with an insulating film, and a source and a drain on both sides of the gate electrode are provided.
On the word line and the
Has a stacked diffusion region in the region between
Having an upper wiring on the stacked diffusion region;
The raised diffusion area is stacked higher than the upper surface of the word line.
In the method of manufacturing a transistor of a semiconductor device, a step of forming an element isolation region on a semiconductor substrate, a step of forming a gate insulating film, and a step of surrounding the element isolation region Embedding a first polycrystalline silicon film in the selected active region via the gate insulating film, and selectively forming a first refractory metal silicide film only on the first polycrystalline silicon film Sequentially depositing a conductive film and a first insulating film; and forming the first polycrystalline silicon film, the first refractory metal silicide film, the conductive film, and the first insulating film into a word line pattern. Patterning, forming a gate electrode in the active region surrounded by the element isolation region, forming a second insulating film on the gate electrode side wall and the word line side wall, sandwiching the word line and the gate electrode Embedding a second polycrystalline silicon film in the region until the surface is planarized, and patterning the second polycrystalline silicon film by etching back until the second insulating film above the word line is exposed. Forming a second refractory metal silicide film in a self-aligning manner on the second polycrystalline silicon film, and forming source and drain regions reaching the semiconductor substrate by impurities of a conductivity type opposite to that of the semiconductor substrate. Is formed.

Alternatively, in order to solve the above problem, a method for forming a source / drain region of a transistor includes a step of depositing a refractory metal film on the second polycrystalline silicon film, Reacting the refractory metal film with the second polycrystalline silicon film to form a refractory metal silicide film, etching away the unreacted refractory metal film, and performing ion implantation. Implanting an impurity of the opposite conductivity type to the semiconductor substrate into the refractory metal silicide film; and changing the refractory metal silicide film into a stable crystal structure by a second rapid heating treatment; After depositing the interlayer insulating film, a step of performing a heat treatment to activate impurities of a conductivity type opposite to that of the semiconductor substrate and diffusing the impurities to the semiconductor substrate is provided.

Further, the high melting point metal or the high melting point metal film is any one of Ti, Co, Ni, Zr, V and Hf.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device and the method of manufacturing the same according to the present invention will be described below in detail with reference to embodiments. 1 (a) is a plan view of the semiconductor device of the present invention, and FIGS. 1 (a) in the A - A '
FIG. 1B is a sectional view of the surface. 2 (a) to 2 (c), 3 (d) to 3 (f), and 4 (g) to 4 (i) are step-by-step cross-sectional views of the transistor of the present invention.

First, as shown in FIG. 2A, a field oxide film 202 is formed on a semiconductor substrate 201 (a P-type semiconductor substrate in this embodiment).

Next, as shown in FIG. 2B, a gate oxide film 203 is formed in an active region surrounded by the field oxide film.
Is formed, and the polycrystalline silicon film 204 is buried. In this embodiment, as a method of embedding the polycrystalline silicon film, a polycrystalline silicon film is deposited and then a photoresist is applied and flattened, and under the etching conditions without selection between the polycrystalline silicon film and the photoresist, Etchback is performed until the field oxide film is exposed. However, as the region becomes smaller in the future, planarization can be achieved only by depositing a polycrystalline silicon film.

Next, a refractory metal film (a titanium film in this embodiment) is deposited, and a first RTA process is performed in a nitrogen atmosphere at 625 ° C. for about 20 seconds, for example, to form a metastable titanium silicide layer 205. Is formed, and the unreacted titanium metal is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide solution, and impurity ions (arsenic ions in this embodiment) of the opposite conductivity type to the substrate are, for example, 40 Kev in this embodiment. After injecting a dose of about 1E16 / cm ² into the titanium silicide film 205 at an implantation energy of about 200 ° C., a second RTA process is performed in a nitrogen atmosphere at 900 ° C. for about 20 seconds, for example. 205 is stable, TiSi ₂
FIG. 2 (c) is obtained by changing to a C54 crystal structure.

Next, as shown in FIG. 3D, a conductor film (in this embodiment, a titanium silicide film 206) and an oxide film 207 are sequentially deposited.

Next, as shown in FIG. 3 (e), the oxide film 207, the conductor film (titanium silicide film 206), the titanium silicide film 205, the polycrystalline silicon film are formed by using a photoresist as a word line pattern as a mask. 204 is sequentially etched to form a word line 209 in which a gate electrode 208 is embedded on the active region. Next, FIG.
As shown in (f), after depositing the oxide film, the oxide film is etched back until the silicon substrate is exposed on the active region, and a sidewall oxide film 210 is formed on the word line 209 and the gate electrode 208 sidewall. .

Next, as shown in FIG. 4G, a polycrystalline silicon film 211 is buried in a region sandwiched between the word line 209 and the gate electrode 208 to prevent a short circuit with an adjacent active region. The polycrystalline silicon film 211 is patterned and separated on an element isolation region (a region in FIG. 1B). Here, in this embodiment, after the polycrystalline silicon film is deposited until the surface is flattened, the word line 209 is formed.
Etchback is performed until the upper oxide film 207 is exposed, and the polycrystalline silicon film 211 is buried.

Next, as shown in FIG. 4H, a high melting point metal film (a titanium film in this embodiment) is deposited, and a third RT is formed.
A treatment is performed, for example, in a nitrogen atmosphere at 625 ° C. for about 20 seconds to form a metastable titanium silicide layer 212;
The unreacted titanium metal is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide solution. After implanting a dose of about 5E15 / cm ² into the titanium silicide film 212 at an energy that is implanted into the titanium silicide film 212, for example, in this embodiment, at an implantation energy of about 35 Kev, RTA treatment, for example, in a nitrogen atmosphere at 900 ° C.
The titanium silicide film 212 is changed to a stable, TiSi ₂ C54 crystal structure for about 20 seconds.

Next, as shown in FIG. 4I, after the interlayer insulating film 213 is deposited, the source and drain regions 214 reaching the semiconductor substrate 201 are formed by heat treatment at 900 ° C. for about 15 minutes. As ions in the gate electrode are sufficiently activated.

Finally, a contact hole is formed to form an upper wiring, thereby obtaining the semiconductor device shown in FIG.

Embodiment 2 The method for forming a silicide layer of the present invention is not limited to the first embodiment.

As the silicidation of the polycrystalline silicon film,
High melting point metal ions, for example, Ti ions are implanted into the polycrystalline silicon films 204 and 211 by an ion implantation method, and the surfaces of the polycrystalline silicon films 204 and 211 are made amorphous. Next, a high melting point metal film made of the same metal as the high melting point metal, for example, a Ti film in this embodiment is deposited. Next, the first RTA
The treatment is performed, for example, in a nitrogen atmosphere at 625 ° C. for about 20 seconds to allow the Ti in the polycrystalline silicon films 204 and 211 and the Ti film to react with the silicon in the polycrystalline silicon film to form a metastable titanium silicide layer , 212, and the unreacted titanium metal is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide solution. Thereafter, a desired transistor element is formed through the same steps as in the first embodiment.

In the first and second embodiments, an amorphous silicon film may be used instead of the polycrystalline silicon films 204 and 211. When an amorphous silicon film is used, there is an advantage that a silicidation reaction occurs uniformly because there is no grain unlike a polycrystalline silicon film.

Further, the refractory metal material for forming the silicide layer of the present invention is not limited to titanium metal. C
o, Ni, Zr, V, and Hf metals may be used.

[0021]

As is clear from the above, according to the present invention, a gate electrode is buried in an active region surrounded by an element isolation region via a gate insulating film. There is a word line, the gate electrode and the side wall of the word line and the upper part of the word line are covered with an insulating film, and in a region sandwiched between the word line and the gate electrode, an upper part reaching the semiconductor substrate is formed. To form a very shallow junction to diffuse impurities from the silicide layer formed above the channel part because of the transistor element characterized in that the source and drain regions formed by the silicide film are buried. And the short channel effect of the transistor can be suppressed. Further, since the silicide region does not reach the semiconductor substrate, the leakage current is small. Further, since a very low-resistance silicide layer is formed, it is not necessary to provide a contact region on the active region, and the diffusion layer area (active region) can be designed to be very small, so that the parasitic resistance of the diffusion layer can be reduced. In addition, when the speed of the transistor can be improved, the aspect ratio of the contact hole can be reduced.

In a transistor forming step, after forming a gate oxide film and a gate electrode, a polycrystalline silicon film is deposited, and a stacked diffusion layer region (source, drain region) separated in a self-aligned manner by etch-back. 5), there is no damage to the channel portion as in the conventional example of FIG.

[Brief description of the drawings]

FIG. 1A is a plan view of a semiconductor device according to the present invention, and FIG. 1B is a cross-sectional view taken along the line AA ′ in FIG.

FIGS. 2A to 2C are cross-sectional views in the order of steps of a transistor according to the present invention.

FIGS. 3A to 3F are step-by-step sectional views (d) to (f) of a transistor according to the present invention.

FIGS. 4A to 4I are cross-sectional views in the order of steps of a transistor according to the present invention.

5A to 5D are cross-sectional views of a transistor in a conventional example in order of process.

[Explanation of symbols]

101, 201, 301 semiconductor substrate 102, 202, 302 field oxide film 303 polycrystal silicon film 304 oxide film 103,203,305 gate oxide film 204 polycrystal silicon film 205 a silicide film 206 silicide film 207 oxide film 104,208, 306 Gate electrode 105, 209 Word line 210 Side wall oxide film 211 Polycrystalline silicon film 106, 212 Silicide film 107, 213 Interlayer insulating film 108, 214 Source / drain region 109 Contact hole 110 Upper wiring 307 Ti silicide film 308 Source / drain region

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-100326 (JP, A) JP-A-63-255965 (JP, A) JP-A-3-174766 (JP, A) JP-A-4- 307968 (JP, A) JP-A-62-86853 (JP, A) JP-A-62-33466 (JP, A) JP-A-62-117329 (JP, A) Applied Physics Vol. 61, No. 11, (1992) −11), pp. 1143 to 1146

Claims (6)

(57) [Claims] In a transistor of a semiconductor device, an active region surrounded by an element isolation region includes a gate electrode with a gate insulating film interposed therebetween, the inter-element isolation region and the gate electrode.
A source / drain region between the electrodes, a word line provided on the device isolation region, sidewalls and upper portions of the gate electrode and the word line covered with an insulating film, and both sides of the gate electrode
On the source and drain regions and the device isolation region
Stacked in the area between the word line and the gate electrode
A diffusion region, and an upper wiring is provided on the stacked diffusion region.
The stacked diffusion region is higher than the upper surface of the word line.
A semiconductor device characterized by being piled up well . 2. A method for forming a transistor in a semiconductor device, comprising: forming an element isolation region on a semiconductor substrate;
Forming a gate insulating film, embedding a first polycrystalline silicon film in the active region surrounded by the element isolation region via the gate insulating film, and forming only the first polycrystalline silicon film. Selectively forming a first refractory metal silicide film; sequentially depositing a conductive film and a first insulating film; the first polycrystalline silicon film and the first refractory metal silicide film Patterning the conductive film and the first insulating film into a word line pattern to form a gate electrode in an active region surrounded by the element isolation region; and forming a second insulating film on the gate electrode side wall and the word line side wall. Forming a film, and forming a second film in a region sandwiched between the word line and the gate electrode.
Embedding the polycrystalline silicon film until the surface is flattened; and patterning the second polycrystalline silicon film by etching back until the second insulating film on the word line is exposed, Forming a second refractory metal silicide film in a self-aligning manner on the second polycrystalline silicon film, and forming source and drain regions reaching the semiconductor substrate with impurities of a conductivity type opposite to that of the semiconductor substrate; A method for manufacturing a semiconductor device, comprising: 3. A method for forming a source / drain region of a transistor in a method of manufacturing a semiconductor device according to claim 2, wherein a step of depositing a high melting point metal film on the second polycrystalline silicon film is performed. Reacting the refractory metal film with the second polycrystalline silicon film by the rapid heat treatment of 1;
A step of forming a high melting point metal silicide film, a step of removing the unreacted high melting point metal film by etching, and injecting impurities of the opposite conductivity type to the semiconductor substrate into the high melting point metal silicide film by an ion implantation method. A step of changing the refractory metal silicide film into a stable crystal structure by a second rapid heat treatment, and a step of depositing an interlayer insulating film thereon, and then performing a heat treatment to remove impurities of the opposite conductivity type to the semiconductor substrate. And a step of diffusing impurities to a semiconductor substrate while activating the semiconductor device. 4. The method of forming a source and drain region of a transistor in the method of manufacturing a semiconductor device according to claim 2, wherein a high melting point metal is implanted into the surface of the second polycrystalline silicon film by an ion implantation method. Amorphizing a surface of the second polycrystalline silicon, and forming the second polycrystalline silicon on the second polycrystalline silicon film by ion implantation.
Depositing a high-melting-point metal film made of the same metal as the high-melting-point metal to be ion-implanted on the surface of the film; Reacting a metal film with silicon atoms of the second polycrystalline silicon film to form a refractory metal silicide film; etching away the refractory metal film that has not reacted with silicon atoms; wherein implanting the semiconductor substrate and the opposite conductivity type impurity, the step of changing into a stable crystal structure the refractory metal silicide film by the second rapid thermal annealing, after depositing an interlayer insulating film is formed thereon by And performing a heat treatment to activate impurities of a conductivity type opposite to that of the semiconductor substrate and diffusing the impurities to the semiconductor substrate. 5. The method for manufacturing a semiconductor device according to claim 2, wherein first and second amorphous silicon films are used instead of said first and second polycrystalline silicon films. Manufacturing method of a semiconductor device. 6. The refractory metal or refractory metal film according to claim 3 or 4, wherein Ti, Co, Ni, Zr, V,
A method for manufacturing a semiconductor device, wherein the method is any one of Hf.