KR0144413B1 - Semiconductor device and manufacturing method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and after forming a gate electrode, a source / drain electrode, a capacitor, etc. in a semiconductor device having a memory cell region and an external circuit region, the semiconductor device has a great influence on the characteristics of the semiconductor device Since the metal silicide film or the selective metal film is formed only on the gate electrode and the source / drain electrodes of the MOSFET in the external circuit region, the current driving capability of the semiconductor device is improved, so that the reliability of device operation is improved and the device is highly integrated.

Description

Semiconductor device and manufacturing method

1A to 1E are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.

2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

X: memory cell area Y: external circuit area

1: semiconductor substrate 2: device isolation insulating film

3: gate oxide film 4A, 4B: gate electrode

5A, 5B: Source electrode 5A ', 5B': Drain electrode

6: interlayer insulating film 10: charge preservation electrode

11: dielectric film 12: plate electrode

13: insulating film 20: metal film

60: insulation spacer 200: silicide

300: selective metal film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, in a semiconductor device including a memory cell region and an external circuit region, a metal oxide semi-conductor field effect transistor (hereinafter referred to as a MOS FET) in an external circuit region. The present invention relates to a semiconductor device having a metal silicide or a selective metal film formed only on a gate electrode and a source / drain electrode of a semiconductor device, which improves reliability of device operation and is advantageous for high integration.

As the semiconductor device is highly integrated, the width of the gate electrode of the MOSFET is also reduced. However, when the width of the gate electrode is reduced by N times, the electrical resistance of the gate electrode is increased by N times, thereby reducing the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, a polyside, an redundancy structure showing the most stable MOSFET characteristics, has been put into practical use as a low resistance gate, and a low resistance gate is formed by filling a high melting point metal film such as tungsten on the polysilicon layer.

However, the gate electrode loaded with the high melting point metal has a high melting point metal penetrating into the insulating film due to the spike phenomenon during the formation process of the high melting point metal film to increase the interface level or the fixed charge, and the high temperature heat treatment process after the gate electrode formation. There are problems such as melting of the melting point metal, and to solve this problem, the high melting point metal is highly purified, the method of forming a high melting point metal film is improved, or the heat treatment is performed in an H ₂ O / H ₂ mixed gas atmosphere to prevent oxidation. Etc. are being studied. In general, PN junctions formed of P or N type impurities on N or P type semiconductor substrates are formed by ion implantation of impurities and then activated by heat treatment. Recently, semiconductor devices have been highly integrated to increase density and switching speed of devices. In addition, in order to reduce power consumption, the design rule of the semiconductor device is reduced to 0.5 μm or less. As a result, in order to prevent short channel effects due to side diffusion from the diffusion region, the junction depth is shallow, and the high concentration impurity diffusion region and the low concentration impurity diffusion region are doubled. A source / drain electrode having a lightly doped drain (hereinafter referred to as LDD) structure is formed to prevent a hot electon effect due to concentration of an electric field.

In general, the most important function of the transistors constituting the semiconductor circuit is the current driving capability, and is formed by adjusting the channel width of the MOSFET. The most widely used MOSFET uses a polysilicon layer doped with an impurity as a gate electrode, and a diffusion region doped with impurities on a semiconductor substrate is used as a source / drain electrode.

The sheet resistance of the gate electrode is about 30-70Ω / _□ or so, the sheet resistance of the source / drain electrodes in the case of N + is approximately 70-150Ω / _□, approximately 100-25-Ω / _□ degree for P +, the gate electrode and In the case of a contact formed on a source / drain electrode, the contact resistance is about 30-7-kPa / _□ per contact.

In order to reduce the high sheet resistance and contact resistance of the gate electrode and the source / drain electrodes, the metal silicide layer may be formed only on the gate electrode and the source / drain electrodes by a salicide (self-aligned silicide) method or a selective metal film deposition method. Alternatively, a selective metal film was formed to increase the current driving capability of the MOSFET.

For example, the use of Ti silicide or selective W significantly reduces the sheet resistance of the gate electrode and source / drain electrodes to about 5 mA / _□ and the contact resistance to about 3 mA / _□ or less per contact, resulting in a MOSFET current drive capability of over 40%. This allows for higher integration of the MOSFET.

However, Ti silicide has poor thermal stability at temperatures above 850 ° C, causing degeneration in the heat treatment process, resulting in uneven silicide films, and reducing sheet resistance and contact resistance. The W silicide film forms W silicide by reacting with the silicon layer of W. Although the W silicide film has good contact properties with N-type silicon, its contact properties are very poor with P-type silicon, and thus the contact resistance is not reduced.

Therefore, the salicide structure or the selective metal film deposition method is used only for semiconductor devices capable of minimizing a heat treatment process of 850 ° C or more in a subsequent process after forming the MOSFET.

In the conventional semiconductor device as described above, in the case of a red-chip type DRAM device, after forming a MOSFET, a capacitor is formed. When forming the silicon layer for the charge storage electrode and the silicon layer for the dielectric film and the plate electrode, which are components of the capacitor, Since the heat treatment process is repeated, the salicide structure or the selective metal film deposition method cannot be used.

In the case of SRAM, after forming a MOSFET, a resistor or a thin film transistor is formed. In this case, since the high temperature heat treatment process is repeated, similarly, the salicide structure or the selective metal film deposition method cannot be used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is that the current driving capability of the MOSFET in the external circuit region has a large influence on the performance of the entire semiconductor device in a semiconductor device having a memory cell region and an external circuit region. In view of the above, a silicide film or a selective metal film is formed only on the gate electrode and the source / drain electrode of the MOSFET in the external circuit region to provide a semiconductor device which is advantageous for high integration of the device.

Another object of the present invention is to form a memory region and an external circuit region, and to form a silicide film or a selective metal film only on the gate electrode and the source / drain electrode of the MOSFET in the external circuit region, which is advantageous for semiconductor device manufacturing. In providing.

A semiconductor device according to the present invention for achieving the above object is a semiconductor device having a gate electrode and a source / drain electrode of a MOSFET and having a memory cell region and an external circuit region. The silicide layer or the selective metal layer is formed on the gate electrode and the source / drain electrode of the MOSFET in the region, and the silicide layer or the selective metal layer is not formed on the gate electrode and the source / drain electrode of the MOSFET in the cell region. It is done.

Another aspect of the method for manufacturing a semiconductor device according to the present invention is to form a gate electrode, a source electrode and a drain electrode of a MOSFET on a semiconductor substrate having a memory cell region and an external circuit region, and source / drain in the external circuit region. Forming a charge storage electrode and a dielectric film in contact with the drain electrode, sequentially forming a plate electrode and an insulating film on all surfaces of the cell region and the external circuit region, and forming a photoresist pattern on the cell region. Exposing a gate electrode and a source / drain electrode upper surface in the external circuit region by performing an etching process using the photoresist pattern as a mask, and a gate electrode and a source / drain of the exposed external circuit region. And forming a metal silicide film or a selective metal film on the electrode. It shall be.

Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1E are manufacturing process diagrams of a semiconductor device according to the present invention. Since 1E is a final structural diagram, description will be mainly given for identification.

First, a device isolation insulating film 2 and a gate oxide film 3 are formed on the semiconductor substrate 1 to separate the devices, and then a series of gate electrodes are formed on the memory cell region X and the external circuit region Y. 4A) and 4B. Then, source electrodes 5A, 5B and drain electrodes 5A ', 5B' are formed on the semiconductor substrate 1 on both sides of the gate electrodes 4A, 4B. An interlayer insulating film 6 made of an oxide film is formed on the surface. The source electrodes 5A, 5B and drain electrodes 5A ', 5B' may also be formed in a normal LDD structure (see also FIG. 1A).

Thereafter, a charge storage electrode contact is formed to expose the source electrodes 5A and 5B of the memory cell region X, and the charge storage electrode 10 is brought into contact with the source electrodes 5A and 5B. Is formed of polysilicon, the dielectric film 11 is formed on the surface of the charge storage electrode 10, and then the plate electrode 12 and the insulating film 13 are sequentially formed on the entire surface of the structure.

A photoresist pattern 14 is then formed on the memory cell region X (see also FIG. 1B).

Thereafter, the gate electrode 4B of the MOSFET in the external circuit region Y is sequentially anisotropically etched from the insulating film 13 of the external circuit region Y exposed by the photosensitive film pattern 14 to the interlayer insulating film 6. And the source electrode 5B and the drain electrode 5B 'are exposed, and the photoresist pattern 14 is removed. At this time, insulating spacers 60 are formed on both sides of the gate electrode 4B (see also 1C).

Next, a transition metal capable of silicide formation, for example, a metal film 20 such as Ti, Cr, Mo, W and Nb, is formed on the entire surface of the structure, and heat-treated at a predetermined temperature to form the gate electrode 4B and the source. The metal silicide layer 200 is formed by reacting the silicon layer of the electrode 5B and the drain electrode 5B 'with a metal.

For example, in the case of forming the Ti silicide, the Ti film is formed at about 300-1000 kPa, and the Ti silicide (TiSi ₂ ) is carried out in a gas atmosphere such as nitrogen or argon at a temperature of about 550-650 ° C. To form. If the above heat treatment step is carried out in a nitrogen atmosphere, the portion of Ti that is not in contact with silicon becomes TiN and remains in Ti in an argon atmosphere. (See also 1D).

Thereafter, the metal silicide layer 200 formed on the gate electrode 4B and the source electrode 5B and the drain electrode 5B 'of the external circuit region Y is not etched, and the remaining metal film 20 is not etched. ), The metal silicide layer 200 remains only on the gate electrode 4B, the source electrode 5B, and the drain electrode 5B 'of the external circuit region Y.

Looking at the etching process, for example, first, when the metal film 20 is a Ti film, the selective etching is NH ₄ OH, H ₂ O ₂ , H ₂ O mixed solution is a ratio of 11: 5-1: 1: It is about 10, and it is etched for about 5-30 minutes at a temperature of about 20-50 ° C. In the case of a mixed solution of H ₂ SO ₄ and H ₂ O ₂ , the ratio is about 2: 1-5: 1, 70 Etch for 5-30 minutes at -120 ° C (see also section 1e).

In the case where the insulating film 13 is not formed on the plate electrode 12, a metal silicide film may be formed on the plate electrode 12.

FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. After the process up to FIG. 1c is performed, the gate electrode 4B, the source electrode 5B, and the external circuit region Y are exposed. The selective metal film 300 is formed on the drain electrode 5B '.

As an example of the selective metal film as described above, in the case of the most used W, WF ₆ and H ₂ mixed gas or WF ₆ and SiH ₄ mixed gas are used under low pressure.

Then, an insulating film is formed on the entire surface of the structure by a low temperature deposition method, and interconnection lines necessary for circuit configuration are formed through a minimum heat treatment process to complete a semiconductor device.

Here, if the insulating film 13 is not formed on the plate electrode 12, the selective metal film is also formed on the flake electrode 12 made of the polysilicon layer.

As described above, even when the metal silicide film or the selective metal film is formed only on the gate electrode and the source / drain electrodes of the external circuit region, the characteristics of the semiconductor device are improved. The current driving capability of the MOSFET in the memory cell region is dependent on the product characteristics. It hardly affects, but the current driving ability of the MOSFET that makes up the external circuit area affects the characteristics of the product.

As described above, the semiconductor device and the method of manufacturing the same according to the present invention form a gate electrode, a source / drain electrode, a capacitor, and the like in a semiconductor device including a memory cell region and an external circuit region. Since the metal silicide film or the selective metal film is formed only on the gate electrode and the source / drain electrode of the MOSFET of the external circuit region which have a large influence, the current driving ability of the semiconductor device is improved, thereby improving the reliability of device operation and high integration of the device. There is an advantageous advantage.

Claims (12)

In a semiconductor device having a gate electrode and a source / drain electrode of a MOSFET and having a memory cell region and an external circuit region, a silicide film or a selective metal on the gate electrode and the source / drain electrode of the MOSFET in the external circuit region. A film is formed, and the silicide film or the selective metal film is not formed on the gate electrode and the source / drain electrode of the MOSFET in the cell region. The semiconductor device according to claim 1, wherein the silicide film is made of one metal silicide optionally selected from the group consisting of Ti, W, Ta, Mo, and Nb. The semiconductor device according to claim 1, wherein a metal silicide film is formed on the plate electrode of the memory cell region. The semiconductor device of claim 1, wherein the selective metal film is selective W. 3. Forming a gate electrode, a source electrode, and a drain electrode of a MOSFET on a semiconductor substrate having a memory cell region and an external circuit region; and forming a charge storage electrode and a dielectric film in contact with the source / drain electrodes in the external circuit region. A process of sequentially forming a plate electrode and an insulating film on the entire surface of the cell region and the external circuit region, a process of forming a photoresist pattern on the cell region, and an etching process using the photoresist pattern as a mask. Proceeding to expose the upper surface of the gate electrode and the source / drain electrodes in the external circuit region; and forming a metal silicide film or a selective metal film on the exposed gate and source / drain electrodes of the external circuit region. Method of manufacturing a semiconductor device comprising a. The Ti silicide according to claim 5, wherein when the silicide film is formed of Ti silicide, the Ti film is formed on the entire surface of 300-1000 Pa, and the Ti silicide is formed by performing about 20-30 seconds in an inert gas atmosphere at a temperature of 550-650 ° C. And forming and performing selective etching notarization. The method for manufacturing a semiconductor device according to claim 5, wherein nitrogen or argon is used as a gas during the heat treatment step for forming the Ti silicide film. The method of claim 5, wherein the NH ₄ OH, H ₂ O ₂ , H ₂ O mixed solution, H ₂ SO ₄ , H ₂ O ₂ mixed solution is used in the selective etching process for forming the Ti silicide layer A method of manufacturing a semiconductor device. According to claim 5 or 8, wherein the NH ₄ OH, H ₂ O ₂ , H ₂ O mixed solution is a ratio of 1: 1: 5-1: 1: 10, respectively, of 20-50 ° C A method of manufacturing a semiconductor device, characterized in that the etching for 5-30 minutes at a temperature. The method according to claim 5 or 8, wherein the H ₂ SO ₄ , H ₂ O ₂ mixed solution is a ratio of 2: 1-5: 1, and performs etching 5-30 minutes at a temperature of 70-120 ° C. A method of manufacturing a semiconductor device, characterized in that. 6. The method of claim 5, wherein a metal silicide film is formed over the plate electrode of the memory cell region. The method of claim 5, wherein the selective metal layer is a selective W layer.