JP3226655B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor (T
FT) and a method of manufacturing the same. The thin film transistor manufactured by the present invention is formed on an insulating substrate such as glass and a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Conventionally, when a thin film transistor (top gate type TFT) in which a gate is located on an active layer is manufactured by using laser crystallization or laser activation technology (including flash lamp annealing), After patterning the thin film semiconductor region (active layer) into an island shape, an insulating film is formed as a gate insulating film by a CVD method or a sputtering method, and a gate electrode is formed thereon. Irradiation with a doping impurity (dopant) to form self-aligned impurity regions such as a source region and a drain region in a semiconductor region (using a gate electrode as a mask), followed by laser irradiation, whereby the semiconductor The impurity introduced therein was activated (laser activation).

[0003]

However, such a conventional method has several problems. One is that, during laser activation, some of the impurities in the semiconductor react with the gate insulating film material (such as silicon oxide) present thereon to generate compounds such as phosphorus glass and boron glass. In addition, the non-equilibrium chemical reaction produces a non-stoichiometric semiconductor oxide (such as silicon oxide in which the ratio of oxygen to silicon is not 2: 1), which results in high contact resistance when a contact is formed later. It was to become. In addition, surface irregularities were significant due to the above reaction and the like. As a result, the yield was reduced. The other is that the boundary of the region to be doped with impurities becomes a shadow of the gate electrode portion, activation of the boundary portion is insufficient, characteristics are unstable, and reliability is deteriorated. An example will be described below.

FIG. 5 shows an example of a conventional laser activation technique. First, a base insulating film (such as silicon oxide) is formed on the substrate 50.
Then, an island-shaped crystalline semiconductor region (silicon or the like) 52 is formed. Further, the CVD
A gate insulating film (such as silicon oxide) 53 is formed by a method such as a sputtering method or a sputtering method, and a gate electrode (such as phosphorus-doped silicon, aluminum, or tantalum) 54 is further formed. (FIG. 5 (A))

[0005] After doping with impurities, the impurity regions 55a and 55b are activated by irradiating with strong light such as a laser. In this case, due to the instantaneous high temperature state, a chemical reaction occurs at the interface between the semiconductor and the gate insulating film indicated by P in the figure, and the insulating film material such as phosphorus glass (or boron glass) as pointed out above is used. The dopant material combines. In addition, silicon oxide and silicon combine to form silicon oxide having a non-stoichiometric ratio. (FIG. 5 (B))

FIG. 6 is also an example of a conventional laser activation technique. However, unlike the case of FIG. 5, an anodic oxide 65 of the gate electrode is formed around the gate electrode. Such an anodic oxide causes an offset state in which the gate electrode and the impurity (to be introduced) region are separated by a distance X, and the electrical characteristics of the TFT (such as a leak current when a reverse bias is applied to the gate). Improvement can be achieved.
(FIG. 6 (A))

However, in this case, Q in FIG.
In the places indicated by, the crystallinity is destroyed by the high-speed doping impurities, but the laser light irradiation is not sufficient, so that the activation is not performed, a large number of trap levels are generated, and the characteristics of the TFT are impaired. Is reduced. (FIG. 6B) An object of the present invention is to solve such a problem.

[0008]

According to the present invention, the above problem is solved by performing doping with the gate insulating film attached, and removing and activating the gate insulating film in the subsequent laser activation step. I do. However, when removing the gate insulating film, there is a high possibility that the underlying oxide film and the substrate will be etched at the same time.
The present invention is characterized in that a mask is used particularly for impurity introduction, and then the gate insulating film and the like are selectively etched using the mask.

As a result, the reaction between the semiconductor and the insulating film could be prevented without lowering the yield during doping and also in the laser activation step.
In a TFT having a structure in which an offset is formed by using an anodic oxide as shown in FIG. 6, if a part of the anodic oxide is simultaneously etched in the step of etching the gate insulating film, doping is performed. It is also possible to irradiate the laser beam at the boundary of the region. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0010]

[Embodiment 1] FIG. 1 is a sectional view showing a manufacturing process of this embodiment. A 200 nm thick silicon oxide base film 11 was formed on a substrate (Corning 7059) 10 by sputtering. Furthermore, by plasma CVD was deposited thickness 2 0 to 20 0 nm, for example 15 0 nm amorphous silicon film. Subsequently, by sputtering, depositing a silicon oxide film having a thickness of 2 0 to 10 0 nm as a protective film. Then, in a reducing atmosphere, 5
Annealing was performed at 00 to 600 ° C., for example, at 600 ° C. for 48 hours for crystallization. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form island-shaped silicon regions 12.

[0011] Next, the thickness of 8 5 by sputtering
~ 15 0 nm, depositing a silicon oxide film 13 of, for example, 10 0 nm as a gate insulating film, subsequently, by low pressure CVD, the thickness of 60 0 to 80 0 nm, for example 60 0 nm silicon film (of 0.01% to 2% Containing phosphorus).
It is desirable that the step of forming the silicon oxide and the silicon film be performed continuously. Then, the gate electrode 14 was formed by patterning the silicon film. (Figure 1
(A))

Next, after masking a region other than the semiconductor region 12 with the photoresist 15, a photoresist mask 15 is formed on the silicon region 12 by a plasma doping method.
Then, impurities (phosphorus) were implanted using the gate electrode 14 as a mask. The doping pattern at this time is shown in FIG.
The shape was as shown in FIG. As a doping gas,
Using phosphine (PH ₃ ), the accelerating voltage is 60 to 11
0 kV, for example, 80 kV. Dose amount is 1 × 10 ¹⁵
５5 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻² .
As a result, N-type impurity regions 16a and 16b were formed in self-alignment with the gate electrode 14. (Figure 1
(B))

After the impurity doping step is completed, the exposed portion of the silicon oxide film 13 is etched with hydrofluoric acid with the mask 15 attached. At this time, it should be noted that the silicon oxide 11 of the base insulating film is also partially etched. After the completion of the etching step, the resist was removed.

Then, the impurities were activated by laser irradiation. As a laser, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 to 40 nsec) was used.
3 nm), XeCl excimer laser (wavelength 308 n)
m), an ArF excimer laser (wavelength 193 nm) or the like may be used. The energy density of the laser is 250
400 mJ / cm ² , for example, 300 mJ / cm ^2, and ² to 10 shots, for example, 2 shots may be applied to one location. During laser irradiation, the substrate is
You may heat to about 50 degreeC. It should be noted that the optimal laser energy density changes when the substrate is heated. (Fig. 1 (D))

[0015] After activation of impurities, followed by, thickness 50 0
A silicon oxide film 17 having a thickness of 800 nm , for example, 600 nm is formed as an interlayer insulator by a plasma CVD method, a contact hole is formed in the silicon oxide film 17, and a metal material, for example, titanium nitride (100 to 200 nm , for example, 100 nm ) is formed. And aluminum ( 500-1000 nm , for example, 800n)
The wirings 18a and 18b were formed by the multilayer film of m ).
And 0.1 to 1 atm, 250 to 400 ° C., for example, 1
Annealing was performed in a hydrogen atmosphere at a pressure of 350 ° C. for 30 to 120 minutes, for example, 30 minutes. Through the above steps, an NMOS semiconductor circuit was completed. (FIG. 1 (E))

[Embodiment 2] FIG. 2 is a cross-sectional view showing a manufacturing process of this embodiment. First, the substrate (Corning 7059) 2
A silicon oxide base film 21 having a thickness of 200 nm was formed on the substrate 0 by sputtering. Furthermore, by plasma CVD was deposited thickness 2 0 to 20 0 nm, for example 10 0 nm amorphous silicon film. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form island-like silicon regions 22. The size of one island-shaped silicon film was 30 μm × 30 μm.

[0017] Next, the thickness 8 0 by sputtering
~ 15 0 nm, for example, 10 0 nm of the silicon oxide film 13 is deposited as a gate insulating film, subsequently, by sputtering, the thickness 30 0 to 60 0 nm, for example 60 0n
m of aluminum film (containing 2% silicon) was deposited. It is desirable to add 0.5 to 5% of silicon or 0.2 to 2% of copper to aluminum. This is because hillocks are generated if these impurities are not included, since a heat treatment at 250 to 350 ° C. is performed in a later step. Note that it is desirable that the step of depositing silicon oxide and aluminum be performed continuously. Further, when the aluminum film was subjected to a heat treatment at 100 to 300 ° C. after the film formation, the generation of hillocks could be suppressed.

Then, the gate electrode 24 was formed by etching the aluminum film with phosphoric acid. Furthermore, after applying a photo nice (photosensitive polyimide), this is patterned, and it is 250 to 350 ° C., for example, 300 ° C.
To selectively form a polyimide mask (for anodic oxidation). This mask may be provided in a place where a contact is formed later or a place where the wiring is divided. (The polyimide mask is not shown in the figure.)

Subsequently, anodic oxidation is performed. Tartaric acid is dissolved in ethylene glycol, and 1 to 5%, for example, 3%
Solution, and add an aqueous ammonia solution to the solution to adjust the pH.
Was set to about 7. Anodization was started by passing a current through the wiring 24 using the platinum mesh electrode as a cathode and the substrate 10 as an anode.

Initially, the voltage is 3-6 V / min, for example, 4 V / min.
The current flows so that the voltage rises in
When the voltage reaches 250 V, for example, 220 V, the voltage rise is stopped, the voltage is kept constant, and the current is 20 μA / cm∧ (2
). As a result, the thickness 150
Up to 300 nm , for example 200 nm of aluminum oxide 2
5 was formed. The presence of the polyimide mask (not shown) was not anodized due to its masking effect. The time required for anodization was 40-70 minutes, typically 55 minutes. (Fig. 2 (A))

Next, a photoresist mask 26 was patterned except for the island-shaped silicon region 22. The patterning shape at this time is shown in FIG.
The one shown in (C) was adopted. That is, at the portion where the step of the silicon region 22 and the gate electrode 24 intersect,
The configuration is such that doping is not performed.

The gate insulating film 23 at such a stepped portion
Because of poor coverage and thinness, defects such as pinholes occur frequently, and a parasitic TFT is generated along the step, resulting in a problem of leakage current. By adopting such a doping pattern, the step does not become a part of the TFT, so that the leak current and the like can be significantly reduced.

Then, using this mask, impurities (phosphorus or boron) were implanted into the silicon region 22 by a plasma doping method. When phosphorus is implanted, phosphine (PH ₃ ) may be used as a doping gas, and the acceleration voltage may be set to 65 to 100 kV, for example, 80 kV.
When boron is implanted, diborane (B ₂ H ₆ ) is used as a doping gas and the acceleration voltage is set to 50 to 80 k.
V, for example, 65 kV. Dose amount is 1 × 10
^{15 to} 5 × 10 ¹⁵ cm ⁻² , for example, 3 × 10 ¹⁵ cm ⁻² . In this manner, impurity region 27 is self-aligned with the gate electrode portion (gate electrode 24 and anodic oxide 25).
a and 27b were formed. The impurity region and the gate electrode 24 are separated from each other by a distance Y in the horizontal direction (offset state). (FIG. 2 (B))

Next, using the mask 26, a part of the silicon oxide film 23 was etched. After the completion of the etching step, the mask 26 was removed. When the pattern of the mask 26 exposes a portion other than the semiconductor region 22 as shown in FIG. 3A, the underlying silicon oxide film is etched in the same manner as in the first embodiment (X in FIG. 1D). However, such a problem did not occur when the exposed portion was limited to only the semiconductor region 22 as shown in FIG. According to the respective patterns, T after etching the gate insulating film 23 is obtained.
The state of the FT is shown in FIGS. FIG.
FIG. 3C shows a cross section of the TFT shown in FIG.
Notably, at this time, the anodic oxide (aluminum oxide) 25 is also etched and receded by the distance Z, so that the boundary of the impurity region is exposed. (Fig. 2 (C))

Further, the implanted impurities were activated by laser annealing. In this process,
Laser light was also applied to the boundary of the impurity region, and sufficient activation was performed. The laser used was a KrF excimer laser (wavelength 248 nm, pulse width 20 ns)
In c), the energy density on the irradiation surface is 250 to 400 m
J / cm ² , for example, 300 mJ / cm ² . At the time of laser irradiation, the substrate is heated to 200 to 400 ° C., for example, 300 ° C.
It may be heated to ° C.

[0026] Then, thickness 50 0 to 80 0nm, for example 50, a silicon oxide film 28 of 0nm formed by a plasma CVD method as an interlayer insulator, furthermore, the thickness of 5 0 to 15 0nm by sputtering, for example, 8 0nm The indium tin oxide (ITO) film was deposited, and this was patterned to form a pixel electrode (ITO) 29. Further, contact holes were formed in the interlayer insulator 28, and the wirings 30a and 30b were formed using a metal material, for example, a multilayer film of titanium nitride and aluminum. And 0.1
To 1 atm, 250 to 400 ° C, for example, 1 atm, 350 ° C
In the hydrogen atmosphere for 30 to 120 minutes, for example, 30 minutes. The semiconductor circuit was completed by the above steps. (FIG. 2 (D))

[Embodiment 3] FIG. 4 is a sectional view showing a manufacturing process of this embodiment. A 200-nm- thick silicon oxide base film 41 was formed on a substrate (Corning 7059) 40 by sputtering. Furthermore, by plasma CVD was deposited thickness 2 0 to 20 0 nm, for example 15 0 nm amorphous silicon film. Subsequently, by sputtering, the thickness 2 0 to 10 0 nm, for example, 2 0 nm
Was deposited as a protective film. Then, this was annealed at 600 ° C. for 48 hours in a reducing atmosphere to be crystallized. The crystallization step may be a method using strong light such as a laser. Then, the obtained crystalline silicon film was patterned to form island-shaped silicon regions 42P and 42N.

[0028] Next, the thickness 8 0 by sputtering
~ 15 0 nm, for example, 10 0 nm silicon oxide film 43 is deposited as a gate insulating film, subsequently, by sputtering, the thickness 30 0 to 60 0 nm, for example 60 0n
m of aluminum film (containing 1-5% silicon) was deposited. It is desirable that the step of forming the silicon oxide and the aluminum film be performed continuously. Then, the aluminum film is patterned to form the gate electrodes 44P, 44P.
Forming a N, Example 2 in the same manner as in anodization the thickness 15 0 to 30 0 nm the surface, for example, 20 0 nm anodic oxide (aluminum oxide) 45P, were coated with 45N. (FIG. 4 (A))

Next, only the semiconductor region 42N was exposed, and the other portions were masked with a photoresist 46N. And
Impurities (phosphorus) were implanted into the silicon region 42N by using the photoresist mask 46N and the gate electrode portion (the gate electrode 44N and the anodic oxide 45N) as a mask by a plasma doping method. Fig. 3 Doping pattern
The shape was as shown in FIG. Phosphine (PH ₃ ) was used as the doping gas, and the accelerating voltage was 65
１１０110 kV, for example, 80 kV. Dose amount is 1 ×
10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, an N-type impurity region 47N was formed. After the end of the doping, a part of the silicon oxide film 43 was etched using the mask 46N. (FIG. 4 (B))

Further, this time, only the semiconductor region 42P is exposed, and other portions are masked with a photoresist 46P, and the silicon region 42P is formed by plasma doping.
An impurity (boron) was implanted into P. Also in this case, the doping pattern was shaped as shown in FIG. As the doping gas, diborane (B ₂ H _6), the accelerating voltage 50～80KV, for example, 65 kV. The dose was 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, a P-type impurity region 47P was formed. After the doping, the mask 46P
Was used to partially etch the silicon oxide film 43.
(FIG. 4 (C))

Thereafter, the introduced impurities were activated by laser irradiation. Kr as laser
An F excimer laser (wavelength 248 nm) was used,
In addition, XeF excimer laser (wavelength 353 nm),
XeCl excimer laser (wavelength 308 nm), Ar
An F excimer laser (wavelength 193 nm) or the like may be used. Laser energy density is 250-400m
J / cm ² , for example, 280 mJ / cm ^2, and ² to 10 shots, for example, 2 shots were irradiated at one location.

[0032] After activation of impurities, followed by, thickness 50 0
A silicon oxide film 48 having a thickness of 800 nm , for example, 600 nm is used as an interlayer insulator to be a TEOS (tetraethoxysilane, S
i (OC ₂ H ₅ ) ₄ ) is formed by a plasma CVD method, a contact hole is formed therein, and wirings 49 a, 49 b, 49 c, 49 d are formed by a metal material, for example, a multilayer film of titanium nitride and aluminum. Was formed.
Then, in a hydrogen atmosphere of 0.1 to 1 atm and 250 to 400 ° C, for example, 0.1 atm and 350 ° C, 30 to 120 atm.
Annealing, for example, for 30 minutes. Through the above steps, a CMOS semiconductor circuit was completed. (FIG. 4
(D))

[0033]

According to the present invention, it is possible to improve the yield of TFTs, increase the reliability thereof, and extract the maximum characteristics. In addition, in obtaining such a great effect, there is a great advantage that the method can be implemented without particularly large process change, investment, and technological development. In the present invention, a TFT on an insulating substrate has been described as an example.
Needless to say, the present invention can be applied to a TFT formed on a single crystal semiconductor substrate. As described above, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a TFT of Example 1.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a TFT of Example 2.

FIG. 3 shows a doping pattern and the like of a TFT of Example 2.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT of Example 3.

FIG. 5 shows a cross-sectional view of a manufacturing process of a conventional TFT.

FIG. 6 is a cross-sectional view showing a manufacturing process of a conventional TFT.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate (Corning 7059) 11 ... Base insulating film (silicon oxide) 12 ... Island-shaped semiconductor region (silicon) 13 ... Gate insulating film (silicon oxide) 14 ... Gate electrode (silicon) 15 ... mask (photoresist) 16 ... impurity region (source, drain) 17 ... interlayer insulator (silicon oxide) 18 ... source electrode, drain electrode (titanium nitride / aluminum) 20 ... -Substrate (Corning 7059) 21 ... Base insulating film (silicon oxide) 22 ... Island-like semiconductor region (silicon) 23 ... Gate insulating film (silicon oxide) 24 ... Gate electrode (aluminum) 25 ..Anodic oxide (aluminum oxide) 26 ... mask (photoresist) 27 ... impurity region (source, drain) 28 ... interlayer insulator (silicon oxide) ) 29 ... pixel electrode (ITO) 30 ... source electrode, the drain electrode (titanium nitride / aluminum)

Claims (4)

(57) [Claims] (1) Forming an island-shaped thin film semiconductor, Forming an insulating film on the island-shaped thin film semiconductor, Forming a gate electrode portion on the insulating film, A part of the gate electrode part and the island-shaped thin film semiconductor;
Set a mask so that it does not overlap, Introducing impurity ions into the island-shaped thin film semiconductor, Using the mask, selectively removing the insulating film; Thin film transistor characterized by irradiating laser or strong light
How to make a transistor. 2. The device according to claim 1, wherein said gate electrode portion comprises:
A method for manufacturing a thin film transistor, wherein a surface of a gate electrode formed of a conductive material is covered with an oxide of the conductive material. 3. An apparatus according to claim 1 or 2, a method for manufacturing a thin film transistor, wherein the material constituting the gate electrode portion is a material mainly composed of aluminum. 4. In any one of claims 1 to 3, before
A method for manufacturing a thin film transistor, wherein the insulating film is removed by wet etching with a solution containing hydrofluoric acid.