KR0185822B1 - Method for fabricating mis semiconductor device - Google Patents

Abstract

An object of the present invention is to manufacture a highly reliable MIS semiconductor device by a low temperature process. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor device, wherein an impurity region is selectively formed on a semiconductor substrate or a semiconductor thin film, and not only the impurity region but also the laser light or the equivalent intensity thereof at the boundary between the impurity region and an active region adjacent thereto. It is made to irradiate, and it activates by the light irradiation. It is characterized by the above-mentioned.

Description

Semiconductor device

The present invention relates to a metal insulator semiconductor (MIS) type semiconductor device (also referred to as an insulated gate type semiconductor device). MIS semiconductor devices include, for example, MOS transistors, thin film transistors, and the like.

Conventionally, MIS semiconductor devices have been fabricated using a self-aligning (self-aligned) method. According to this method, a gate wiring (electrode) is formed on a semiconductor substrate or a semiconductor film with a gate insulating film interposed therebetween, and impurities are introduced into the semiconductor substrate or the semiconductor film using the gate wiring as a mask. As means for introducing impurities, methods such as thermal diffusion method, ion implantation method, plasma doping method and laser doping method are used. By such means, the edges of the gate electrodes and the edges of the impurity regions (source and drain) are almost coincident with each other, so that the overlap state (cause of parasitic capacitance generation) where the gate electrode and the impurity region overlap, and the gate electrode and the impurity region It is possible to eliminate the offset state (causing the decrease in effective mobility) that is apart.

However, in the conventional process, the spatial variation of the impurity region and the carrier concentration in the active region (channel formation region) adjacent to the impurity region and below the gate electrode is so large that a remarkably large electric field is generated, in particular, the gate electrode. There is a problem that the leakage current (off current) increases when a reverse bias voltage is applied to the circuit.

The inventors of the present invention have found that this problem can be improved by slightly offsetting the gate electrode and the impurity region. Therefore, in order to realize this offset state, the gate electrode is formed of an anodizable material and impurities are introduced using the resulting anodization film as a mask as a result of the anodization, so that an offset state of a constant size can be obtained with good reproducibility. I found that.

In addition, in a method such as an ion implantation method or a plasma doping method in which impurities are introduced by irradiating high-speed ions to a semiconductor substrate or a semiconductor film, the crystallinity of the semiconductor substrate or the semiconductor film in a portion where ions have penetrated is impaired. Improvement (activation) of crystallinity is required. Up to now, thermal crystallinity has been mainly improved at a temperature of 600 ° C or higher, but in recent years, a tendency for the process to be lowered has become evident. Therefore, the present inventors have shown that activation can also be performed by irradiating laser light or a strong light equivalent thereto and that its mass productivity is excellent.

2 shows a thin film transistor fabrication process based on the above concept. First, a base insulating layer 202 is deposited on the substrate 201, and then an island-shaped crystalline semiconductor region 203 is formed, and an insulating film 204 serving as a gate insulating film is formed thereon. The gate wiring 205 is then formed using an anodizable material (FIG. 2 (a)).

Next, the gate wiring is anodized to form an anode oxide 206 having an appropriate thickness of, for example, 300 nm or less, preferably 250 nm or less, on the surface of the gate wiring. Then, using the anode oxide as a mask, impurities (for example, phosphorus (P)) are irradiated self-aligned by an ion implantation method or an ion doping method to form an impurity region 207 (Fig. (B). ))

Thereafter, a laser beam or a strong light equivalent thereto is irradiated from above to activate a region into which impurities are introduced (Fig. 2 (c)).

Finally, the interlayer insulator 208 is deposited, contact holes are formed in the impurity region, and the electrode 209 connected to the impurity region is formed, thereby completing the thin film transistor (FIG. (D)).

However, in the above method, the physical properties at the boundary between the impurity region and the active region (a semiconductor region disposed between the impurity regions immediately below the gate electrode) (indicated by X in Fig. 2 (c)) are unstable. It has been found that problems such as an increase in leakage current and a decrease in reliability in long time use may occur. That is, as is apparent from the process, the crystallinity of the active region does not substantially change from the beginning. On the other hand, the impurity region adjacent to the active region initially has the same crystallinity as the active region, but crystallinity is destroyed in the process of introducing a large amount of impurities (up to 10 ⁵ cm ⁻² ). In addition, although the impurity region recovers in a later laser light irradiation process, it is difficult to reproduce the same crystalline state as the original, and in particular, the portion of the impurity region in contact with the active region tends to be shaded when irradiated with laser light, so that it is sufficiently activated. It turned out that

That is, the crystallinity of the impurity region and the active region is discontinuous, and therefore, the trap level is likely to occur. In particular, when a method of irradiating high-speed ions as the impurity introduction method is employed, impurity ions return to the bottom of the gate electrode part by scattering, and destroy the crystallinity of the portion. Therefore, the area under the gate electrode part is shaded by the gate electrode part, and it is impossible to activate the area by laser light or the like.

One way to solve this problem is to irradiate light, such as laser light, from the back side to activate the portion. In this method, since the boundary between the active region and the impurity region is not shaded by the gate wiring, the boundary is also sufficiently activated. In this case, however, it is necessary for the substrate material to transmit light, and of course, this method cannot be used when a silicon wafer or the like is used. In addition, since many glass substrates do not transmit ultraviolet light of 300 nm or less, for example, KrF excimer laser (wavelength 248 nm) having excellent mass productivity cannot be used.

Accordingly, it is an object of the present invention to solve such problems and to obtain a highly reliable MIS type semiconductor device such as a MOS transistor and a thin film transistor by achieving continuity of crystallinity between an active region and an impurity region.

1 (a) to 1 (e) are sectional views showing the first embodiment of the present invention.

2 (a) to 2 (d) are cross-sectional views showing examples of the prior art.

3 (a) to 3 (f) are cross-sectional views showing a second embodiment of the present invention.

4A to 4C are plan views showing a second embodiment of the present invention.

5 (a) to 5 (f) are sectional views showing the third embodiment of the present invention.

6 (a) to 6 (e) are sectional views showing the fourth embodiment of the present invention.

7 (a) to 7 (f) are sectional views showing the fifth embodiment of the present invention.

8 (a) to 8 (f) are sectional views showing the sixth embodiment of the present invention.

Fig. 9 is a block diagram of an integrated circuit using the sixth embodiment.

* Explanation of symbols for main parts of the drawings

101 substrate 102 silicon oxide film

103: amorphous silicon film 104: gate insulating film

105: gate electrode 106: first anode oxide

107 impurity region 108 second anode oxide

109: interlayer insulation 110: electrode

311 polyimide film 706 photoresist mask

707: porous anode oxide 708: barrier type anode oxide

According to the present invention, when irradiating light energy generated from a powerful light source such as a laser or a flash lamp to an impurity region from above to activate the impurity region, not only the impurity region but also a portion of the active region adjacent thereto, especially an impurity region and an active region Light energy is also irradiated to the boundary between the regions. In order to achieve such an object, a part of the material constituting the gate electrode portion is removed before or after the impurity is introduced, so that the boundary portion thereof is substantially transparent to the irradiated light.

A method of fabricating a semiconductor device according to the present invention includes the steps of forming a gate wiring (gate electrode) of an anodized material after forming an insulating film serving as a gate insulating film on a crystalline semiconductor substrate or a semiconductor film, and the gate Anodizing the wiring to form an anode oxide (first anode oxide) on its surface, and a portion defined by a gate electrode portion or a gate electrode portion made of an anodizable material and an anode oxide thereof. A process of introducing impurities into the semiconductor substrate or the semiconductor film in a self-aligning manner as a mask, and removing part or all of the first anode oxide before or after the impurity introduction process, and at or near the boundary between the impurity region and the active region The light energy can be irradiated, and the light energy is irradiated in this state to activate the impurity region. It includes forward.

If necessary, the gate electrode is again anodized to cover the surface with a highly insulating anode oxide (second anode oxide), and an interlayer insulator or the like is provided to reduce the capacitive coupling with the upper wiring. Not to mention that it is good. In the anodic oxidation, a wet method usually using an electrolytic solution is used, but other known reduced pressure plasma method (dry method) may be used. In addition, the anode oxide obtained by the wet method may be a dense barrier type having a high internal pressure, or a porous type having a porous and low internal pressure, and these may be appropriately combined.

Preferred anodizable materials used in the present invention include aluminum, titanium, tantalum, silicon, tungsten and molybdenum. A single electrode or an alloy of these materials may be a single layer or a multilayer structure to form a gate electrode. It goes without saying that a small amount of other elements may be added to these materials. It goes without saying that the wiring may be oxidized by any suitable oxidation method other than anodization.

As a source of light energy used in the present invention, excimer lasers such as KrF laser (wavelength 248 nm), XeCl, laser (wavelength 308 nm), ArF laser (wavelength 193 nm), XeF laser (wavelength 353 nm); Coherent light sources such as Nd: YAG laser (wavelength 1064 nm) and its second, third and fourth harmonics, carbon dioxide lasers, argon ion lasers and copper vapor lasers; And incoherent light sources such as xenon flash lamps, krypton arc lamps, halogen lamps are suitable.

The MIS semiconductor device obtained through this process has a substantially identical shape (similar to that of the junction of the impurity regions (source and drain) and the gate electrode portion (including the gate electrode and the anode oxide accompanying it) when viewed from above. Form), and the gate electrode (combined by the conductive surface, not including ancillary materials such as anodized oxide) and the impurity region are offset.

In the case where the oxide does not have the same oxide as the second anode oxide, there is no anode oxide around the gate electrode, and the impurity region and the gate electrode are offset.

As for the width of an offset, 0.1-0.5 micrometer is preferable.

In the present invention, after forming the first anode oxide, a portion thereof is left, and the upper wiring is formed with the remaining portion interposed therebetween, so that a capacitor having the first anode oxide as an insulating material may be formed. In this case, the thickness of the anode oxide of the gate electrode portion and the oxide of the capacitor portion of the portion serving as the gate electrode of the MIS type semiconductor device may be different, and each thickness may be determined according to the respective purpose.

Similarly, in the process of forming an oxide like the second anode oxide, the thickness of the anode oxide can be changed even on the same substrate by, for example, adjusting the applied voltage per wiring. Also in this case, the thickness of the oxide such as the anode oxide of the gate electrode portion may be different from the thickness of the oxide of the capacitor (or the portion where the wiring intersects).

Hereinafter, an Example is shown and this invention is demonstrated in detail.

First embodiment

1 shows a first preferred embodiment of the present invention. In this embodiment, a thin film transistor is formed on an insulating substrate. The substrate 101 may be a glass substrate, for example, an alkali free glass substrate or a silica substrate such as Corning 7059. In view of the cost, a Corning 7059 substrate was used here. A silicon oxide film 102 was deposited on the substrate as a base oxide film. As the deposition method of the silicon oxide film, a sputtering method or a chemical vapor deposition method (CVD method) can be used. Here, film formation was performed by plasma CVD method using TEOS (tetraethoxysilane) and oxygen as the source gas. Substrate temperature was 200-400 degreeC. The thickness of the underlying silicon oxide film was 500 to 2000 mm 3.

Next, an amorphous silicon film 103 was deposited and patterned into islands.

As the deposition method of the amorphous silicon film 103, a plasma CVD method or a reduced pressure CVD method can be used. Here, an amorphous silicon film was deposited by plasma CVD using monosilane (SiH ₄ ) as a source gas. The thickness of the amorphous silicon film 103 was 200-700 GPa. Subsequently, laser light (KrF laser: wavelength 248 nm, pulse width 20 nsec) was irradiated to this. Before laser light irradiation, the board | substrate was heated at 300-550 degreeC for 1-3 hours in vacuum, and the hydrogen contained in the amorphous silicon film was discharge | released. The energy density of the laser light was 250-450 mJ / cm 2. At the time of laser beam irradiation, the board | substrate was heated at 250-550 degreeC. As a result, the amorphous silicon film crystallized into a crystalline silicon film.

Next, a silicon oxide film serving as the gate insulating film 104 was formed to a thickness of 800 to 1200 kPa. As the method for forming the silicon oxide film, the same method as that for forming the underlying silicon oxide film 102 was adopted. Next, the gate electrode 105 was formed using an anodizable material, that is, a metal such as aluminum, tantalum, titanium, a semiconductor such as silicon, or a conductive metal nitride such as tantalum nitride and titanium nitride. Here, tantalum was used, and its thickness was 2000-10000 mm (FIG. 1 (a)).

Thereafter, the gate electrode was anodized to form an anode oxide (first anode oxide) 106 having a thickness of 1500 to 2500 GPa on the surface thereof. Anodization is carried out by immersing the substrate in an ethylene glycol solution with 1-5% citric acid, integrating all the gate wirings as anodes and platinum as cathodes, increasing the applied voltage to 1-5V / min. It became. Next, boron (B) or phosphorus (P) ions were irradiated by plasma doping to form an impurity region 107. The acceleration energy of the ions is changed depending on the thickness of the gate insulating film 104, but in general, when the thickness of the gate insulating film is 1000 mW, the acceleration energy of 50 to 65 keV in boron and 60 to 80 keV in phosphorus is appropriate. Further, the dose amount is ^{2 × 10 14 ~ 6 × 10} 15 cm ^-2 but are suitable, it has been found that lower the dose that is highly reliable device produced amount. As a result of impurity introduction in the state where the anodic oxide is present, the gate electrode (tantalum) and the impurity region are offset. In addition, the range of the impurity region shown in the figure is nominal, and it is natural that the ions actually return by scattering or the like (Fig. 1 (b)).

After the completion of the impurity doping, only the first anode oxide 106 was etched. Etching was performed in a plasma atmosphere of carbon tetrafluoride (CF ₄ ) and oxygen. The ratio of carbon tetrafluorocarbon (CF ₄ ) to oxygen (flow rate) was CF ₄ / O ₂ = 3 to 10. Under these conditions, tantalum pentoxide, which is an anode oxide of tantalum, is etched, but silicon oxide is not etched. As a result, only the first anode oxide 106 can be etched without etching the silicon oxide film serving as the gate electrode 105 and the gate insulating film 104. As a result, as shown in Fig. 1C, a boundary (denoted by X) between the impurity region 107 and the active region between the impurity regions appears. Then, in this state, the impurity region was activated by laser light irradiation. The laser used was a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec), and the energy density of the laser was 250-450 mJ / cm 2. In addition, when the substrate is heated to 250 to 550 ° C. during laser light irradiation, the impurity region may be activated more effectively. Typically, in the phosphorus doped impurity region, a sheet resistance of 500 to 1000 Ω / □ is obtained when the dose is 1 × 10 ¹⁵ cm ⁻² , the substrate temperature is 250 ° C., and the laser energy is 300 mJ / cm 2. lost.

In addition, in this embodiment, since the boundary between the impurity region and the active region (indicated by X) is also irradiated with laser light, the decrease in reliability due to deterioration of the boundary portion, which is a problem in the conventional manufacturing process, is significantly reduced. It became. In addition, in this process, since the laser beam is irradiated to the exposed gate wiring (gate electrode), it is preferable that the surface of the wiring sufficiently reflects the laser beam or the wiring itself has sufficient heat resistance. Tantalum has no problem because its melting point is 3000 ° C. or higher, but care must be taken when using a low melting point material such as aluminum, for example, it is desired to provide a heat resistant material on the upper surface (FIG. 1 (c)).

Thereafter, an electric current was applied to the gate wiring again to perform anodization to form an anode oxide (second anode oxide) 108 having a thickness of 1000 to 2500 mW. Since the second anode oxide 108 determines the size of the offset of the thin film transistor by preventing the conductive surface from retreating and short-circuit with the upper wiring, a thickness appropriate for the purpose needs to be selected. Of course, in some cases, such an anode oxide may not be formed (Fig. 1 (d)).

Finally, a plasma oxide CVD method using TEOS as the source gas, for example, forms a silicon oxide film with a thickness of 2000 to 10000 GPa as the interlayer insulator 109, forms a contact hole therein, and a titanium nitride of 200 GPa and A thin film transistor was completed by connecting the electrode 110, which is a multilayer film of 500 Å aluminum, to an impurity region (Fig. 1 (e)).

Second embodiment

3 and 4 show a second embodiment. 3 is a cross-sectional view taken along the dashed-dotted line in FIG. 4 (plan view). First, a base silicon oxide film was formed on a substrate (Corning 7059) 301, and an amorphous silicon film was formed to a thickness of 1000 to 1500 kPa. Then, the amorphous silicon film was crystallized by annealing at 600 ° C. for 24 to 48 hours in nitrogen or argon atmosphere. Thus, island-like crystalline silicon regions 302 were formed. Then, a silicon oxide film serving as the gate insulating film 303 was deposited to a thickness of 1000 mW to form tantalum wiring (thickness 5000 m) (304, 305 and 306) (Fig. 3 (a)).

Subsequently, a current was applied to these wirings 304 to 306 to form first anode oxides 307, 308, and 309 having a thickness of 2000 to 2500 Å on their surfaces. Using the wiring thus treated as a mask, impurities were introduced into the island-like silicon regions 302 by plasma doping to form the impurity regions 310 (Figs. 3 (b) and 4 (a)).

Then, only the first anode oxides 307 to 309 were etched to expose the surface of the wiring, and in that state, the KrF excimer laser light was irradiated to activate the impurity region (Fig. 3 (c)).

After that, the polyimide film 311 having a thickness of 1 to 5 탆 was provided only in the portion of the wiring 306 to form the contact hole among the wirings. As the polyimide, the photosensitive polyimide can be easily used due to the ease of patterning (Fig. 3 (d) and Fig. 4 (b)).

Subsequently, a current was applied to the wirings 304 to 306 in this state to form second anode oxides 312, 313, 314 having a thickness of 2000 to 2500 Å. The portion where the polyamide has already been provided is not anodized and the contact hole 315 remains (Fig. 3 (e)).

Finally, as the interlayer insulator 316, a silicon oxide film having a thickness of 2000 to 5000 kPa was deposited to form a contact hole. In the portion 319 enclosed by a dotted line in a part of the wiring 305 (FIG. 4C), all of the interlayer insulators were removed to expose the second anode oxide 313. Next, wirings and electrodes 317 and 318 using a multilayer film of tantalum nitride (thickness 500 mW) and aluminum (thickness 3500 mW) were formed to complete the circuit. At this time, the wiring 318 forms a capacitor together with the wiring 305 at the portion 319 and is connected to the wiring 306 at the contact 320 (FIGS. 3F and 4C).

Third embodiment

5 shows a third embodiment. After the underlying silicon oxide film was formed on the substrate (Corning 7059) 501, an amorphous silicon film was formed to a thickness of 1000 to 5000 GPa. And an amorphous silicon film was crystallized by annealing at 600 degreeC for 24 to 48 hours in nitrogen or argon atmosphere. Thus, island-like crystalline silicon regions 502 were formed. Further, a silicon oxide film functioning as the gate insulating film 503 was deposited to a thickness of 1000 mW to form tantalum wiring (thickness 5000 m) (504, 505, 506) (Fig. 5 (a)).

Subsequently, a current was flowed through these wirings to form anodized oxide films 507, 508, and 509 having a thickness of 500-1500 에 on the side and top surfaces of the wirings. Using the wirings thus treated as masks, impurities were introduced into the island-like silicon regions 502 by plasma doping to form the impurity regions 510. (Fig. 5 (b)).

Then, only the anode oxide films 507, 508, and 509 are etched to expose the boundary between the impurity region 510 and the active region between the impurity regions, and irradiated with KrF excimer laser light in this state, thereby producing an impurity region. Was activated (FIG. 5 (c)).

Thereafter, in order to cover the wiring 504, a polyimide film 511 having a thickness of 1 to 5 μm was formed. As the polyimide, the photosensitive polyimide can be easily used due to the ease of patterning (Fig. 5 (d)).

Then, a current was flowed through the wirings 504 to 506 in this state to form anode oxides 513 and 514 having a thickness of 2000 to 2500 mW. The part where the polyimide has already been provided is not anodized (Fig. 5 (e)).

Lastly, as the interlayer insulator 515, a silicon oxide film having a thickness of 2000 to 5000 Å was deposited, and contact holes were formed in the impurity region 510. In addition, part of the wiring 506 was removed to expose the anode oxide 514 by removing all the interlayer insulators. Next, wirings and electrodes 516 and 517 using a multilayer film of tantalum nitride (thickness 500 mW) and aluminum (thickness 3500 mW) were formed to complete the circuit. At this time, the wiring 517 constitutes a capacitor having the wiring 506 and the anode oxide 514 as a dielectric in the portion 518 (Fig. 5 (f)).

Fourth embodiment

6 shows a fourth embodiment. In this embodiment, a thin film transistor is formed on an insulating substrate. A silicon oxide film 602 was deposited on the substrate 601 as a base oxide film. Subsequently, an amorphous silicon film was deposited and this was patterned into islands. And the laser beam (KrF laser, wavelength 248nm, pulse width 20nsec) was irradiated to this. Before the laser light irradiation, the substrate was heated in a vacuum at 300 to 550 ° C. for 0.1 to 3 hours to release hydrogen contained in the amorphous silicon film. The energy density of the laser light was 250-450 mJ / cm 2. In addition, the board | substrate was heated at 250-550 degreeC at the time of laser beam irradiation. As a result, the amorphous silicon film was crystallized to form the crystalline silicon film 603.

Next, a silicon oxide film serving as the gate insulating film 604 was formed to a thickness of 800 to 1200 kPa. And the gate electrode 605 was formed using aluminum. His thickness was 2000-1000 mm 3 (Fig. 6 (a)).

Thereafter, the gate electrode was anodized to form an anode oxide (first anode oxide) 606 having a thickness of 1500 to 2500 GPa on the surface thereof. Anodization is performed by immersing the substrate in an ethylene glycol solution having 1-5% tartaric acid, integrating all the gate wirings as an anode, and using platinum as the cathode to boost the applied voltage to 1 to 5 V / min. Was performed by. Subsequently, boron (B) or phosphorus (P) ions were irradiated by plasma doping to form an impurity region 607. (Fig. 6 (b)).

After the impurity doping was finished, only the first anode oxide was etched. Etching was performed in a plasma atmosphere of carbon tetrafluoride (CF ₄ ) and oxygen. The ratio of tetrafluorocarbon (CF ₄ ) to oxygen was CF ₄ / O ₂ = 3 to 10. Under these conditions, the anodic oxide of aluminum is etched, but the silicon oxide is not etched. As a result, only the anode oxide 606 can be etched without etching the gate wiring (gate electrode) 605 and the silicon oxide film 604 as the gate insulating film. By the etching process, the thickness of the anode oxide was reduced to 500-1500 Pa (anode oxide 608).

As a result, as shown in Fig. 6C, a boundary (marked with X) between the impurity region 607 and the active region between the impurity regions appeared. Subsequently, in this state, the impurity region was activated by laser light irradiation. The laser used was a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec), and the energy density of the laser was 250-450 mJ / cm 2. When the substrate is heated to 250 to 550 캜 during laser irradiation, the impurity region can be activated more effectively. In this embodiment, since the boundary between the impurity region and the active region (indicated by X) is also irradiated with a laser light, the decrease in reliability due to deterioration of the boundary portion, which has been a problem in the conventional manufacturing process, is significantly reduced. 6 (c))

Thereafter, anodization was applied again to the gate wiring to form an anode oxide (second anode oxide) 609 having a thickness of 1000 to 2500 mV. Since the thickness of the anodic oxide 609 has the effect of determining the offset size of the thin film transistor by retreating the conductive surface during anodization and preventing a short circuit with the upper wiring, a thickness appropriate for this purpose can be selected. Can be. In some cases, it is not necessary to form such an anode oxide (Fig. 6 (d)).

Finally, as the interlayer insulator 610, a silicon oxide film is formed to a thickness of 2000 to 10000 GPa, a contact hole is formed therein, and an electrode 611 made of a titanium nitride having a thickness of 200 GPa and a aluminum having a thickness of 500 GPa is placed in the impurity region. By connecting, the thin film transistor was completed. (FIG. 6 (e)).

Fifth Embodiment

This embodiment shows an example in which two kinds of anodic oxides, that is, porous anodic oxides and barrier anodes, are combined as an anodic oxide. That is, in this embodiment, a porous anode oxide formed at a relatively low voltage is formed on the side of the gate electrode at a thickness of 0.2 µm or more, preferably 0.5 µm or more, while a barrier type anode oxide having good insulation on the upper surface of the gate electrode. To form.

The porous anodic oxide can be obtained by anodizing in an aqueous solution of 3-20% citric acid or hydroxyl, phosphoric acid, chromic acid, sulfuric acid and the like. On the other hand, the barrier anodization can be obtained by anodizing using an organic solvent such as an ethylene glycol solution such as 3-10% tartaric acid, boric acid, nitric acid, or the like. The barrier type anode oxide formed on the upper surface of the gate electrode is preferably as thin as possible (as long as insulation with the upper wiring is maintained), and preferably 0.2 µm or less, preferably 0.1 µm or less.

These two kinds of anodic oxides form a mask material on the upper surface of the gate electrode, and in this state, a porous anodic oxide is formed first, and then the mask material is removed to form a barrier type anode oxide around the upper surface of the gate electrode. It is formed by forming. The mask material used for this purpose must be able to withstand the voltage of anodization, and polyimide is suitable as the mask material, for example. In particular, when photosensitive materials such as Photonese (photosensitive polyimide) and AZ1350 are used, patterning may be performed using such a mask material at the time of patterning the gate electrode. In addition, the photoresist used in the conventional photolithography process (for example, OFPR 800/30 cp manufactured by Tokyo Okagyo Co., Ltd.) has a defect in that the resist is gradually peeled off during porous anodization because of insufficient insulation. However, this problem can be solved by forming an oxide film having a thickness of 50 to 1000 GPa under the condition of barrier type anodization before application of the resist.

Fig. 7 is a sectional view showing the manufacturing process of this embodiment. First, a base silicon oxide film 702 having a thickness of 2000 GPa was formed on a substrate (Corning 7059) 701 by the sputtering method. Subsequently, an intrinsic (I-type) amorphous silicon film having a thickness of 200 to 1000 mW, for example, 500 mW is deposited by plasma CVD, and then patterned and etched to form an island-like silicon region 703, which is then lasered. Light (KrF excimer laser) was irradiated to crystallize the island-like silicon region 703. Then, a silicon oxide film 704 having a thickness of 1000 으로서 was deposited as the gate insulating film by the sputtering method.

Subsequently, an aluminum film (containing 0.1 to 0.3% by weight of scandium) having a thickness of 3000 to 8000 Pa, for example, 4000 Pa was deposited by the sputtering method. Subsequently, a 3% tartaric acid was neutralized with ammonia and the substrate was immersed in an ethylene glycol solution set at approximately pH 7, and a voltage of 10 to 30 V was applied to form a thin anode oxide having a thickness of 100 to 400 kPa on the aluminum film. . On the aluminum film thus treated, a photoresist (eg, OFPR 800/30 cp manufactured by Tokyo Okagyo Kogyo Co., Ltd.) having a thickness of approximately 1 μm was formed by spin coating. Next, the gate electrode 705 was formed by a known photolithography method. The photoresist mask 706 remains on the gate electrode 705. Instead of the photoresist, for example, the same effect can be obtained by using a photosensitive polyimide (photonis) such as UR 3800 manufactured by Tray Kogyo Co., Ltd. (Fig. 7 (a)).

Subsequently, the substrate is immersed in an aqueous 10% citric acid solution and subjected to anodization at a constant voltage of 5 to 50 V, for example, 8 V for 10 to 500 minutes, for example, 200 minutes, to provide a porous anode oxide having a thickness of approximately 5000 Pa. 707 can be formed on the sidewall of the gate electrode with an accuracy of ± 200 Hz or less. Since the photoresist mask 706 is present on the upper surface of the gate electrode, anodization hardly proceeds there (Fig. 7 (b)).

Next, the mask material was removed to expose the top surface of the gate electrode, the substrate was immersed in an ethylene glycol solution of 3% tartaric acid (which had been neutrally formed by ammonia), and then subjected to 1-5 V / min, for example, Anodization was performed by flowing a current while raising the voltage to 100V at 4V / min. At this time, not only the top surface of the gate electrode but also the sidewall was anodized to form a dense barrier type anode oxide 708 having a thickness of 1000 占 퐉. The internal pressure of this anode oxide was 50 V or more (Fig. 7 (c)).

Next, the silicon oxide film 704 was etched by the dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important not to etch the silicon region 703 deeply by sufficiently increasing the selectivity of silicon and silicon oxide. If CF ₄ is used as the etching gas, for example, the anode oxides 707 and 708 are not etched, and only the silicon oxide film is etched. Further, the silicon oxide film under the anode oxide is not etched and remains as the gate insulating film 710.

Subsequently, impurities (phosphorus) were implanted into the silicon region 703 by the plasma doping method using the gate electrode 705 and the porous anode oxide 707 on the side surface as a mask. At this time, phosphine (PH ₃ ) was used as the doping gas, the acceleration voltage was 5 ~ 30kV, for example, 10kV. The dose was 1 × 10 ¹⁴ to 8 × 10 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^-2 . As a result, an N-type impurity region 709 was formed (Fig. 7 (d)).

Next, the porous anodic oxide 707 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid to expose the barrier type anodic oxide 708. The doped impurities were then activated by irradiating a laser beam from above and performing laser annealing. In this laser light irradiation, the laser light is also irradiated to the boundary 711 between the doped impurity region and the undoped region (Fig. 7 (e)).

The energy density of the laser light was 100 to 400 mJ / cm 2, for example 150 mJ / cm 2, and 2 to 10 shots, for example, 2 shots were irradiated. At the time of laser beam irradiation, you may heat a board | substrate to 200-300 degreeC, for example, 250 degreeC. In this embodiment, since the surface of the silicon region is exposed at the time of laser light irradiation, it is preferable that the energy density of the laser light is slightly low.

Next, a silicon oxide film having a thickness of 6000 Å is formed as the interlayer insulator 712 by the plasma CVD method, and a contact hole is formed therein, and the electrode of the source region and the drain region of the TFT is formed of a multilayer of a metal material such as titanium nitride and aluminum. Wirings 713 and 714 were formed. Finally, annealing was carried out at 350 ° C. for 30 minutes in an atmosphere of hydrogen at 1 atmosphere. Through the above process, the thin film transistor was completed. In the present embodiment, the offset width X was approximately 6000 mm by adding the thickness of the barrier type anodization film to 1000 mW of the porous anodic oxide (1000 m) (Fig. 7 (f)).

In this embodiment, since no excessive voltage is applied to the gate insulating film during anodization, the interfacial density of the gate insulating film is low, and therefore, the sub threshold characteristic (S value) of the TFT is very small. As a result, steep on / off rise characteristics are obtained.

Sixth embodiment

Fig. 8 is a sectional view showing the manufacturing process of this embodiment. First, a base silicon oxide film 802 having a thickness of 2000 GPa is formed on a substrate (Corning 7059) 801, and island-shaped intrinsic (type I) crystalline silicon having a thickness of 200 to 1500 GPa, for example, 800 GPa. After the region 803 was formed, a silicon oxide film 804 having a thickness of 1000 Å was formed to cover the island-shaped silicon region.

Subsequently, an aluminum film (containing 0.1 to 0.3% by weight of scandium) having a thickness of 3000 to 8000 Pa, for example, 4000 Pa was deposited by the sputtering method. Then, in the same manner as in the fifth embodiment, a thin anodic oxide having a thickness of 100 to 400 Å was formed on the surface of the aluminum film. On the aluminum film thus treated, a photoresist having a thickness of approximately 1 mu m was formed by spin coating, and then a gate electrode 805 was formed by a known photolithography method. The photoresist mask 806 remains on the gate electrode (Fig. 8 (a)).

Subsequently, the substrate was immersed in a 10% aqueous solution of aquatic acid and subjected to anodization for 10 to 500 minutes, for example, 200 minutes at a constant voltage of 5 to 50 V, for example 8 V, to approximately 5000 kW thickness on the sidewall of the gate electrode. A porous anode of 807 was formed. Since the photoresist mask 806 remains on the upper surface of the gate electrode, anodization hardly proceeded there (Fig. 8 (b)).

Next, the mask material was removed to expose the top surface of the gate electrode, and the substrate was immersed in an ethylene glycol solution of 3% tartaric acid (which had a pH adjusted to neutral by ammonia), for example, 1 to 5 V / min, for example Anodization was performed by supplying a current thereto while increasing the voltage to 100 V at 4 V / min. At this time, the top and side surfaces of the gate electrode were anodized to form a dense barrier type anode oxide 808 having a thickness of 100 GPa. The internal pressure of this anodic oxide was 50 V or more.

Next, the silicon oxide film 804 was etched by the dry etching method. In this etching, the anode oxides 807 and 808 were not etched, only the silicon oxide film was etched. Further, the silicon oxide film under the anodic oxide was not etched and remained as the gate insulating film 809 (Fig. 8 (c)).

Next, the porous anodic oxide 807 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid to expose the barrier type anodic oxide 808. Then, using the gate electrode 805 and the gate insulating film 809 defined by the porous anode oxide 807 on the side as a mask, impurities (phosphorus) are formed in the silicon region 803 by plasma doping. Was injected. Phosphine (PH3) was used as the doping gas, and the acceleration voltage was 5 to 30 kV, for example, 10 kV. The dose was 1 × 10 ¹⁴ to 8 × 10 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^-2 .

In this doping step, a high concentration of phosphorus is injected into the region 810 not covered with the gate insulating film 809, but the gate insulating film is disturbed in the region 811 whose surface is covered by the gate insulating film 809, The doping amount is small, and in this embodiment, only 0.1 to 5% of the impurities in the region 810 are implanted. As a result, an N-type high concentration impurity region 810 and a low concentration impurity region 811 were formed (Fig. 8 (d)).

Thereafter, the laser light was irradiated from above to perform laser annealing, thereby activating the doped impurities. In this case, however, the laser light may not be sufficiently irradiated on the boundary between the low concentration impurity region 811 and the active region. However, since the amount of doping in the low concentration impurity region 811 is very small as described above, damage to silicon crystal is small, and therefore, the necessity of improvement of crystallinity by laser light irradiation is not so large.

In contrast, the boundary between the high concentration impurity region 810 and the low concentration impurity region 811 needs to be sufficiently irradiated with a laser beam. This is because a large amount of impurity ions are introduced into the high concentration impurity region 811, and crystal defects in the region are also large. As shown in the diagram showing the structure of this embodiment, the laser beam also transmits to the boundary portion (Fig. 8 (e)).

Subsequently, a silicon oxide film having a thickness of 6000 Å is formed as the interlayer insulator 812 by the plasma CVD method, and a contact hole is formed therein, and the wiring of the source region and the drain region of the TFT is made of a multilayer film made of a metal material such as titanium nitride and aluminum. Electrodes 813 and 814 were formed; Finally, annealing was carried out at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm. Through the above steps, the thin film transistor was completed.

In this embodiment, a structure similar to the so-called low concentration drain (LDD) structure can be obtained. The LDD structure is shown to be effective in suppressing deterioration due to hot carriers, but the same effect can be obtained in the TFT fabricated by this embodiment. However, as compared with the known process for obtaining the LDD, the present embodiment is characterized in that the LDD can be obtained by one doping process. In this embodiment, the highly concentrated impurity region 810 is defined by using the gate insulating film 809 defined by the porous anodization film 807. In other words, the impurity region is indirectly defined by the porous anode oxide 807. And as is clear from this embodiment, the width X of the LDD region is substantially determined by the width of the porous anodic oxide.

Higher integration can be performed by using the TFT fabrication method shown in this embodiment or the previous embodiment. At that time, it is more convenient to change the width X of the offset region or the LDD region in accordance with the characteristics required for the TFT. Fig. 9 shows a block diagram of an electro-optical system using an integrated circuit in which a display, a CPU, a memory, and the like are installed on one glass substrate.

Here, the input port reads a signal input from the outside and converts it into an image signal. The correction memory is a memory inherent to an active matrix panel for correcting an input signal or the like corresponding to the characteristics of the active matrix panel. In particular, this correction memory is for retaining information unique to each pixel in the nonvolatile memory and individually correcting it. That is, in the case where there is a point defect in a pixel of the electro-optical device, the correction memory sends a corrected signal corresponding to it to the pixels around the point to cover the point defect, thereby making the point defect inconspicuous. Alternatively, when one pixel is darker than the surrounding pixels, the pixel is sent to a larger signal so as to have the same brightness as the surrounding pixels.

The CPU and memory are the same as those of a normal computer. In particular, the memory has an image memory corresponding to each pixel as a RAM. The backlight for illuminating the substrate from the rear side can be changed according to the image information.

In order to obtain the width of the offset region or LDD region suitable for each of these circuits, wirings of 3 to 10 lines may be formed so as to change the anodization conditions individually. In general, in the TFT 91 of the active matrix circuit, when the channel length is 10 mu m, the width of the LDD region is 0.4 to 1 mu m, for example, 0.6 mu m. In the driver, in the N-channel TFT, when the channel length is 8 μm and the channel width is 200 μm, the width of the LDD region may be 0.2 to 0.3 μm, for example, 0.25 μm. Similarly, in the P-channel TFT, when the channel length is 5 mu m and the channel width is 500 mu m, the width of the LDD region may be 0 to 0.2 mu m, for example, 0.1 mu m. In the decoder, in the N-channel TFT, when the channel length is 8 μm and the channel width is 10 μm, the width of the LDD region may be 0.3 to 0.4 μm, for example, 0.35 μm. Similarly, in the P-channel TFT, when the channel length is 5 mu m and the channel width is 10 mu m, the width of the LDD region may be 0 to 0.2 mu m, for example, 0.1 mu m. In addition, the CPU, the input port, the correction memory, and the NTFT and PTFT of the memory in FIG. 9 may optimize the width of the LDD region similarly to the decoder for high frequency operation and low power consumption. Thus, the electro-optical device 94 can be formed on the same substrate having an insulating surface.

As described above, according to the present invention, the reliability of MIS semiconductor devices such as MOS transistors, thin film transistors, etc. manufactured in a low temperature process can be improved. Specifically, even when the source was grounded and left for 10 hours or more while a potential of +20 or more or -20 V or less was applied to one or both of the drain and the gate, there was no significant effect on the characteristics of the transistor.

Although the above embodiments have been described centering on the thin film transistor, the effects of the present invention can be obtained in the same manner in the MIS transistor fabricated on a single crystal semiconductor substrate. In addition, with respect to the semiconductor material, in addition to the silicon described in the embodiments, the same effect can be obtained also in the silicon-germanium alloy, silicon carbide, germanium, cadmium selenite, cadmium sulfide, gallium arsenide, and the like. As mentioned above, this invention is industrially advantageous invention.

Claims (31)

A substrate having an (correction) insulating surface, an active matrix circuit formed on the insulating surface, at least one driver formed on the insulating surface and driving the active matrix circuit, and the at least one provided on the insulating surface A semiconductor device connected to a driver of the semiconductor device, the semiconductor device including a circuit including at least one of a memory, a CPU, an input port, and a correction memory, wherein at least one of the active matrix circuit, the driver, and the circuit is at least one P-channel type. A semiconductor device comprising a thin film transistor and at least one N-channel thin film transistor; Each of the P-channel and N-channel thin film transistors is formed with a semiconductor film formed on a substrate, a first region including a channel region formed in the semiconductor film, and formed in the semiconductor film, to impart one conductivity type. A pair of second regions doped with impurities and serving as source and drain regions, a pair of third regions respectively disposed between the first region and each of the second regions, and a gate insulating film And a gate electrode disposed adjacent to the first region, wherein the width of the third region of the N-channel thin film transistor is larger than that of the P-channel thin film transistor. The semiconductor device according to claim 1, wherein said gate electrode is provided on said semiconductor film. The semiconductor device according to claim 1, wherein one boundary of one of the third regions coincides with an edge of the gate electrode. The semiconductor device of claim 1, wherein the third regions include an LDD region, an offset region, or any one of them. The semiconductor device according to claim 1, wherein the third regions include two or more regions having different specific resistances. The semiconductor device according to claim 1, wherein the substrate is selected from the group consisting of a glass substrate, a single crystal semiconductor substrate, an alkali free glass substrate, and a silica substrate. The semiconductor device according to claim 1, wherein the material of the semiconductor film is selected from the group consisting of silicon-germanium alloy, silicon carbide, germanium, cadmium selenite, cadmium sulfide, gallium arsenide and silicon. The electro-optical device according to claim 1, wherein the material of the gate electrode is selected from the group consisting of aluminum, tantalum, titanium, silicon, tantalum nitride, titanium nitride, tungsten and molybdenum. A substrate having an insulating surface, an active matrix circuit formed on the insulating surface, at least one driver formed on the insulating surface and driving the active matrix circuit, and provided on the insulating surface A semiconductor device connected to at least one driver and comprising a circuit including at least one of a memory, a CPU, an input port, and a correction memory, wherein at least one of the active matrix circuit, the driver, and the circuit is at least one P A semiconductor device comprising a channel type thin film transistor and at least one N channel type thin film transistor; Each of the P-channel and N-channel thin film transistors is formed with a semiconductor film formed on a substrate, a first region including a channel region formed in the semiconductor film, and formed in the semiconductor film, to impart one conductivity type. A pair of second regions doped with an impurity, a pair of third regions respectively disposed between the first region and each of the second regions, and a gate insulating film disposed adjacent to the first region And a gate electrode, wherein a channel length of the N-channel thin film transistor is larger than that of the P-channel thin film transistor, and a width of the third region of the N-channel thin film transistor is greater than that of the P-channel thin film transistor. And larger than the width of the third region. The semiconductor device according to claim 9, wherein said gate electrode is provided on said semiconductor film. The semiconductor device according to claim 9, wherein the substrate is selected from the group consisting of a glass substrate, a single crystal semiconductor substrate, an alkali free glass substrate and a silica substrate. The semiconductor device according to claim 9, wherein the material of the semiconductor film is selected from the group consisting of silicon-germanium alloy, silicon carbide, germanium, cadmium selenite, cadmium sulfide, gallium arsenide and silicon. 10. The semiconductor device according to claim 9, wherein the material of the gate electrode is selected from the group consisting of aluminum, tantalum, titanium, silicon, tantalum nitride, titanium nitride, tungsten and molybdenum. (Correction) a substrate having an insulating surface, an active matrix circuit formed on the insulating surface, at least one driver formed on the insulating surface and driving the active matrix circuit, and the at least one provided on the insulating surface A semiconductor device connected to a driver of the semiconductor device, the semiconductor device including a circuit including at least one of a memory, a CPU, an input port, and a correction memory, wherein at least one of the active matrix circuit, the driver, and the circuit is at least one P-channel type. A semiconductor device comprising a thin film transistor and at least one N-channel thin film transistor; Each of the P-channel and N-channel thin film transistors is formed with a semiconductor film formed on a substrate, a first region including a channel region formed in the semiconductor film, and formed in the semiconductor film, to impart one conductivity type. A pair of second regions doped with impurities, and LDD regions each disposed between the first region and each of the second regions and doped with the impurities at a concentration less than that in the second region, respectively. A pair of third regions including a gate electrode and a gate electrode disposed adjacent to the first region with a gate insulating layer interposed therebetween, and the edges of which are aligned with the edge of the first region. And the width of the LDD region is larger than that of the P-channel thin film transistor. The semiconductor device according to claim 14, wherein said gate electrode is provided on said semiconductor film. The semiconductor device according to claim 14, wherein said substrate is selected from the group consisting of a glass substrate, a single crystal semiconductor substrate, an alkali free glass substrate and a silica substrate. 15. The semiconductor device according to claim 14, wherein the material of the semiconductor film is selected from the group consisting of silicon-germanium alloy, silicon carbide, germanium, cadmium selenite, cadmium sulfide, gallium arsenide and silicon. 15. A semiconductor device according to claim 14, wherein the material of the gate electrode is selected from the group consisting of aluminum, tantalum, titanium, silicon, tantalum nitride, titanium nitride, tungsten and molybdenum. A substrate having an insulating surface, an active matrix circuit formed on the insulating surface, at least one driver formed on the insulating surface and driving the active matrix circuit, and provided on the insulating surface A semiconductor device connected to at least one driver and comprising a circuit including at least one of a memory, a CPU, an input port, and a correction memory, wherein at least one of the active matrix circuit, the driver, and the circuit is at least one P A semiconductor device comprising a channel type thin film transistor and at least one N channel type thin film transistor; Each of the P-channel and N-channel thin film transistors is formed with a semiconductor film formed on a substrate, a first region including a channel region formed in the semiconductor film, and formed in the semiconductor film, to impart one conductivity type. A pair of second regions doped with impurities, and LDD regions each disposed between the first region and each of the second regions and doped with the impurities at a concentration less than that in the second region, respectively. And a pair of third regions including a gate electrode and a gate electrode disposed adjacent to the first region with a gate insulating layer interposed therebetween, wherein the LDD region of the P-channel thin film transistor has a width of 0 to 0.2 μm. And the width of the LDD region of the N-channel thin film transistor is larger than the width of the LDD region of the P-channel thin film transistor. 20. The semiconductor device according to claim 19, wherein said gate electrode is provided on said semiconductor film. 20. The semiconductor device according to claim 19, wherein the substrate is selected from the group consisting of a glass substrate, a single crystal semiconductor substrate, an alkali free glass substrate and a silica substrate. 20. The semiconductor device according to claim 19, wherein the material of the semiconductor film is selected from the group consisting of silicon-germanium alloys, silicon carbide, germanium, cadmium selenite, cadmium sulfide, gallium arsenide and silicon. 20. The semiconductor device according to claim 19, wherein the material of the gate electrode is selected from the group consisting of aluminum, tantalum, titanium, silicon, tantalum nitride, titanium nitride, tungsten, and molybdenum. (delete) (delete) (delete) (delete) (delete) (delete) (delete) (delete)