JP3219856B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3219856B2 JP3219856B2 JP19111992A JP19111992A JP3219856B2 JP 3219856 B2 JP3219856 B2 JP 3219856B2 JP 19111992 A JP19111992 A JP 19111992A JP 19111992 A JP19111992 A JP 19111992A JP 3219856 B2 JP3219856 B2 JP 3219856B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- film
- insulating film
- heat treatment
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 37
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000003990 capacitor Substances 0.000 claims description 41
- 238000010438 heat treatment Methods 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 150000004767 nitrides Chemical class 0.000 claims description 19
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 18
- 229910044991 metal oxide Inorganic materials 0.000 claims description 10
- 150000004706 metal oxides Chemical class 0.000 claims description 10
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 9
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 9
- 239000012298 atmosphere Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 2
- 229910002113 barium titanate Inorganic materials 0.000 claims description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 2
- NKZSPGSOXYXWQA-UHFFFAOYSA-N dioxido(oxo)titanium;lead(2+) Chemical compound [Pb+2].[O-][Ti]([O-])=O NKZSPGSOXYXWQA-UHFFFAOYSA-N 0.000 claims description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 230000008569 process Effects 0.000 description 25
- 238000000206 photolithography Methods 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 9
- 238000000059 patterning Methods 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 239000010410 layer Substances 0.000 description 8
- 239000012299 nitrogen atmosphere Substances 0.000 description 8
- 230000006866 deterioration Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000002542 deteriorative effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 3
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910001009 interstitial alloy Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路用の例
えばキャパシタの製造方法に係り、特に少なくとも一方
の電極として金属窒化物を用い、さらに絶縁膜として金
属酸化物を用いる半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing, for example, a capacitor for a semiconductor integrated circuit, and more particularly to a method of manufacturing a semiconductor device using a metal nitride as at least one electrode and a metal oxide as an insulating film. About.
【０００２】[0002]
【従来の技術】従来、情報の記憶動作を行なう半導体装
置の１つとして、ＭＯＳトランジスタとキャパシタが組
み合わされたＤＲＡＭが知られている。2. Description of the Related Art Conventionally, a DRAM in which a MOS transistor and a capacitor are combined has been known as one of the semiconductor devices which perform an operation of storing information.
【０００３】近年、半導体技術の進歩、特に微細加工技
術の進歩により高集積化大容量化が急速に進められてい
る。この集積化に伴い、キャパシタ面積は減少する。し
かし、キャパシタ容量を低下させれば、メモリ内容が誤
って読みだされたり、または、α線等によるメモリ内容
が破壊される等のソフトエラーの発生が問題になってく
る。In recent years, with the advance of semiconductor technology, especially the advance of fine processing technology, high integration and large capacity have been rapidly promoted. With this integration, the capacitor area decreases. However, if the capacitance of the capacitor is reduced, the occurrence of a soft error such as erroneous reading of the memory contents or destruction of the memory contents due to α rays or the like becomes a problem.
【０００４】一般に、キャパシタ絶縁膜として酸化シリ
コン、窒化シリコン、あるいはそれらの複合膜が用いら
れている。このような状況にあって、実行的なキャパシ
タ面積を稼ぐためには３次元構造のキャパシタが用いら
れている。しかし、一層の集積化に対しての構造的な工
夫だけでは十分ではなく、キャパシタ絶縁膜として酸化
シリコンよりも誘電率の高い金属酸化膜の検討が行なわ
れている。上述のような高誘電体膜として代表的な物質
としては、タンタル酸化膜、更にＳr Ｔi Ｏ3、ＰＺＴ
等のペロブスカイト型の絶縁膜などが検討されており、
酸化シリコンに比べて少ない面積で大きなキャパシタ容
量を得ることが可能である。しかし、キャパシタ絶縁膜
としてタンタル酸化膜や高誘電率絶縁膜を用いた場合、
電極材料として従来の多結晶シリコンを用いると電極／
絶縁膜界面に誘電率の低いＳi Ｏ2 が形成されて容量の
低下を引き起こすと共に、金属酸化膜を還元し、リーク
電流の増大をもたらすために、それらの膜上に用いるこ
とはできない。したがって、これらの絶縁膜を劣化させ
ずに安定かつ加工性の良好な金属電極を用いる必要があ
る。確かにＴi Ｎをはじめ金属窒化物は安定かつ加工性
に優れている。Generally, silicon oxide, silicon nitride, or a composite film thereof is used as a capacitor insulating film. In such a situation, a capacitor having a three-dimensional structure is used to increase an effective capacitor area. However, structural measures for further integration are not enough, and a metal oxide film having a higher dielectric constant than silicon oxide has been studied as a capacitor insulating film. Typical materials for the high dielectric film as described above include a tantalum oxide film, SrTiO 3 , and PZT.
Perovskite-type insulating films and the like are being studied.
A large capacitor capacity can be obtained with a smaller area than silicon oxide. However, when using a tantalum oxide film or a high dielectric constant insulating film as the capacitor insulating film,
If conventional polycrystalline silicon is used as the electrode material, the electrode /
Since SiO 2 having a low dielectric constant is formed at the interface of the insulating film to cause a reduction in capacity, the metal oxide film is reduced and a leak current is increased, so that it cannot be used on those films. Therefore, it is necessary to use a metal electrode which is stable and has good workability without deteriorating these insulating films. Certainly, metal nitrides such as TiN are stable and have excellent workability.
【０００５】しかしながらキャパシタ絶縁膜としてこの
ような材料を電極に用いた場合、その後の高温熱処理を
経ることにより、リーク電流が増大するという問題があ
る。実際のＬＳＩ工程においてはキャパシタ形成後、い
くつかの高温処理が必要であるために、これらの工程を
経た後にはキャパシタの劣化が生じてしまう。その結
果、ＤＲＡＭ等の素子の信頼性を著しく損なうことにな
る。However, when such a material is used for the electrode as the capacitor insulating film, there is a problem that the leakage current increases due to the subsequent high-temperature heat treatment. In the actual LSI process, some high-temperature processing is required after the formation of the capacitor, so that the capacitor is deteriorated after these processes. As a result, the reliability of a device such as a DRAM is significantly impaired.
【０００６】[0006]
【発明が解決しようとする課題】本発明は上述の事情を
考慮してなされたもので、本発明の目的は、電極として
金属窒化物を用い、容量絶縁膜として金属酸化物を用い
た例えばキャパシタにおいて、その金属窒化物からなる
電極の形成後の熱処理によってその金属酸化膜を劣化さ
せることなく、その金属窒化物を構造的、熱的、組成的
に安定化させ、熱処理によってリーク電流の増加の生じ
ない大容量のキャパシタ等の半導体装置の製造方法を提
供することにある。SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a capacitor using a metal nitride as an electrode and a metal oxide as a capacitor insulating film. In the above, the metal nitride is structurally, thermally and compositionally stabilized without deteriorating the metal oxide film by the heat treatment after the formation of the metal nitride electrode, and the heat treatment increases the leakage current. It is an object of the present invention to provide a method of manufacturing a semiconductor device such as a large-capacity capacitor which does not cause a problem.
【０００７】[0007]
【課題を解決するための手段】本発明の骨子は、少なく
とも一方の電極として金属窒化物を形成後、所望の熱工
程を行なう前に、一旦、非酸化性雰囲気中あるいは真空
中で熱処理を行なうことにより、容量絶縁膜である金属
酸化膜を劣化することなく、金属窒化物を構造的、熱
的、組成的に安定な状態にすることにより、ＤＲＡＭ等
の素子の特性および信頼性の向上を図り得るキャパシタ
を提供することにある。The gist of the present invention is to perform a heat treatment in a non-oxidizing atmosphere or a vacuum once after forming a metal nitride as at least one electrode and before performing a desired heating step. This makes it possible to improve the characteristics and reliability of devices such as DRAMs by making the metal nitride structurally, thermally, and compositionally stable without deteriorating the metal oxide film, which is the capacitive insulating film. It is to provide a capacitor that can be achieved.
【０００８】また本発明は、半導体基板上に形成された
例えばキャパシタにおいて、容量絶縁膜として金属酸化
膜を形成する工程と、その容量絶縁膜上に金属窒化物か
らなる電極を形成する工程と、後工程における層間絶縁
膜、配線の形成に伴う熱工程を経る前に非酸化性雰囲気
中または真空中で３００℃以上５００℃以下の温度で１
時間以上熱処理する工程とから構成される半導体装置の
製造方法である。The present invention also provides a process for forming a metal oxide film as a capacitor insulating film in a capacitor formed on a semiconductor substrate, for example, and a process for forming an electrode made of metal nitride on the capacitor insulating film. Before passing through a heat process accompanying the formation of an interlayer insulating film and wiring in a post-process, a temperature of 300 ° C. to 500 ° C. in a non-oxidizing atmosphere or vacuum is applied.
And a heat treatment for at least one hour.
【０００９】また同様に、容量絶縁膜として還移金属酸
化膜を形成する工程と、その容量絶縁膜上に金属窒化物
からなる電極を形成する工程と、後工程における層間絶
縁膜、配線の形成に伴う熱工程を経る前に非酸化性雰囲
気中または真空中で７００℃以上９００℃以下の温度で
２分以下の熱処理をする工程とから構成される半導体装
置の製造方法である。Similarly, a step of forming a transition metal oxide film as a capacitor insulating film, a step of forming an electrode made of metal nitride on the capacitor insulating film, and a step of forming an interlayer insulating film and wiring in a later step Performing a heat treatment at a temperature of 700 ° C. or more and 900 ° C. or less for 2 minutes or less in a non-oxidizing atmosphere or vacuum before passing through a heat step accompanying the above.
【００１０】[0010]
【作用】一般に、金属窒化物は金属中に窒素原子が入り
込んだいわゆる侵入型化合物であるために、金属と窒素
の組成比の最も安定な組成からのズレが生じやすい。ま
た、金属と窒素の結合も不安定になりやすい。このため
に余剰あるいは結合が不完全な窒素や金属原子は不安定
であるために、隣合った金属酸化膜と相互作用を起し、
その結果この金属酸化膜の絶縁性を劣化させる。In general, a metal nitride is a so-called interstitial compound in which a nitrogen atom has entered a metal, so that the composition ratio of the metal and nitrogen tends to deviate from the most stable composition. In addition, the bond between the metal and nitrogen tends to be unstable. For this reason, surplus or incompletely bonded nitrogen and metal atoms are unstable and interact with adjacent metal oxide films,
As a result, the insulation of the metal oxide film is deteriorated.
【００１１】ＬＳＩ工程において、キャパシタ形成後に
は層間絶縁膜および配線の形成に伴う熱工程を経ること
になるが、キャパシタ電極の金属窒化膜の安定化が図ら
れていないと上述のように絶縁膜との相互作用によりリ
ーク電流の増加等の劣化を引き起こす結果となる。この
金属窒化膜を安定化するためには、ある程度の熱処理が
必要であるが、この際に絶縁膜の劣化を招かないように
する必要がある。５００℃以下の温度ではほとんど劣化
は生じないが、その安定化には少なくとも１時間以上の
経過を要する。この理由は、低温では余剰の窒素の「外
方拡散」の速度が小さいためである。一方、７００℃以
上の温度では上述のような安定化は短時間で生じるが、
その反面、絶縁膜の劣化反応が生じやすくなる。このた
め、少なくとも２分以下の短時間で、しかも急速急冷の
プロセスが必要となる。[0011] In the LSI process, after forming the capacitor, a heat process accompanied with the formation of the interlayer insulating film and the wiring is performed. However, if the metal nitride film of the capacitor electrode is not stabilized, the insulating film is formed as described above. The result of the interaction is that degradation such as an increase in leakage current is caused. To stabilize the metal nitride film, a certain amount of heat treatment is required. At this time, it is necessary to prevent deterioration of the insulating film. Degradation hardly occurs at a temperature of 500 ° C. or less, but the stabilization requires at least one hour or more. The reason for this is that the rate of "outward diffusion" of excess nitrogen is low at low temperatures. On the other hand, at a temperature of 700 ° C. or higher, the above stabilization occurs in a short time,
On the other hand, a deterioration reaction of the insulating film is likely to occur. Therefore, a rapid quenching process in a short time of at least 2 minutes or less is required.
【００１２】一方、５００℃より高温でかつ７００℃よ
りも低温な範囲では、金属窒化物の安定化を図り、且つ
絶縁膜の劣化を招かないような熱処理はとりにくい。し
かし、前述のような後工程での温度はこの範囲に入るの
で、本発明の主旨としてこのような熱処理に先だって、
一旦上述のような金属窒化物の安定化を意図した熱処理
を施すことによって、劣化のない信頼性の高いキャパシ
タの作成が可能となる。On the other hand, when the temperature is higher than 500 ° C. and lower than 700 ° C., it is difficult to perform a heat treatment that stabilizes the metal nitride and does not cause deterioration of the insulating film. However, since the temperature in the post-process as described above falls within this range, prior to such heat treatment as the gist of the present invention,
Once a heat treatment intended to stabilize the metal nitride as described above is performed, a highly reliable capacitor without deterioration can be manufactured.
【００１３】その結果として、本発明の製造方法によ
り、金属窒化物の電気抵抗が低下し、構造的、熱的、化
学的に安定化した半導体装置が提供可能となる。As a result, according to the manufacturing method of the present invention, it is possible to provide a semiconductor device in which the electrical resistance of the metal nitride is reduced and which is structurally, thermally and chemically stabilized.
【００１４】[0014]
【実施例】以下に、本発明の各実施例の詳細を図を参照
しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below in detail with reference to the drawings.
【００１５】図１は本発明の第１の実施例に関するＤＲ
ＡＭ用スタックトキャパシタの断面図である。FIG. 1 shows a DR according to a first embodiment of the present invention.
It is sectional drawing of the stacked capacitor for AM.
【００１６】図１（ａ）に示す如く、比抵抗１０Ω・ｃ
ｍを有し、表面が（１００）面のｐ型シリコン基板１０
１上にＬＯＣＯＳ法により選択的に酸化膜１０２を形成
して素子分離領域を形成する。まお、ここで素子分離を
行なうための溝１２０を形成し、この溝をＣＶＤ酸化膜
１０２で埋め込み、その後、通常の写真蝕刻工程を経て
パターニングする。次に、ゲート酸化膜となる薄い熱酸
化膜１０３を形成し、その後、ゲート電極となる第１の
ｎ+ 型ポリシリコン膜１０４を形成した後、通常の写真
蝕刻工程を経てパターニングを行なう。その後、前記ゲ
ートに対して自己整合的にイオン注入法によりｎ- 型拡
散層（ソース・ドレイン領域）１０５を形成する。As shown in FIG. 1A, the specific resistance is 10Ω · c.
p-type silicon substrate 10 having a surface of (100)
An oxide film 102 is selectively formed on the substrate 1 by a LOCOS method to form an element isolation region. Here, a groove 120 for performing element isolation is formed, the groove is filled with a CVD oxide film 102, and thereafter, patterning is performed through a normal photolithography process. Next, a thin thermal oxide film 103 serving as a gate oxide film is formed, and thereafter, a first n + type polysilicon film 104 serving as a gate electrode is formed. Thereafter, patterning is performed through a normal photolithography process. Thereafter, an n @-type diffusion layer (source / drain region) 105 is formed in a self-aligned manner with respect to the gate by ion implantation.
【００１７】続いて図１（ｂ）に示す如く、厚いＣＶＤ
酸化膜１０６を全面に形成した後通常の写真蝕刻工程を
経てｎ- 型拡散層１０５の一部と接続する開口部１０７
を形成する。さらに全面に第２のｎ+ 型ポリシリコン膜
１０８を形成し通常の写真蝕刻工程を経てパターニング
する。タンタル酸化膜１０９をＴａ（ＯＣ2 Ｈ5 ）5を
ソースガスとして使用し、熱ＣＶＤ法によって１５０オ
ングストロームの厚さに形成する。Subsequently, as shown in FIG.
After an oxide film 106 is formed on the entire surface, an opening 107 connected to a part of the n − -type diffusion layer 105 through a normal photolithography process.
To form Further, a second n + type polysilicon film 108 is formed on the entire surface, and is patterned through a normal photolithography process. A tantalum oxide film 109 is formed to a thickness of 150 Å by a thermal CVD method using Ta (OC 2 H 5 ) 5 as a source gas.
【００１８】次に、図１（ｃ）に示す如く、窒化チタン
膜１１０をスパッタ法で全面に形成した後、通常の写真
蝕刻工程を経てパターニングする。最後に、４００℃で
４時間、窒素雰囲気中で熱処理を行なう。この後、ビッ
ト線形成後に配線と拡散層のコンタクト形成にシリサイ
ド化のための６００℃の高温工程を経ることになるが、
本発明の製造方法によればこのような熱処理によっても
絶縁膜の特性の劣化を生じない。その結果、上述の一連
の製造処理工程によって信頼性の高いＤＲＡＭメモリセ
ルを完成することが可能となる。Next, as shown in FIG. 1C, after a titanium nitride film 110 is formed on the entire surface by a sputtering method, patterning is performed through a usual photolithography process. Finally, heat treatment is performed at 400 ° C. for 4 hours in a nitrogen atmosphere. After that, a high-temperature process of 600 ° C. for silicidation is performed for forming a contact between the wiring and the diffusion layer after forming the bit line.
According to the manufacturing method of the present invention, such heat treatment does not cause deterioration of the characteristics of the insulating film. As a result, a highly reliable DRAM memory cell can be completed by the above-described series of manufacturing processing steps.
【００１９】なお、窒化チタン膜形成後の熱処理は、Ａ
ｒ雰囲気中で行なってもよいし、真空中で行なってもよ
い。また、窒素雰囲気中７５０℃で３０秒間の高速熱処
理を行なってもよい。The heat treatment after the formation of the titanium nitride film is performed by A
It may be performed in an r atmosphere or in a vacuum. Alternatively, high-speed heat treatment may be performed at 750 ° C. for 30 seconds in a nitrogen atmosphere.
【００２０】次に、本発明の第２の実施例を図２を参照
しながら説明する。図２は本発明の第２実施例に関する
ＤＲＡＭ用スタックトキャパシタの断面図である。Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a sectional view of a stacked capacitor for a DRAM according to a second embodiment of the present invention.
【００２１】まず、図２（ａ）に示す如く、比抵抗１０
Ω・ｃｍを有し、表面が（１００）面のｐ型シリコン基
板２０１上に、ＬＯＣＯＳ法により選択的に酸化膜２０
２を形成して素子分離領域を形成する。なお、素子分離
を行なうために溝２２０を形成し、この溝をＣＶＤ酸化
膜２０２により埋め込む。続いて、ゲート酸化膜となる
薄い熱酸化膜２０３を形成した後、ゲート電極となる第
１のｎ+ 型ポリシリコン膜２０４を形成した後、通常の
写真蝕刻工程を経てパターニングを行なう。その後、前
記ゲートに対して自己整合的にイオン注入法によりｎ-
型拡散層（ソース・ドレイン領域）２０５を形成する。First, as shown in FIG.
An oxide film 20 is selectively formed on a p-type silicon substrate 201 having Ω · cm and having a (100) surface by a LOCOS method.
2 is formed to form an element isolation region. A groove 220 is formed for element isolation, and this groove is filled with a CVD oxide film 202. Subsequently, after a thin thermal oxide film 203 serving as a gate oxide film is formed, a first n + type polysilicon film 204 serving as a gate electrode is formed, and patterning is performed through a normal photolithography process. Thereafter, the gate is self-aligned with n-
A type diffusion layer (source / drain region) 205 is formed.
【００２２】続いて、図２（ｂ）に示す如く、厚いＣＶ
Ｄ酸化膜２０６を全面に形成した後に、通常の写真蝕刻
工程を経てｎ- 型拡散層２０５の一部と接続する開口部
２０７を形成する。さらに、全面に第１の窒化チタン膜
２０８をスパッタ法で形成し、その後７５０℃で１分
間、窒素雰囲気中で急速冷却で熱処理を行なう。さらに
その後、通常の写真蝕刻工程を経てパターニングし、タ
ンタル酸化膜２０９をＴａ（ＯＣ2 Ｈ5 ）5 をソースガ
スとして使用して、熱ＣＶＤ法により膜厚１５０オング
ストロームに形成する。Subsequently, as shown in FIG.
After forming the D oxide film 206 on the entire surface, an opening 207 connected to a part of the n − -type diffusion layer 205 is formed through a normal photolithography process. Further, a first titanium nitride film 208 is formed on the entire surface by a sputtering method, and thereafter, heat treatment is performed at 750 ° C. for 1 minute in a nitrogen atmosphere by rapid cooling. Thereafter, patterning is performed through a normal photolithography process, and a tantalum oxide film 209 is formed to a thickness of 150 Å by a thermal CVD method using Ta (OC 2 H 5 ) 5 as a source gas.
【００２３】次に、図２（ｃ）に示す如く、第２の窒化
チタン膜２１１をＣＶＤ法で全面に形成した後、通常の
写真蝕刻工程を経てパターニングする。最後に、７５０
℃で１分間、窒素雰囲気中で熱処理を行なうことによ
り、以降の６００℃の熱工程にも耐えうる１トランジス
タ／１キャパシタのＤＲＡＭセルが完成する。Next, as shown in FIG. 2C, after a second titanium nitride film 211 is formed on the entire surface by the CVD method, patterning is performed through a normal photolithography process. Finally, 750
By performing a heat treatment at a temperature of 1 ° C. for 1 minute in a nitrogen atmosphere, a 1-transistor / 1-capacitor DRAM cell that can withstand the subsequent heat treatment at 600 ° C. is completed.
【００２４】この窒化チタン膜形成後の熱処理は、Ａｒ
雰囲気中で行なってもよいし、真空中で行なってもよ
い。また、窒素雰囲気中５００℃で１時間の熱処理を行
なってもよい。The heat treatment after the formation of the titanium nitride film is performed using Ar
It may be performed in an atmosphere or in a vacuum. Further, heat treatment may be performed at 500 ° C. for 1 hour in a nitrogen atmosphere.
【００２５】図３は、本発明の第３の実施例を表わすＤ
ＲＡＭ用のスタックキャパシタの断面図である。図３
（ａ）に示す如く、比抵抗１０Ω・ｃｍを有し、表面が
（１００）面のｐ型シリコン基板３０１上に、ＬＯＣＯ
Ｓ法により選択的に酸化膜３０３を形成して素子分離領
域を形成する。なお、素子分離を行なうための溝３２０
を形成し、この溝をＣＶＤ酸化膜３０３により埋め込ん
でもよい。更に通常の写真蝕刻工程を経てパターニング
を行なう。続いて、ゲート酸化膜となる薄い熱酸化膜３
０４を形成した後、ゲート電極となる第１のｎ+ 型ポリ
シリコン膜３０５を形成した後、通常の写真蝕刻工程を
経てパターニングを行なう。その後、反応性イオンエッ
チングによりサイドウォールを形成する。前記ゲートに
対して自己整合的にイオン注入法によりｎ- 型拡散層
（ソース・ドレイン領域）３０６を形成する。FIG. 3 shows a third embodiment of the present invention.
It is sectional drawing of the stack capacitor for RAM. FIG.
As shown in (a), LOCO is placed on a p-type silicon substrate 301 having a specific resistance of 10 Ω · cm and a surface of (100).
An oxide film 303 is selectively formed by the S method to form an element isolation region. Note that a groove 320 for performing element isolation is provided.
May be formed, and the trench may be filled with a CVD oxide film 303. Further, patterning is performed through a normal photolithography process. Subsequently, a thin thermal oxide film 3 serving as a gate oxide film
After the formation of the gate electrode 04, a first n + -type polysilicon film 305 serving as a gate electrode is formed, and then patterned through a normal photolithography process. Thereafter, a sidewall is formed by reactive ion etching. An n @--type diffusion layer (source / drain region) 306 is formed by ion implantation in a self-aligned manner with respect to the gate.
【００２６】次に、ウェハの全面にスパッタリングによ
ってタングステンシリサイド膜３０７および、多結晶シ
リコン積層膜３０８を形成後、通常の写真蝕刻工程を経
てビット線を形成する。Next, after a tungsten silicide film 307 and a polycrystalline silicon laminated film 308 are formed on the entire surface of the wafer by sputtering, bit lines are formed through a normal photolithography process.
【００２７】続いて、図３（ｂ）に示す如く、厚いＣＶ
Ｄ酸化膜３０９を全面に形成した後に、通常の写真蝕刻
工程を経てｎ- 型拡散層３０６の一部と接続する開口部
３１０を形成する。さらに、全面に第２のｎ+ 型ポリシ
リコン膜３１１とＣＶＤ酸化膜を形成した後、通常の写
真蝕刻工程を経てパターニングを行なう。その後ｎ+型
ポリシリコン膜３１３を形成後、反応性イオンエッチン
グ法によりＣＶＤ酸化膜のサイドウォールのｎ+ 型ポリ
シリコン膜３１３のみを残してエッチングする。更に、
フッ化アンモニウムでＣＶＤ酸化膜を除去する。タンタ
ル酸化膜３１４をＴａ（ＯＣ2 Ｈ5 ）5 をソースガスと
して使用して、熱ＣＶＤ法により１５０オングストロー
ムの厚さに形成する。Subsequently, as shown in FIG.
After forming the D oxide film 309 on the entire surface, an opening 310 connected to a part of the n − type diffusion layer 306 is formed through a normal photolithography process. Further, after forming a second n + type polysilicon film 311 and a CVD oxide film on the entire surface, patterning is performed through a normal photolithography process. Thereafter, after forming an n + -type polysilicon film 313, etching is performed by a reactive ion etching method while leaving only the n + -type polysilicon film 313 on the side wall of the CVD oxide film. Furthermore,
The CVD oxide film is removed with ammonium fluoride. A tantalum oxide film 314 is formed to a thickness of 150 Å by thermal CVD using Ta (OC 2 H 5 ) 5 as a source gas.
【００２８】最後に図３（ｃ）に示す如くＣＶＤ法でチ
タン窒化膜３１５を形成した後、通常の写真蝕刻工程を
経てパターニングする。最後に窒素雰囲気中５００℃で
１時間、熱処理を行なうことにより、以降の６００℃の
熱処理を経ても劣化しない１トランジスタ／１キャパシ
タのＤＲＡＭセルが完成する。Finally, after a titanium nitride film 315 is formed by a CVD method as shown in FIG. 3C, patterning is performed through a normal photolithography process. Finally, heat treatment is performed in a nitrogen atmosphere at 500 ° C. for 1 hour, thereby completing a one-transistor / one-capacitor DRAM cell which does not deteriorate even after the subsequent heat treatment at 600 ° C.
【００２９】なお、チタン窒化膜３１５の形成後の熱処
理は、Ａｒ雰囲気中で行なってもよいし、真空中で行な
ってもよい。また、窒素雰囲気中７５０℃で１分間、熱
処理を行なってもよい。The heat treatment after the formation of the titanium nitride film 315 may be performed in an Ar atmosphere or in a vacuum. Further, heat treatment may be performed at 750 ° C. for 1 minute in a nitrogen atmosphere.
【００３０】次に本発明の実施例の効果について説明す
る。上記各実施例の効果は図４のグラフで説明されてい
る。すなわち、窒化チタン形成後に窒素雰囲気中５００
℃で１時間熱処理を行なう本実施例のものと、上記の熱
処理を行なわずに６００℃で熱処理を行なう従来のもの
の場合のリーク電流の変化をそれぞれ２本のグラフ曲線
で比較されている。このグラフでも明らかなように、上
述の実施例に教示された工程にしたがって作成されたキ
ャパシタとチタン窒化膜形成後に熱処理を行わなかった
キャパシタを、６００℃で１時間、窒素雰囲気中で熱処
理した場合におけるリーク電流特性として比較すると、
本実施例で製造された半導体装置は、従来の方法で製造
されたものに比較してその絶縁膜のリーク電流の増加が
少ない。このリーク電流の増加が抑制されるのは次の理
由によると思われる。すなわち、上部電極であるチタン
窒化膜形成後の熱処理でタンタル酸化膜の劣化を抑制し
ながら、窒化チタン膜が安定化され、その後の熱処理で
窒化チタンと酸化タンタルの反応によるリーク電流の増
加が抑制されるためであると推定される。Next, the effects of the embodiment of the present invention will be described. The effect of each of the above embodiments is described in the graph of FIG. In other words, after forming titanium nitride,
The changes in the leakage current in the case of the present embodiment in which the heat treatment is performed at 1 ° C. for one hour and the change in the leak current in the case of the conventional one in which the heat treatment is performed at 600 ° C. without performing the above heat treatment are compared by two graph curves. As is clear from this graph, when a capacitor prepared according to the process taught in the above embodiment and a capacitor not subjected to the heat treatment after forming the titanium nitride film are subjected to a heat treatment at 600 ° C. for 1 hour in a nitrogen atmosphere. Comparing the leakage current characteristics at
In the semiconductor device manufactured in this embodiment, the increase in the leak current of the insulating film is smaller than that in the semiconductor device manufactured by the conventional method. It is considered that the increase in the leak current is suppressed for the following reason. That is, the titanium nitride film is stabilized while suppressing the deterioration of the tantalum oxide film by the heat treatment after the formation of the titanium nitride film serving as the upper electrode, and the increase in leak current due to the reaction between titanium nitride and tantalum oxide is suppressed by the subsequent heat treatment. It is presumed that this is done.
【００３１】なお、本発明は上記の各実施例に限定され
るものではない。本実施例ではキャパシタ絶縁膜にタン
タル酸化膜を用いているが、他の絶縁膜を用いることも
可能である。例えば、酸化ジルコニウム、酸化ハフニウ
ム、酸化チタン、チタン酸ストロンチウム、チタン酸バ
リウム、チタン酸鉛、ＰＺＴ（チタン酸ジルコン酸
鉛）、ＰＬＺＴ（チタン酸ジルコン酸ランタン鉛）など
を使用してもよい。また、本実施例では上部電極に窒化
チタンを用いているが、その代りに窒化タンタル、窒化
タングステン、窒化アルミニウム、窒化ジルコニウム、
窒化ハフニウムなどを用いてもよい。さらに、下部電極
または上部電極、下部電極の両方に金属窒化物を用いて
もよい。また、本実施例に示されたスタックドキャパシ
タ以外のトレンチキャパシタなどの他の３次元構造を成
すキャパシタにも本製造方法を適用することが可能であ
る。The present invention is not limited to the above embodiments. In this embodiment, a tantalum oxide film is used for the capacitor insulating film, but another insulating film can be used. For example, zirconium oxide, hafnium oxide, titanium oxide, strontium titanate, barium titanate, lead titanate, PZT (lead zirconate titanate), PLZT (lead lanthanum zirconate titanate), or the like may be used. Further, in this embodiment, titanium nitride is used for the upper electrode, but instead, tantalum nitride, tungsten nitride, aluminum nitride, zirconium nitride,
Hafnium nitride or the like may be used. Further, metal nitride may be used for both the lower electrode, the upper electrode, and the lower electrode. Further, the present manufacturing method can be applied to a capacitor having another three-dimensional structure such as a trench capacitor other than the stacked capacitor shown in the present embodiment.
【００３２】なお、その他本発明の趣旨を逸脱しない範
囲で種々変形して実施することも可能である。Various modifications can be made without departing from the spirit of the present invention.
【００３３】[0033]
【発明の効果】以上に詳述した如く本発明によれば、窒
化金属を形成後所望の熱工程の前に一旦、真空中あるい
は非酸化性雰囲気中で熱処理を行なうことで、所望の熱
工程後においてもリーク電流の増加の無い低リーク電流
で大容量のキャパシタを実現することができる。その結
果、高信頼性を有する高集積半導体素子の実現に寄与す
ることが可能となる。As described in detail above, according to the present invention, a heat treatment is performed once in a vacuum or in a non-oxidizing atmosphere after forming a metal nitride and before a desired heat treatment. Even afterwards, a large-capacity capacitor with a low leakage current without an increase in the leakage current can be realized. As a result, it is possible to contribute to the realization of highly integrated semiconductor elements having high reliability.
【図１】本発明の第１実施例に関わるＤＲＡＭセルの製
造工程を示す断面図。FIG. 1 is a sectional view showing a manufacturing process of a DRAM cell according to a first embodiment of the present invention.
【図２】本発明の第２実施例に関わるＤＲＡＭセルの製
造工程を示す断面図。FIG. 2 is a sectional view showing a manufacturing process of a DRAM cell according to a second embodiment of the present invention.
【図３】本発明の第３実施例に関わるＤＲＡＭセルの製
造工程を示す断面図。FIG. 3 is a sectional view showing a manufacturing process of a DRAM cell according to a third embodiment of the present invention.
【図４】上記各実施例の効果を説明するためのリーク電
流の変化を表わすグラフ。FIG. 4 is a graph showing a change in leakage current for explaining the effect of each of the above embodiments.
１０１，２０１，３０１ …Ｐ型シリコン基板、 １０２，２０２，３０３ …ＣＶＤ酸化膜、 １０３，２０３，３０４ …薄い熱酸化膜、 １０４，２０４，３０５ …第１のｎ+ 型ポリシリコ
ン、 １０５，２０５，３０６ …ｎ- 型拡散層、 １０６，２０６，３０９ …ＣＶＤ酸化膜、 １０７，２０７，３１０ …開口部、 １０８ …第２のｎ+ 型ポリシリコン、 １０９，２０９，３１４ …タンタル酸化膜、 １１０，３１５ …チタン窒化膜、 １２０，２２０，３２０ …溝、 ２０８ …第１のチタン窒化膜、 ２１０ …第２のチタン窒化膜、 ３０７ …タングステンシリサイド膜、 ３０８ …多結晶シリコン膜、 ３１１，３１３ …ｎ+ 型ポリシリコン膜。101, 201, 301 ... P-type silicon substrate, 102, 202, 303 ... CVD oxide film, 103, 203, 304 ... thin thermal oxide film, 104, 204, 305 ... first n + type polysilicon, 105, 205 , 306... N-type diffusion layer, 106, 206, 309... CVD oxide film, 107, 207, 310... Opening, 108... Second n + type polysilicon, 109, 209, 314. , 315: titanium nitride film, 120, 220, 320: groove, 208: first titanium nitride film, 210: second titanium nitride film, 307: tungsten silicide film, 308: polycrystalline silicon film, 311, 313 ... n + type polysilicon film.
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/04 H01L 21/822 H01L 21/8242 H01L 27/108 Continued on the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 27/04 H01L 21/822 H01L 21/8242 H01L 27/108
Claims (2)
の電極を構成する導電体膜が金属窒化物からなり、金属
酸化物を容量絶縁膜とする半導体装置の製造方法であっ
て、前記容量絶縁膜を形成する工程と、 前記少なくとも一方の電極として、窒化チタン、窒化タ
ングステン、窒化アルミニウムからなる群から選択され
た金属窒化物からなる上部電極を、前記容量絶縁膜上に
直接形成する工程と、 前記上部電極を形成後、熱工程を経る前に非酸化性雰囲
気または真空中で所定の熱処理を施す工程と、 を具備することを特徴とする半導体装置の製造方法。1. A method for manufacturing a semiconductor device, wherein a conductive film formed on a semiconductor substrate and constituting at least one electrode is made of metal nitride and a metal oxide is used as a capacitor insulating film.
Forming the capacitive insulating film; and forming the at least one electrode as titanium nitride or titanium nitride.
Selected from the group consisting of tungsten, aluminum nitride
An upper electrode made of metal nitride is placed on the capacitor insulating film.
A method for manufacturing a semiconductor device , comprising: a step of directly forming a semiconductor element; and a step of performing a predetermined heat treatment in a non-oxidizing atmosphere or a vacuum after forming the upper electrode and before passing through a heating step.
ウム、チタン酸バリウム、チタン酸鉛、ＰＺＴ、ＰＬ
Ｚ、ＰＬＺＴからなる群から選択された材料からなるこ
とを特徴とする請求項１に記載の半導体装置の製造方
法。Wherein said semiconductor device is a capacitor, before Symbol capacitor insulating film, a tantalum oxide, strontium titanate, barium titanate, lead titanate, PZT, PL
2. The method according to claim 1, wherein the semiconductor device is made of a material selected from the group consisting of Z and PLZT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19111992A JP3219856B2 (en) | 1992-07-17 | 1992-07-17 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19111992A JP3219856B2 (en) | 1992-07-17 | 1992-07-17 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0637257A JPH0637257A (en) | 1994-02-10 |
| JP3219856B2 true JP3219856B2 (en) | 2001-10-15 |
Family
ID=16269185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19111992A Expired - Fee Related JP3219856B2 (en) | 1992-07-17 | 1992-07-17 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3219856B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0370516A3 (en) * | 1988-11-25 | 1991-11-21 | William Ormond | Tie bar monotoring system |
| KR100284737B1 (en) * | 1998-03-26 | 2001-03-15 | 윤종용 | Manufacturing method of capacitor having dielectric film of high dielectric constant in semiconductor device |
| KR100293713B1 (en) | 1998-12-22 | 2001-07-12 | 박종섭 | Method of manufacturing capacitor of memory element |
-
1992
- 1992-07-17 JP JP19111992A patent/JP3219856B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0637257A (en) | 1994-02-10 |
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