JP2003158201A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce resistance of a word line, contact resistance of a diffused layer with a retrieved electrode, the size of a DRAM cell, to suppress a junction leakage and to assure a pressure resistance between the word line and the electrode, and to stabilize transistor characteristics in a DRAM. SOLUTION: The semiconductor device comprises the word line 18 embedded in a groove 14 formed on a semiconductor substrate 11 via a gate insulating film 16, and a diffused layer 19 formed on the surface side of the substrate 11 at the sidewall of the groove 14. The semiconductor device further comprises a silicide layer 21 formed on the upper layer of the word line 18, a stopper insulating film 75 formed to embed the groove 14 on the silicide layer 21, and the retrieved electrode 24 connected to the diffused layer 19 in the state in which the electrode 24 is overlapped on the word line 18 via the stopper insulating film 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a DRAM (Dynamic Rand).
om Access Memory) manufacturing method.

[0002]

2. Description of the Related Art Due to the ever-increasing miniaturization competition, a composite device in which a large capacity DRAM and a high speed logic element are mounted on one chip has been developed. That DR
As an example of the AM structure, the memory cell gate of the DRAM is stacked on the substrate, and a so-called self-aligned contact is used to take out the diffusion layer of the memory cell transistor.

However, stack-type DRAMs also have various problems.

In order to maintain transistor performance, DRA
The substrate concentration is increasing more and more with the shrinking of the M memory cell, and the junction leak in the DRAM region is approaching a severe state. Therefore, the electric field applied to the junction is becoming stronger and stronger, and it has become difficult to suppress the junction leak of the ppm order in the megabit class DRAM. That is, it has become difficult to maintain the data retention characteristic (generally called tail characteristic) of the DRAM, which has been conventionally controllable with a margin. If nothing is done, the only effective means is to increase the capacity of the capacitor for each generation.

Further, as DRAM cells are reduced in size,
The contact area between the diffusion layer and the take-out electrode is narrowed, and the contact resistance is increasing with a double power for each generation. In the generation after 0.1 μm, this contact resistance is expected to be several kilo Ω, and it is expected that it will be comparable to the ON resistance of the word transistor of the memory cell. Therefore, not only the cell transistor but also the variation of the contact resistance severely affects the DRAM operation (especially high speed operation), and further precision is required in manufacturing.
In particular, in DRAMs that are required to operate at high speed, securing the performance is a problem.

Further, with the reduction of the size of the DRAM cell,
The interlayer insulation distance between the word line and the extraction contact of the diffusion layer formed beside it is getting closer with each generation. In manufacturing a megabit class DRAM, 20 nm to 30 nm is said to be the limit distance in order to secure this withstand voltage. Therefore, in the DRAM of the generation of 0.1 μm or later, it is necessary to form the extraction contact of the diffusion layer at a distance less than the withstand voltage limit distance.

Conventionally, tungsten silicide (WSi
₂ ) The word line of DRAM, which has been slowed down by adopting the polycide structure of / doped polysilicon, has become severer in aspect ratio with the recent miniaturization, and has a sufficiently low resistance to suppress the delay of the word line. Has become difficult to obtain. Stacked DR that requires particularly high-speed operation
In AM and the like, this word line delay becomes a serious problem that affects the access time of DRAM. As a technique for reducing the resistance of the gate, a low resistance of the wiring by salicide has been put into practical use. However, in order to apply to the gate of the DRAM memory cell, the salicide is not formed in the diffusion layer of the DRAM in order to prevent the DRAM memory cell from being downsized because the offset silicon oxide film cannot be used and to maintain the data retention characteristic. Due to difficulties such as requiring a process, it cannot be usually adopted.

Further, the storage node contact of the DRAM is also required to have an opening having no margin due to its cell size, and like the diffusion layer contact, an opening within the withstand voltage limit is required.
There is a need for a technology that efficiently suppresses the increase in resistance with the narrow contact diameter.

On the other hand, the transistor performance of the logic section has been remarkably improved, and in particular, the p ⁺ gate electrode for suppressing the off-leakage of the p-channel transistor has come into general use. However, in this p ⁺ gate, the impurity boron is diffused toward the substrate side by the heat treatment. It is known to include the problem of so-called "penetration" and cause serious problems such as characteristic variations of p-channel transistors and depletion of gate electrodes. DRAM
Widely used for diffusion layer contacts. Doped polysilicon is a material in which activation by heat treatment is indispensable, and attention must be paid to the compatibility during mixed mounting.

As described above, even if the technology that can be tolerated in the current 0.18 .mu.m generation is managed in the future.
From the 1 μm generation onward, it is expected that some measures will be required along with further thinning of the gate oxide film, and that drastic improvement of the stacked DRAM structure will be required to maintain the performance trend of the chip.

An element structure capable of solving all the problems of the above-mentioned items which are expected to become apparent in a stacked type DRAM having a size of 0.1 μm or more and still maintaining the tendency (trend) of chip performance, and manufacturing thereof. As a method, DR
Embedding the AM word line in the groove formed in the substrate, Tren
A ch Access Transistor (TAT) DRAM cell has been proposed by the applicant. Among them, a technique for clarifying a method for forming a substrate profile that realizes a drastic improvement in data retention characteristics of DRAM has been proposed.

Next, the basic structure of the trench access transistor DRAM cell in the DRAM section will be described with reference to the schematic sectional view of FIG.

As shown in FIG. 5, an STI (Shallow Trench Isola) is formed on a semiconductor substrate 511 made of a silicon substrate.
element isolation region 512 for isolating the memory element region. Further semiconductor substrate 5
The buffer layer 5 covering the element isolation region 512
71 is formed of, for example, a silicon oxide film.

In the semiconductor substrate 511 in the memory element region, a P-type well diffusion layer 513, for example, an upper surface having a thickness of 15 is formed.
It is formed so that the thickness in the depth direction is, for example, about 0.8 μm in a state deeper than 0 nm to 200 nm.
Further, a groove 514 which penetrates the buffer layer 571 and forms a word line (including a gate electrode) in the DRAM region is formed in the element isolation region 512 and the semiconductor substrate 511. The depth of the groove 514 is, for example, 100 nm to
Well diffusion layer 51 having a thickness of about 150 nm and formed previously
The semiconductor substrate 511 is formed so as to remain between 3 and the bottom of the groove 514.

Further, a channel diffusion layer 515 is formed on the semiconductor substrate 511 between the bottom of the groove 514 and the well diffusion layer 513. A gate insulating film 516 is formed on the inner surface of the groove 514 and on the semiconductor substrate 511.
For example, it is formed of a silicon oxide film having a thickness of about 1.5 nm to 5 nm.

Further, a word line (including a gate electrode) 518 made of, for example, a phosphorus-doped polysilicon film via the gate insulating film 516 so as to fill each groove 514.
Are formed. The word line 518 has a lower layer formed of a polysilicon layer and an upper layer formed of a silicide (for example, salicide) layer 521. A sidewall insulating film 520 is formed of, for example, a silicon nitride film on the sidewall of the trench 514 on the polysilicon layer of the word line 118. The surface of the word line 518 is at least the distance to the extraction electrode 524, which will be described later, and the surface of the word line 518 is above the groove 514.
11 is formed so as to be lower than the surface. for that reason,
The withstand voltage distance between the diffusion layer and the extraction electrode 524 described later is secured.

Further, the semiconductor substrate 511 in the DRAM area
A diffusion layer 519 serving as a source / drain is formed in the.

A cap insulating film 580 is formed of, for example, a silicon nitride film on the entire surface of the semiconductor substrate 511. Further, a first insulating film (insulating film) 522 is formed. The surface of the first insulating film 522 is flattened. A connection hole 523 is formed in the first insulating film 522 so as to penetrate the cap insulating film 580, the buffer layer 571 and the like and reach the diffusion layer 519 in the DRAM region. It is desirable that the connection hole 523 be formed as large as possible in diameter so that the extraction electrode can contact the entire surface of the diffusion layer 519. Thereby, the contact resistance can be reduced.

In the drawings, the state in which some misalignment has occurred is intentionally described. However, if excessive over-etching is not performed at the time of opening the contact hole, the physical properties of the extraction electrode 124 of the word line formed in the contact hole 523 will be described. It is possible to secure the appropriate distance. In the projection design viewed from above, the connection hole 523 completely overlaps the word line (gate electrode) 518. A lead-out electrode 524 made of, for example, phosphorus-doped polysilicon is formed in the connection hole 523.

One of the characteristics of the DRAM structure described above is that the word line in the DRAM section is arranged below the substrate with respect to the diffusion layer to be in contact therewith, so that the reactivity of high selectivity such as self-aligned contact is achieved. It is not necessary to use ion etching technology or the like. Therefore, D
It is possible to make the opening diameter as large as possible so that the entire diffusion layer of the RAM can be taken out as a contact.

Further, even if some misalignment occurs, the physical distance between the word line and the take-out electrode can be secured unless excessive overetching is performed at the time of opening the contact.

[0022]

However, as shown in FIG. 6, the alignment is largely deviated and the diffusion layer 519
In the case where the extraction electrode 524 connected to is overlapped with the lower layer word line (gate electrode) 518 and the upper layer salicide layer 521, the diffusion layer 519 and the word line ( Current may leak between the gate electrode) 518 and in the worst case, a short circuit may occur.

[0023]

SUMMARY OF THE INVENTION The present invention is a semiconductor device and a method of manufacturing the same which are made to solve the above problems.

In the semiconductor device of the present invention, a word line is embedded in a groove formed in a semiconductor substrate via a gate insulating film, and a diffusion layer is formed on a side surface of the groove on a surface side of the semiconductor substrate. In the device, a silicide layer formed on the word line upper layer, a stopper insulating film formed on the silicide layer so as to fill the groove,
An extraction electrode connected to the diffusion layer in a state of overlapping above the word line via the stopper insulating film is provided.

In the above semiconductor device, since the stopper insulating film is formed on the silicide layer formed in the upper layer of the word line in the groove so as to fill the groove, in the state of overlapping above the word line, Even if the lead-out electrode connected to the diffusion layer formed on the semiconductor substrate at the side wall of the groove is formed, the stopper insulating film prevents the lead-out electrode from being connected to the silicide layer. Therefore, the occurrence of a short circuit between the word line and the extraction electrode is prevented,
In addition, a sufficient breakdown voltage is secured during that period. Therefore, the semiconductor device has high reliability.

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an element isolation region on a semiconductor substrate and then forming a diffusion layer on the front surface side of the semiconductor substrate, and the semiconductor substrate and the element isolation region at predetermined positions. A step of forming a groove, a step of forming a gate insulating film on the inner surface of the groove, a step of forming a lower layer of the word line so as to fill the inside of the groove with the upper part of the groove left, A step of forming a sidewall insulating film on the side wall of the groove on the lower layer, and a step of forming an upper silicide layer on the lower layer of the word line,
Forming a stopper insulating film on the silicide layer to fill the upper portion of the groove; forming an insulating film covering the semiconductor substrate; and overlapping the word line with the stopper insulating film interposed therebetween. The method includes a step of forming a connection hole reaching the diffusion layer in the insulating film, and a step of forming a lead electrode in the connection hole.

In the method of manufacturing a semiconductor device described above, after forming the silicide layer to be the upper layer of the word line in the groove and forming the stopper insulating film filling the upper part of the groove, the semiconductor substrate on the side wall of the groove is then formed. When the connection hole connecting to the formed diffusion layer is formed, the connection hole is not formed deeper than that due to the stopper insulating film. That is, the connection hole does not reach the silicide layer. Therefore, even if the lead-out electrode is formed in the connection hole, the lead-out electrode is not connected to the word line (silicide layer), so that the lead-out electrode and the word line are prevented from being short-circuited, and the withstand voltage between them is sufficient. Reserved. Therefore, a highly reliable semiconductor device is formed.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG.

As shown in FIG. 1, the semiconductor substrate 11 is composed of a silicon substrate having a p-type impurity concentration of about 1 × 10 ¹⁷ / cm ³ , for example. The semiconductor substrate 11 has an element isolation region 1 for electrically isolating a memory element region.
2 is formed. The element isolation region 12 is formed by, for example, STI (Shallow Trench Isolation) technology.
For example, it is formed to a depth of about 0.1 μm to 0.2 μm. Further, on the semiconductor substrate 11, a buffer layer 71 covering the element isolation region 12 is formed of, for example, a silicon oxide film with a thickness of, for example, 20 nm to 40 nm.

The buffer layer 71 is necessary for manufacturing, has a function as a buffer film when the well diffusion layer 13 is formed, and has a substrate concentration of a transistor (access transistor) of a memory element described later. Has a function as a stopper for ion implantation to a region which becomes a junction of the DRAM at the time of ion implantation for adjusting the ion implantation, and further, when the silicide layer 21 is formed on the surface of the word line 18 buried in the trench 14, It has a function of preventing the silicide layer 21 from being formed in the diffusion layer 19 in the region.

In the semiconductor substrate 11 in the memory element region, the well diffusion layer 13 has, for example, an upper surface of 150 nm to 2 nm.
It is formed in a state deeper than 00 nm and has a thickness in the depth direction of, for example, about 0.8 μm. The well diffusion layer 13 is of P type and is formed by introducing, for example, boron. For example, when the well diffusion layer 13 is formed by ion implantation, boron is used as an ion species and the dose amount is, for example, 5 × 10 5. ^{It is about 12} / cm ^{2 to} 7 × 10 ¹² / cm ² .

Further, if necessary, the element isolation region 12
An element isolation diffusion layer (not shown) may be formed on the lower semiconductor substrate 11.

Further, a groove 14 is formed in the element isolation region 12 and the semiconductor substrate 11 so as to penetrate the buffer layer 71 and in which a word line (including a gate electrode) in the DRAM region is formed. The depth of this groove 14 is, for example, 100 n
The thickness is about m to 150 nm, and the semiconductor substrate 11 is formed so as to remain between the well diffusion layer 13 previously formed and the bottom of the groove 14. The depth of the groove 14 formed in the semiconductor substrate 11 and the groove 1 formed in the element isolation region 12
The depth of 4 may have some difference.

The edge of the bottom of the groove 14 is preferably formed in a so-called round shape in order to avoid the electric field concentration of the cell transistor, and the width of the groove 14 is the channel of the access transistor of the memory element. Since it becomes long, it is desirable that the side wall of the groove 14 is formed as perpendicular to the surface of the semiconductor substrate 11 as possible.

Further, the bottom of the groove 14 and the well expansion are
The channel diffusion layer 1 is formed on the semiconductor substrate 11 between the diffusion layer 13 and the diffusion layer 13.
5 is formed. Word Transistor in DRAM area
As the channel diffusion layer 15 of the
1.0 x 10¹⁸/ Cm³~ 1.0 x 10¹⁹/ Cm³) To
The area that must be dug down is the semiconductor substrate 11.
Which is the semiconductor substrate 11 portion at the bottom of the groove 14 and is on the groove 14 side.
The concentration of the semiconductor substrate 11 on the walls and the upper part should be extremely low.
Yes. Therefore, the semiconductor substrate below the diffusion layer 19 described later
11 parts are extremely low density (for example, 1.0 × 10¹⁷/ C
m³~ 1.0 x 10 ¹⁸/ Cm³) Is formed.

A gate insulating film 16 is formed on the inner surface of the groove 14 and on the semiconductor substrate 11. Since the gate insulating film 16 has a film thickness slightly thicker than that of the most advanced logic transistor and the gate length is formed a little longer, the silicon oxide film formed by thermal oxidation is applied even in this generation. Is possible. Therefore, the gate insulating film 16 in the DRAM region has, for example, 1.5 nm to 5 n.
It is formed of a silicon oxide film having a thickness of about m.

Further, a word line (including a gate electrode) 18 made of, for example, a phosphorus-doped polysilicon film is formed via the gate insulating film 16 so as to fill each groove 14. The word line 18 has a lower layer made of a polysilicon layer and an upper layer made of silicide (for example, salicide).
It is formed of the layer 21. Further, a sidewall insulating film 20 is formed of, for example, a silicon nitride film on the sidewall of the trench 14 on the polysilicon layer of the word line 18. The surface of the word line 18 is, for example, 50 degrees from the surface of the semiconductor substrate 11 above the groove 14 as a distance at which a withstand voltage with respect to the extraction electrode 24 described later is secured.
It is formed so as to decrease by about 100 nm to 100 nm.

Further, the silicide layer 21 is made of, for example, cobalt silicide (CoSi ₂ ), titanium silicide (TiSi ₂ ), nickel silicide (NiSi ₂ ), or the like. The sidewall insulating film 20 has a function of ensuring a breakdown voltage between the silicide layer 21 and the diffusion layer 19. It should be noted that there may be some difference between the depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12.

The groove 14 on the silicide layer 21 is filled with a stopper insulating film 75. The stopper insulating film 75 is made of, for example, silicon nitride, and is an insulating material having a function of preventing the connection hole 23 from reaching the silicide layer 21 when the connection hole 23 reaching the diffusion layer 19 described later is formed by etching. I wish I had it. Therefore, in the stopper insulating film 75, in addition to silicon nitride,
It is also possible to use an organic insulating material.

Further, on the semiconductor substrate 11 in the DRAM region, diffusion layers 19 serving as sources / drains are formed. Phosphorus is used as an N-type impurity in the diffusion layer 19 and has a concentration of 1 × 10 ¹⁸ / cm ^{3 to} 3 × 10 ¹⁸ / cm 3.
^{It is 3} . Therefore, the semiconductor substrate 11 in this region
Is set to a very thin concentration of about 1 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ¹⁷ / cm ³ .

Therefore, this NP junction becomes an ultra-graded junction (a junction having a very gentle concentration gradient). In the junction in such a state, the electric field at the time of reverse bias is relaxed,
In the megabit class DRAM, it dramatically contributes to the suppression of the junction leakage current, which occurs in a defective bit of only ppm order and is about two orders of magnitude worse than usual. The data retention characteristic of the defective bit dominates the chip performance of the DRAM, and will be an important technique for maintaining the data retention characteristic in the future DRAM.

For example, if the substrate concentration is about 5 × 10 ¹⁶ / cm ³ , a data retention characteristic of 500 ms or more at 85 ° C. can be expected, which is actually the data retention characteristic of previous generations 4-5 generations. It is expected that the performance will be comparable to. The access transistor in the DRAM area is
Since the channel is formed in a so-called round shape in the semiconductor substrate 11, it is possible to secure a long effective channel length, and to apply a back bias to use the transistor characteristics of the DRAM cell with a severe short channel effect. It can also be achieved.

On the entire surface of the semiconductor substrate 11, a cap insulating film 80 is formed of, for example, a silicon nitride film having a thickness of 10 nm to 20 nm. This cap insulating film 80
Is effective in suppressing the junction leak in the salicide forming portion, but it is not necessary to form it if it is unnecessary. further,
A first insulating film (insulating film) 22 is formed on the entire surface.
The surface of the first insulating film 22 is flattened.

A connection hole 23 is formed in the first insulating film 22 so as to penetrate the cap insulating film 80, the buffer layer 71 and the like and reach the diffusion layer 19 in the DRAM region. It is desirable that the connection hole 23 be formed as large as possible in diameter so that the extraction electrode can contact the entire surface of the diffusion layer 19. Thereby, the contact resistance can be reduced.

In the connection hole 23, for example, a lead-out electrode 2 for a word line formed of phosphorus-doped polysilicon.
4 are formed. The surface of the first insulating film 22 is flattened so that the upper surface of the extraction electrode 24 is flush with the surface of the second insulating film 22.

In the semiconductor device having the above structure, FIG. 1 intentionally describes a state in which some misalignment occurs. In such a case, even if excessive over-etching is performed when the connection hole 23 is opened, the stopper insulating film 75 prevents the connection hole 23 from approaching or reaching the silicide layer 21, and is formed in the connection hole 23. It is possible to secure a physical distance between the extraction electrodes 24. In the projection design viewed from above, the connection hole 23 completely overlaps the word line (gate electrode) 18.

Further, an example of a capacitor formed on the above-described cell transistor will be described with reference to the schematic cross-sectional view of FIG.

As shown in FIG. 2, the structure below the first insulating film 22 and the extraction electrode 24 is the same as the structure described with reference to FIG. The etching stop layer 2 covering the extraction electrode 24 is formed on the first insulating film 22.
5 is formed.

The etching stop layer 25, the first
In the insulating film 22, the cap insulating film 80, and the stopper insulating film 75, a connection hole 26 reaching the silicide layer 21 (21w) on the word line 18 in the DRAM region is formed. An extraction electrode 27 is formed in the connection hole 26. The extraction electrode 27 is composed of a tungsten film 86 formed so as to fill the inside of the connection hole 26 with an adhesion layer 85 composed of a titanium nitride film interposed therebetween.

A second insulating film 31 is formed on the etching stop layer 25 to cover the extraction electrode 27. The second insulating film 31 is formed by depositing, for example, a silicon oxide film to a thickness of 50 nm to 150 nm.

A bit contact hole 32 connected to the extraction electrode 24 is formed in the second insulating film 31 and the etching stop layer 25. A bit line 34 is formed on the second insulating film 31, and a part of the bit line 34 is connected to the extraction electrode 24 through the bit contact hole 32. Further, the local wiring 35 is formed on the second insulating film 31. Bit line 34
The local wiring 35 is formed of, for example, a tungsten film 37.
The adhesive layer 36 is formed on the lower portion of the above, and the cap layer 38 is formed on the upper portion thereof.

An etching stopper layer 41 and a third insulating film 42 are formed on the second insulating film 22 to cover the bit line 34 and the local wiring 35. The etching stopper layer 41 is an ALD silicon nitride film and is formed to have a thickness of, for example, 30 nm to 50 nm.

A connection hole 43 is formed from the third insulating film 42 to the etching stopper layer 25, in which storage node contacts reaching the extraction electrodes 24, 24 of the storage node contact are provided. This connection hole 43
Inside, the etching stopper layer 41 remains on the side wall of the bit line 34 as a side wall having a film thickness that ensures the breakdown voltage between the bit line and the storage node contact. Further, a storage node contact 44 connected to the extraction electrode 24 is formed in the connection hole 43. The storage node contact 44 is made of, for example, tungsten, titanium,
It is made of a material such as titanium nitride, tantalum, tantalum nitride, or ruthenium oxide. The third insulating film 4
The second surface is flattened together with the upper surface of the storage node contact 44, for example.

A fourth insulating film 45 is formed on the third insulating film 42. A recess 46 in which a capacitor is formed is formed in the fourth insulating film 45 so that the upper surface of the storage node contact 44 is exposed at the bottom thereof. In the recess 46, MIM (Me
A capacitor 91 having a tal / insulator / Metal structure is formed. It is expected that the MIM structure capacitor 91 will be indispensable in a DRAM having a size of 0.1 μm or later. At present, as an example, electrodes 92 and 94 are made of a ruthenium (Ru) or ruthenium oxide (RuO) -based material, and the electrodes 92 and 9 are used.
The BST (BaTiO 3) is formed on the dielectric film 93 formed between
A mixed crystal type film of ₃ and SrTiO ₃ is used.

The MIM is formed on the fourth insulating film 45.
A fifth insulating film 47 covering the structured capacitor 91 is formed. The surface of the fifth insulating film 47 is flattened. The fifth insulating film 47 to the first insulating film 22 are provided with a capacitor extraction electrode, a word line extraction electrode,
Connection hole 1 for forming local wiring take-out electrodes, etc.
11, 112, 113 and the like are formed.

In each connection hole 111, 112, 113, etc.,
A capacitor extraction electrode 121, a word line extraction electrode 122, a local wiring extraction electrode 123, etc. are formed.

Further, a sixth insulating film 48 is formed on the fifth insulating film 47. In the sixth insulating film 48, the wiring groove 13 reaching each electrode 121, 122, 123 is formed.
1, 132, 133 are formed, and the wiring grooves 131 to 13 are formed.
The first wirings 141 to 143 are formed on the third wiring 3. The first wirings 141 to 143 are, for example, copper wirings.
Although not shown, an upper layer wiring is further formed if necessary. The electrodes 121 to 123 and the wirings 141 to 143 are provided with a commonly known adhesion layer and barrier layer depending on the materials of the electrodes, wirings, and insulating films.

In the above semiconductor device, the semiconductor substrate 1 between the lower portion of the groove 14 in which a channel is formed and the well diffusion layer 13 is formed.
Since the channel diffusion layer 15 is formed in No. 1, the impurity concentration of the region between the groove 14 and the well diffusion layer 13 is higher than the impurity concentration of the semiconductor substrate 11 around the groove 14. Further, since the concentration of the semiconductor substrate 11 under the diffusion layer 19 serving as the source / drain is extremely low, the electric field of the junction of the diffusion layer 19 is weakened, so that it is possible to suppress the junction leak on the order of ppm. Thereby,
The data retention characteristics are extremely improved.

Since the silicide layer 21 is formed above the word line 18, the resistance of the word line 18 is reduced, the delay problem is avoided, and the operation speed is improved. At the same time, the contact resistance to the word line 18 is reduced.

Moreover, since the diffusion layer is formed on the surface side of the semiconductor substrate 11 and the word line is buried in the groove formed in the semiconductor substrate via the gate insulating film, the word line is formed in the channel. It is formed so as to surround the semiconductor substrate on the bottom side of the groove. Therefore, since an effective channel length is sufficiently secured, a back bias is applied to the memory element (for example, D
The transistor characteristics of RAM) are stabilized.

Since the diffusion layer 19 has a low impurity concentration in the depth direction, the concentration of the semiconductor substrate 11 below the diffusion layer 19 in the memory element region should not be made as high as required for the cell transistor. Therefore, the electric field of the junction is relaxed, and the performance of the data retention characteristic, which becomes more severe as the cell size of the memory element is reduced, is maintained.

In addition, the word line 1 embedded in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16.
Since the take-out electrode 24 connected to the diffusion layer 19 formed on the surface of the semiconductor substrate 11 is formed on the semiconductor substrate 8 while overlapping the word line 18 via the first insulating film 22, the word It becomes possible to secure a sufficient film thickness of 20 nm to 30 nm or more for the first insulating film 22 on the line 18. Thereby, the breakdown voltage with respect to the extraction electrode connected to the diffusion layer 19 is secured. Therefore, since the entire surface of the diffusion layer 19 of the memory element is used for the contact, the effective area can be effectively used. Therefore, the lowest resistance value that can be realized by the cell design is realized, so that the contact resistance can be reduced.

Next, an embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to manufacturing process sectional views of FIGS. In FIGS. 3 and 4, the same components as those described with reference to FIGS. 1 and 2 are designated by the same reference numerals.

As shown in FIG. 3A, the semiconductor substrate 1
1, for example, 1 × 10¹⁷/ Cm ³P-type impurities
A silicon substrate having a concentration is prepared. For example STI
(Shallow Trench Isolation)
An element isolation region for isolating the memory element region is formed on the conductor substrate 11.
Area 12 is formed. The element isolation region 12 has, for example, 0.
It is formed to a depth of about 1 μm to 0.2 μm. Then
Chemical vapor deposition (hereinafter referred to as CVD, CVD is chemical
 Vapor Deposition) on the element isolation region 12
On the semiconductor substrate 11 so as to cover
The buffer layer 71 made of a silicon film, for example, 20 nm to 40 n
It is formed to a thickness of m.

Next, by ion implantation, for example, boron is introduced into the semiconductor substrate 11 in the memory element region of the DRAM to form the well diffusion layer 13. As the ion implantation conditions, boron is used as the ion species, the dose amount is, for example, about 5 × 10 ¹² / cm ^{2 to} 7 × 10 ¹² / cm ^2, and the depth is deeper than the depth of the groove formed later. Eg 1
It is formed deeper than 50 nm to 200 nm and slightly deeper than the depth of the element isolation region 12. The well diffusion layer 13 has a thickness in the depth direction of, for example, about 0.8 μm.

If necessary, punch-through stop ion implantation is performed. At this stage, the substrate concentration adjusting ion implantation (so-called channel doping) for the access transistor of the DRAM cell is not yet performed. Furthermore, if necessary, an element isolation diffusion layer (not shown) may be formed on the semiconductor substrate 11 below the element isolation region 12.

The buffer layer 71 has a function as a buffer film when the well diffusion layer 13 is formed.
Further, DR is performed at the time of ion implantation for adjusting the substrate concentration of the transistor (access transistor) of the memory element, which is performed later
It functions as a stopper for ion implantation in a region that becomes a junction of AM. Further, it has a function of preventing the formation of salicide in the diffusion layer in the DRAM region when forming salicide on the surface of the word line buried in the groove.

Next, as shown in FIG. 3B, a resist mask (not shown) having an opening in a region where a word line is formed is formed by resist coating and a lithographic technique, and then an etching process is performed to form a buffer. The layer 71, the element isolation region 12, and the semiconductor substrate 11 are etched (for example, continuously etched) to form the element isolation region 1
A trench 14 in which a word line (including a gate electrode) in the DRAM region is formed is formed in the 2 (field) and the semiconductor substrate 11. The depth of the groove 14 is, for example, 100 nm to 1
The thickness is about 50 nm, and the semiconductor substrate 11 is left between the well diffusion layer 13 previously formed and the bottom of this groove 14. The depth of the groove 14 formed in the semiconductor substrate 11 and the depth of the groove 14 formed in the element isolation region 12 may be slightly different.

Since the groove 14 is formed only in the DRAM region, it is desirable that the edge portion at the bottom of the groove 14 be formed in a so-called round shape in order to avoid electric field concentration of the cell transistor. Since the width of 14 corresponds to the channel length of the access transistor of the memory device, it is desirable that the sidewall of the groove 14 be formed as perpendicular to the surface of the semiconductor substrate 11 as possible. In addition, DR
The buffer layer 71 formed in the AM region is etched at the same time when the element isolation region 12 is etched.
After that, the resist mask is removed by a normal removal technique.

Next, a sacrificial oxide film (not shown) is formed on the entire exposed surface of the semiconductor substrate 11 by, eg, thermal oxidation to a thickness of, for example, 10 nm to 20 nm.

Then, channel doping of the access transistor in the DRAM region is performed to form a channel diffusion layer 15 between the bottom of the groove 14 and the well diffusion layer 13. As the channel diffusion layer 15 of the word transistor in the DRAM region, a high concentration (for example, 1.0 × 10
^The region that must be ¹⁸ / cm ^{3 to} 1.0 × 10 ¹⁹ / cm ³ ) is the semiconductor substrate 11 (11a) portion at the bottom of the groove 14 in which the semiconductor substrate 11 is dug, and the semiconductor on the side wall and the upper portion of the groove 14 It is almost unnecessary to perform ion implantation as the substrate concentration on the substrate 11. Further, in the above ion implantation, the buffer layer 71 initially provided on the surface of the semiconductor substrate 11 serves as a mask for ion implantation, so that the channel diffusion layer 1 is formed only on the bottom of the groove 14 without using a new mask.
5 can be formed. Therefore, the semiconductor substrate 11 below the diffusion layer 19 [see (3) in FIG. 3] described below.
The part has an extremely low concentration (for example, 1.0 × 10 ¹⁷ / cm ³
˜1.0 × 10 ¹⁸ / cm ³ ) can be formed.

Then, the sacrificial oxide film (not shown) is removed by, for example, wet etching. Then D
A gate insulating film 16 is formed on the inner surface of the groove 14 in the RAM region and on the semiconductor substrate 11 by a normal gate oxide film forming method. Note that when a logic element is formed, the gate insulating film in the logic portion is formed separately in a later step, so that no special care needs to be taken at this stage.
The gate insulating film 16 in the DRAM section is formed of, for example, silicon oxide (SiO ₂ ) or silicon oxynitride (SiON).
Is desirable.

As shown in FIG. 3C, a gate forming film is formed of a phosphorus-doped polysilicon film on the gate insulating film 16 so as to fill each groove 14 in the DRAM region. Since this gate forming film is used only for the word line in the DRAM region, phosphorus-doped polysilicon which is an N ⁺ gate material can be used. Further, the gate forming film is formed to have a film thickness of 50 nm to 150 nm, and the film thickness is set to a film thickness optimized only for forming a groove-shaped word line.

Next, the gate forming film is etched back so that the gate forming film remains inside the groove 14. As a result, a word line (which partially functions as a gate electrode) 18 made of a gate forming film is formed inside the groove 14. At that time, the surface of the word line 18 is 50 nm or less from the surface of the semiconductor substrate 11.
By performing etch back of the gate forming film so as to reduce the thickness by about 100 nm, the withstand voltage distance between the extraction electrode and the diffusion layer to be formed later is secured. In this etch back, the gate insulating film 16 functions as an etching stop layer.

Further, using a doped polysilicon film, a silicon oxide film or the like as a mask, ion implantation for forming a source / drain is performed on the semiconductor substrate 11 in the DRAM region to form a diffusion layer 19. This ion implantation is
The profile should be as sharp as possible only on the top of the diffusion layer. As the ion implantation conditions, implantation energy that penetrates the buffer layer 71 is sufficient, so the implantation energy is set to, for example, 20 keV to 50 keV, and the dose amount is 1 × 10 ¹⁸ / cm ^{2 to} 3 × 10 ¹⁸ /
Set to cm ² . If ion implantation is performed under these conditions, D
Almost no ions are implanted into the semiconductor substrate 11 below the diffusion layer 19 in the RAM area. Therefore, the semiconductor substrate 11 in this region is 1 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ¹⁷ / cm 3.
It becomes possible to set a very thin density of about ³ .

Therefore, this NP junction becomes an ultra-graded junction (a junction having a very gentle concentration gradient). In the junction in such a state, the electric field at the time of reverse bias is relaxed,
In the megabit class DRAM, it dramatically contributes to the suppression of the junction leakage current, which occurs in a defective bit of only ppm order and is about two orders of magnitude worse than usual. The data retention characteristic of the defective bit dominates the chip performance of the DRAM, and will be an important technique for maintaining the data retention characteristic in the future DRAM.

For example, if the substrate concentration is about 5 × 10 ¹⁶ / cm ³ , a data retention characteristic of 500 ms or more at 85 ° C. can be expected, which is actually the data retention characteristic of the 4th to 5th generations previous data. It is expected that the performance will be comparable to. The access transistor in the DRAM area is
Since the channel is formed in a so-called round shape in the semiconductor substrate 11, it is possible to secure a long effective channel length, and to apply a back bias to use the transistor characteristics of the DRAM cell with a severe short channel effect. It can also be achieved.

In the above-mentioned ion implantation, the ion implantation is performed slightly shallower in consideration of diffusion due to the heat treatment for forming the gate in the DRAM region later. However, since the DRAM gate has a substrate embedded type, the channel in the DRAM region is Since it is formed at the bottom of the groove 14 forming the buried gate, there is no problem. Further, since it is activated by the subsequent heat treatment, it is not necessary to perform the heat treatment at this stage.

Next, a protective film for protecting the gate in the DRAM region is formed, for example, with a thin silicon nitride film (for example, with a thickness of 10).
nm to 50 nm). This protective film is etched by, for example, reactive ion etching (RIE) to form D
The word line 18 in the RAM area is exposed. As a result. A side wall insulating film 20 made of a protective film is formed on the side wall of the groove 14 on the word line line 18. This sidewall insulating film 20 is used for the word line 18 at the time of forming salicide later.
Contributes to ensuring the withstand voltage. In the reactive ion etching, the diffusion layer 19 in the DRAM area is not exposed, that is, the buffer layer 7 is formed on the diffusion layer 19.
It is important to leave 1.

Further, using the usual salicide technique,
A silicide layer 21 is formed on the word line 18 in the DRAM area.
Are selectively formed. In this way, the silicide layer 21 is selectively formed on the word line 18 in the DRAM region which needs to realize low resistance. Examples of the silicide layer include cobalt silicide (CoSi ₂ ), titanium silicide (TiSi ₂ ) and nickel silicide (Ni).
Si ₂ ) or the like can be used.

Next, as shown in FIG. 3D, a stopper insulating film 75, for example, silicon nitride having a thickness of 50 nm to 150 nm is formed on the entire surface by, for example, a CVD method so as to fill the groove 14 on the silicide layer 21. It is formed by depositing to a thickness. The stopper insulating film 75 needs to be deposited to a thickness necessary to fill the silicide layer 21 of the groove 14. It should be noted that this film is used as an etching mask when opening a connection hole later, and it is necessary to have a film thickness that does not reach the lower silicide layer 21 during the etching.

Next, as shown in FIG. 4 (5), the entire surface is flattened by using a flattening technique such as chemical mechanical polishing or an etch back technique, and only the trench 14 on the silicide layer 21 is exposed. The stopper insulating film 75 is left. After that, a cap insulating film 80, for example, a silicon nitride film is formed on the entire surface.
It is formed by depositing to a thickness of 0 nm to 20 nm. The cap insulating film 80 is effective in suppressing the junction leak in the silicide forming portion, but it is not necessary to form it if it is unnecessary. Although not shown, a silicide layer may be formed on the gate electrodes of the transistors in the peripheral circuit portion to form a salicide structure to reduce the resistance of the gate electrodes.

Next, as shown in (6) of FIG. 4, after the first insulating film (insulating film) 22 is formed on the entire surface, the surface of the first insulating film 22 is flattened by CMP. The method for flattening the surface of the first insulating film 22 is not limited to CMP as long as the method can realize the flattening, and for example, an etch back method or the like can be used.

Next, the first insulating film 22 is penetrated and DR
A connection hole 23 reaching the diffusion layer 19 in the AM region is formed.
At this time, the word line (gate electrode) 18 in the DRAM area
Is disposed below the surface of the semiconductor substrate with respect to the diffusion layer 19 to be contacted, it is not necessary to use a special technique such as self-aligned contact. Further, it is desirable to form the opening diameter of the connection hole 23 as large as possible so that the entire surface of the diffusion layer 19 of the DRAM can be brought into contact with the extraction electrode. Thereby, the contact resistance can be reduced.

Further, in (6) of FIG. 4, the state in which some misalignment has occurred is intentionally described. In such a case, even if excessive over-etching is performed when the connection hole 23 is opened, the stopper insulating film 75 prevents the connection hole 2 from being formed.
3 can be prevented from approaching or reaching the silicide layer 21 of the word line 18, and the physical distance of the extraction electrode formed in the connection hole 23 can be secured. In the projection design viewed from above, the connection hole 23 completely overlaps the word line (gate electrode) 18.

Next, as shown in FIG. 4 (7), a lead electrode forming film is formed on the first insulating film 22 so as to fill the inside of the connection hole 23. The lead-out electrode forming film is formed by depositing phosphorus-doped polysilicon of N-type doped polysilicon to a thickness of 100 nm to 150 nm, for example. As for the lead-out electrode forming film for taking out the diffusion layer, it is desirable that phosphorus-doped polysilicon is selected in the conventional manner in consideration of reduction of junction leak in the DRAM region. At this stage, heat treatment for activation is unnecessary.

Thereafter, the excess take-out electrode forming film (phosphorus-doped polysilicon) on the first insulating film 22 is removed by using a flattening technique such as chemical mechanical polishing, and the connection hole 2 is formed.
A lead-out electrode 24 made of a lead-out electrode forming film connected to the diffusion layer 19 is formed in the inside 3, and the surface of the first insulating film 22 is flattened by polishing.

Then, heat treatment is performed. By this heat treatment, the extraction electrode 24 made of polysilicon in the DRAM region is activated. In this heat treatment, 900 ° C, 10
RTA (Rapid Thermal Annealing) of about a second is sufficient, but thermal annealing using a normal furnace can be performed. Since the high temperature heating process is not performed in the subsequent steps, for example, when a logic element is formed at the same time as the DRAM, the diffusion of boron from the gate electrode of the logic element, so-called “penetration” is minimized. Can be suppressed to.

After that, a bit line, a bit contact, a capacitor, an interlayer insulating film, a wiring, etc. are formed by a normal process.

In the method of manufacturing a semiconductor device, the trench 1 is formed after forming the silicide layer 21 to be the upper layer of the word line 18.
Since the stopper insulating film 75 that fills the upper part of 4 is formed, when the connecting hole 23 reaching the diffusion layer 19 is formed thereafter, the connecting hole 23 is not formed deeper than the stopper insulating film 75. That is, the connection hole 23 does not reach the silicide layer 21. Therefore, the connection hole 2
Even if the extraction electrode 24 is formed in the
Since 4 is not connected to the silicide layer 21, a short circuit between the extraction electrode 24 and the word line 18 is prevented. At the same time, the breakdown voltage with respect to the extraction electrode 24 connected to the diffusion layer 19 is secured. In this way, the entire surface of the diffusion layer 19 of the memory element can be used for the contact, so that the effective area can be effectively used. Further, since the lowest resistance value that can be realized by the cell design is realized, the contact resistance can be reduced. This enables high-speed DRAM operation with less parasitic resistance.

Furthermore, in the above-mentioned method of manufacturing a semiconductor device,
Since the buffer layer 71 is formed, the channel diffusion layer 1 is formed on the semiconductor substrate 11 at the bottom of the groove 14 thereafter.
When the impurity forming 5 is introduced, the buffer layer 71 serves as a mask to selectively form the semiconductor substrate 1 at the bottom of the groove 14.
Impurities are introduced into 1 to form the channel diffusion layer 15.

Thus, the lower portion of the groove 14 and the well diffusion layer 1 are
Since the channel diffusion layer 15 is formed in the semiconductor substrate 11 between the trenches 3 and 3, the impurity concentration of the region between the trench 14 and the well diffusion layer 13 becomes higher than the impurity concentration of the semiconductor substrate 11 around the trenches 14. Moreover, since the concentration of the semiconductor substrate 11 below the diffusion layer 19 serving as the source / drain can be kept extremely low, the electric field at the junction of the diffusion layer 19 is weakened. For this reason, it is possible to suppress the junction leak on the order of ppm, thereby forming a semiconductor device having extremely excellent data retention characteristics.

Further, since the silicide layer 21 is formed above the word line 18, the resistance of the word line 18 is reduced and the problem of delay is avoided. At the same time, the contact resistance to the word line 18 is reduced.

The diffusion layer 19 is formed on the front surface side of the semiconductor substrate 11.
Is formed so that the word line 18 is embedded in the groove 14 formed in the semiconductor substrate 11 via the gate insulating film 16, so that the channel is a semiconductor on the bottom side of the groove 14 in which the word line 18 is formed. It is formed so as to surround the substrate 11. Therefore, since an effective channel length is sufficiently secured, a back bias is applied to stabilize the transistor characteristics of a memory element (for example, DRAM) having a severe short channel effect.

Since the diffusion layer 19 in the memory element region is formed so that the impurity concentration becomes low in the depth direction, the semiconductor substrate 1 below the diffusion layer 19 in the memory element region is formed.
Since the one concentration does not have to be as high as required for the cell transistor, the electric field of the junction is relaxed, and the performance of the data retention characteristic, which becomes more severe as the cell of the memory element is reduced, is maintained.

The semiconductor device and the method of manufacturing the same according to the present invention described above can be applied to a DRAM, a semiconductor device in which a DRAM and a logic element are mounted together, and the like. For example, when manufacturing a semiconductor device in which a DRAM and a logic element are mounted together, first, the manufacturing method of the present invention is applied to form the cell transistor of the DRAM, and then form the transistor of the logic element. Then DR
While forming AM bit lines, capacitors, etc.,
Wiring in the RAM area, wiring in the logic area, and the like may be formed.

[0097]

As described above, according to the semiconductor device of the present invention, the stopper insulating film is formed on the silicide layer formed in the upper layer of the word line in the groove so as to fill the groove. , Even if the take-out electrode connected to the diffusion layer formed on the semiconductor substrate on the side wall of the groove is formed in the state of overlapping above the word line, the stopper insulating film causes a short circuit between the take-out electrode and the silicide layer. It can be prevented, and a sufficient pressure resistance can be secured during that time. Therefore, a highly reliable semiconductor device can be provided.

According to the method of manufacturing a semiconductor device of the present invention,
Since the stopper insulating film filling the upper part of the groove is formed after forming the silicide layer to be the upper layer of the word line in the groove, the connection hole for connecting to the diffusion layer formed in the semiconductor substrate on the side wall of the groove is formed thereafter. At this time, the connection hole is not formed deeper than that by the stopper insulating film. That is, the stopper insulating film can prevent the occurrence of a short circuit between the take-out electrode and the silicide layer, and can ensure a sufficient withstand voltage therebetween. Therefore, a highly reliable semiconductor device can be formed.

[Brief description of drawings]

FIG. 1 is a schematic configuration cross-sectional view showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic configuration cross-sectional view of a DRAM having the configuration of the semiconductor device of the present invention.

FIG. 3 is a manufacturing step sectional view showing an embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a manufacturing step sectional view showing the embodiment of the method for manufacturing the semiconductor device of the present invention.

FIG. 5 is a schematic configuration sectional view showing a conventional technique.

FIG. 6 is a schematic sectional view showing a problem.

[Explanation of symbols]

11 ... Semiconductor substrate, 14 ... Groove, 16 ... Gate insulating film, 1
8 ... Word line, 19 ... Diffusion layer, 21 ... Silicide layer, 2
4 ... take-out electrode, 75 ... stopper insulating film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/108 H01L 21/88 JF term (reference) 4M104 AA01 BB01 DD02 DD07 DD78 DD84 EE05 EE17 FF01 FF14 GG16 HH16 5F033 HH04 HH25 HH27 JJ04 KK01 LL04 MM07 MM30 QQ09 QQ13 QQ25 QQ31 QQ37 QQ48 QQ70 QQ73 RR06 TT06 VV16 XX10 XX15 XX31 5F083 AD04 AD10 AD31 GA02 JA10 MA43 PR23 JA40 JA43 JA43 JA38 JA38 JA38 JA39 JA38 JA38 JA39 JA38 JA38 JA39 JA38 JA39 JA38 JA38 JA39 JA38 JA38 JA39 JA38 JA38 JA39 JA38 JA39 PR36 PR39 PR40 PR42 PR52

Claims (2)

[Claims] 1. A semiconductor device in which a word line is buried in a groove formed in a semiconductor substrate via a gate insulating film, and a diffusion layer is formed on a side surface of the groove on a surface side of the semiconductor substrate, A silicide layer formed on the word line upper layer, a stopper insulating film formed on the silicide layer so as to fill the groove, and the diffusion in a state of being overlapped above the word line via the stopper insulating film. A semiconductor device comprising: an extraction electrode connected to the layer. 2. A step of forming a diffusion layer on the surface side of the semiconductor substrate after forming an element isolation region on the semiconductor substrate, a step of forming a groove at a predetermined position of the semiconductor substrate and the element isolation region, Forming a gate insulating film on the inner surface of the groove; forming a lower layer of the word line so as to fill the inside of the groove with the upper portion of the groove left; Forming a wall insulating film; forming an upper silicide layer on the lower layer of the word line; forming a stopper insulating film filling the upper portion of the groove on the silicide layer; and the semiconductor substrate A step of forming an insulating film covering the insulating film; a step of forming a connection hole in the insulating film, the connection hole overlapping the word line and passing through the stopper insulating film and reaching the diffusion layer; And a step of forming a lead electrode in the connection hole.