JP3216277B2 - High-efficiency coding device and decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency encoding apparatus and a decoding apparatus for packing encoded data after ADRC encoding processing in a sync block and adding a parity to the encoded data for transmission.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a system configuration of a digital VTR.

In FIG. 1, a video signal SVi supplied to an input terminal is converted into a digital signal by an A / D converter 12 and supplied to a blocking circuit 13. The blocking circuit 13 is provided for an ADRC encoder 14, which will be described later. In the blocking circuit 13, a screen is divided and a large number of unit blocks are formed.

[0004] Data of each block output from the blocking circuit 13 is supplied to an ADRC encoder 14 and
DRC encoding processing is performed. FIG. 3 shows an example of the ADRC encoder.

[0005] In the figure, data DI of each block output from a blocking circuit 13 is a maximum value detection circuit 141.
And the minimum value detection circuit 142. The maximum value detection circuit 141 detects the maximum value MAX for each block, and supplies the maximum value MAX to the subtraction circuit 143. The minimum value detection circuit 142 detects a minimum value MIN for each block, and the minimum value MIN is supplied to subtraction circuits 143 and 144. In the subtraction circuit 143, the minimum value MIN is subtracted from the maximum value MAX.
The dynamic range DR of the block represented by (X-MIN) is obtained.

The data DI is supplied to a subtraction circuit 144 via a delay circuit 145. The delay circuit 145 delays the data DI of each block by a time necessary to detect the maximum value MAX and the minimum value MIN. In the subtraction circuit 144, the minimum value MIN is calculated from the data DI.
Is subtracted to form data PDI after minimum value removal.

[0007] The data PDI from the subtraction circuit 144 from which the minimum value has been removed is supplied to the quantization circuit 146. The dynamic range DR from the subtraction circuit 143 is supplied to the quantization circuit 146, and quantization adapted to the dynamic range DR is performed. As the quantization bit number, a bit number smaller than the original bit number (eg, 8 bits), for example, 4 bits is used. For simplicity, assuming that the number of quantization bits is 2 bits, a level range obtained by dividing the dynamic range DR into four is set, and a 2-bit code signal is assigned according to which level range the data PDI belongs to.

Returning to FIG. 2, the minimum value MIN and dynamic range DR for each block output from the ADRC encoder 14 and the code signal DT for each pixel are supplied to the packing circuit 15 as compressed data. FIG.
The figure shows data per block after the DRC encoding process.

Here, one block (one sync block)
The compression data per hit is: dynamic range DR = L1 bit, minimum value MIN = L2 bit, bit plane = k
Bit × n (k is the number of quantization bits, n is the number of pixels constituting one block). In the packing circuit 15, compressed data of each block is, for example, 8 bits (1 byte).
Packed in units.

FIG. 5 shows a conventional packing process. However, this is an example in which L1 = L2 = 8. First, the dynamic range DR and the minimum value MI constituting the additional data
N are arranged, and subsequently, n code signals DT constituting a bit plane are sequentially packed. In this case, the direction of each code signal DT is the byte direction ,
The direction is orthogonal to the column direction of the bits forming the unit .

[0011] The compressed data packed by the packing circuit 15 is supplied to a parity adding circuit 16, where parity is added in units of bytes, and a modulating circuit 17 performs a modulation process. 19
And recorded on a magnetic tape (not shown).

Next, a signal reproduced from the magnetic tape by the reproduction head 20 is supplied to a demodulation circuit 22 via a reproduction amplifier 21 and subjected to demodulation processing, and then supplied to an error correction circuit 23 to be added by a recording system. The error correction process is performed using the parity.

The compressed data output from the error correction circuit 23 is subjected to a depacking process in the depacking circuit 24, which is the reverse of the packing process in the above-described packing circuit 15 of the recording system. ADRC in the system ADRC encoder 14
An ADRC decoding process opposite to the encoding process is performed.

The data output from the ADRC decoder 25 is supplied to a block disassembly circuit 26, which performs a block disassembly process reverse to that of the recording block operation circuit 13, and
The signal is converted into an analog signal by the D / A converter 27, and the video signal SVo is output to the output terminal.

[0015]

In the packing circuit 15 of the recording system of the digital VTR shown in FIG. 2, when packing a bit plane as described above, the direction of each code signal DT is the same as the direction orthogonal to the byte direction. Therefore, if an error flag is set in a portion where the bit plane is packed (see FIG. 5), one error flag in units of 8 bits propagates to image data of 8 samples after ADRC decoding processing. was there.

Accordingly, an object of the present invention is to reduce the number of samples of image data to which one error flag propagates.

[0017]

According to the present invention, there is provided packing means for rearranging, in a sync block, a code signal for each pixel which has been subjected to a coding process by quantization adapted to a dynamic range for each block, in the high efficiency encoding device for transmitting by adding a parity byte sync block, packing means is for packing sequentially packed in column direction of bits constituting bytes code signal subsequent to the additional code .

[0018]

[Action] In the present invention, for packing sequentially packed code signal constituting the bit plane in the column direction of the bits constituting bytes, that one of the error flag kept small number of samples of the image data to be propagated Becomes possible.

[0019]

An embodiment of the present invention will be described below with reference to the drawings.

The digital VTR of this embodiment is also basically configured as shown in FIG. In the packing circuit 15 of the recording system, compressed data (dynamic range DR, minimum value MIN, and n code signals DT) for each block are packed in units of 8 bits (1 byte). A packing process different from the example is performed.

FIG. 1 shows the packing process of this embodiment. Here, the bit number L1 of the dynamic range DR
In this example, the bit number L2 of the minimum value MIN is 8 bits, and the bit number k of the code signal DT is 3 bits.

In this embodiment, first, a dynamic range DR and a minimum value MIN constituting the additional data are arranged, and subsequently, n code signals DT constituting a bit plane are sequentially packed. In this case, each code signal DT constitutes a byte direction , that is, a byte unit.
Bits are sequentially arranged in the column direction .

Since the above-described packing process is performed by the packing circuit 15, the reverse depacking process is performed in the reproducing depacking circuit 24 (see FIG. 2).

The present embodiment is configured as described above, and the rest is configured similarly to the example of FIG.

In the present embodiment, at the time of the packing process in the packing circuit 15, the n code signals DT constituting the bit plane are sequentially packed in the byte direction and packed. In this case, the number of code signals DT included in the 8 bits constituting each byte is four or less. Therefore, even if an error flag is raised in a portion where a bit plane is packed (see FIG. 1), one error flag in 8-bit units only propagates to image data of 4 samples or less after ADRC decoding processing. is there. Therefore, according to the present example, the number of samples of the image data to which one error flag propagates can be reduced as compared with the conventional example.

In the above-described embodiment, the case where the number k of bits of the code signal DT is 3 bits has been described. However, the present invention is similarly applicable to a case where a fixed-length ADRC encoding process with other bits is performed. Can be applied to In addition, it goes without saying that the present invention can be similarly applied to a case where a variable length ADRC encoding process for quantizing with a different number of bits according to the range of the dynamic range DR is performed.

[0027]

According to the present invention, since a code signal constituting a bit plane is sequentially packed in a column direction of bits constituting a byte unit and packed, an image in which one error flag propagates is obtained. The number of data samples can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a packing process in an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a system configuration example of a digital VTR.

FIG. 3 is a block diagram illustrating a configuration of an ADRC encoder.

FIG. 4 is a diagram showing data per block after ADRC encoding processing.

FIG. 5 is a diagram for explaining a conventional packing process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input terminal 13 Blocking circuit 14 ADRC encoder 15 Packing circuit 16 Parity addition circuit 17 Modulation circuit 22 Demodulation circuit 23 Error correction circuit 24 Depacking circuit 25 ADRC decoder 26 Block decomposition circuit 28 Output terminal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-89782 (JP, A) JP-A-3-24885 (JP, A) JP-A-4-245881 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04N 5/91-5/956 H04N 7/24

Claims (2)

(57) [Claims] 1. A packing means for rearranging a code signal for each pixel after being subjected to an encoding process by quantization adapted to a dynamic range for each block in a sync block, wherein parity is provided in byte units of the sync block. in the high efficiency encoding device for transmitting by adding, the packing means, high efficiency, characterized in that packing the code signal subsequent to the additional code sequentially packed in column direction of bits forming the byte Encoding device. 2. The data transmitted from the high-efficiency coding apparatus according to claim 1 is subjected to error correction with added parity and depacking processing, and then to decoding processing. Decoding device.