JP3125471B2 - Framer for digital video signal recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a framing apparatus for a digital video signal recording apparatus using ADRC, DCT or the like as high efficiency coding.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by a rotary head, for example, is known. Because of the large amount of digital video signal information,
High-efficiency coding for compressing the transmission data amount is often adopted. ADRC, DCT (Discrete Cosin
e Transform) have been proposed.

The ADRC is disclosed in, for example,
No. 89, finds a dynamic range defined by a maximum value and a minimum value of a plurality of pixels included in a two-dimensional block, and performs high-efficiency coding that performs coding adapted to the dynamic range. is there. ADRC
As one of them, a variable length ADRC has been proposed. AD
RC is calculated for each two-dimensional block in which the dynamic range DR (difference between the maximum value MAX and the minimum value MIN) is, for example, (8 lines × 8 pixels = 64 pixels). Further, the minimum level (minimum value) in the block is removed from the input pixel data. The pixel data after the removal of the minimum value is converted to a representative level. In this quantization, the dynamic range D detected in four level ranges corresponding to a smaller number of bits than the original number of quantized bits, for example, 2 bits, is used.
This is a process of dividing R, detecting a level range to which each pixel data in the block belongs, and generating a code signal indicating the level range. Therefore, the 8-bit data of each pixel is compressed to 2 bits and transmitted.

The variable-length ADRC prepares, for example, 0, 1, 2, and 3 bits (0 bits means that no quantization code is transmitted) as the number of quantization bits, and when the dynamic range DR is large, The number of quantization bits is increased, and when the number is small, the number of quantization bits is reduced.

A digital VTR using a magnetic tape,
In a disk recording device or the like using a disk-shaped recording medium, one field or one frame of video data is usually recorded on a plurality of tracks. However, as described above, when a variable length output is formed, the data amount during these predetermined periods fluctuates. For this reason, a buffering process is required to reduce the amount of data during a predetermined period to a target value or less.

As a buffering method of the variable length ADRC, the present applicant forms a cumulative dynamic range frequency distribution as described in Japanese Patent Application No. 61-257586, and this frequency distribution , A threshold value for determining the number of allocated bits prepared in advance is applied to determine the amount of generated information for a predetermined period, for example, one frame period, and control so that the generated information amount does not exceed the target value. Suggesting things.

That is, in order to control the amount of generated information, a frequency distribution table for a predetermined period of the dynamic range DR, for example, one frame period, is formed, and this frequency distribution table is converted into a cumulative frequency distribution table. On the other hand, T1, T2, T
3, a threshold value of T4 (T1 <T2 <T3 <T4) is applied. In the case of (DR <T1), the allocated bit number n is set to 0 (that is, no code signal is transmitted), and (T
If 1 ≦ DR <T2, then (n = 1) and (T
If 2 ≦ DR <T3, then (n = 2) and (T
If 3 ≦ DR <T4, then (n = 3) and (T
If (4 ≦ DR), (n = 4). A plurality of thresholds T1 to T4 are prepared, and among the plurality of thresholds T1 to T4, a threshold that can reduce the amount of data generated during a predetermined period to a predetermined value or less is determined. Each of the plurality of thresholds T1 to T4 is identified by a threshold number. Although the determined threshold value itself may be recorded, the threshold number is usually recorded / reproduced.

The DCT converts an image of one frame into, for example, an (8 × 8) block structure, and performs a cosine transform process on this block, which is a type of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to a variable length coding process such as a run length code and a Huffman code. During transmission, to facilitate data processing on the playback side,
A code signal, which is an encoded output, is inserted into a data area of a fixed-length sync block, and the code signal is framed to form a sync block to which a sync signal and an ID signal are added.

Even when DCT is used for high-efficiency encoding, a variable-length encoded output is generated, so that a buffering process is required. As an example, a buffering process that controls the data amount in a predetermined period (referred to as a buffering unit) shorter than one field or one frame, so that even in the entire one field or one frame period, the data amount is eventually equal to or less than a target value Has been proposed.
The buffering process is a process of requantizing the coefficient data of the alternating current generated by the DCT at an appropriate quantization step to suppress the transmission data amount to a target value or less. A quantization step or a code of a quantization number indicating the quantization step is inserted into the transmission data together with the encoded data.

Digital VT employing variable length ADRC
FIG. 4 shows a configuration on the recording side of an example of R, and FIG. 5 shows a configuration on the reproducing side. In FIG. 4, a video signal is supplied from an input terminal 1 and one sample is digitized by the A / D converter 2 into, for example, 8 bits. This A
Output data of the / D converter 2 is supplied to the blocking circuit 3. In this embodiment, the blocking circuit 3 divides the effective area of one frame into blocks each having a size of (4 × 4) pixels, (8 × 8) pixels, or the like.

A digital video signal scan-converted in the order of blocks from the blocking circuit 3 is supplied to a block coding circuit 4. The block encoding circuit 4 compresses the digital video signal using the variable length ADRC code. Further, a buffering process for controlling the data amount of the variable length coded output occurring during a predetermined period, for example, a period corresponding to one track, to a predetermined value or less is performed. A threshold number indicating threshold information generated in a buffering unit, a dynamic range DR and a minimum value MIN generated for each block, and quantized data D corresponding to each pixel in the block
T is output data of the block encoding circuit 4.

The output data of the block encoding circuit 4 is supplied to a parity generation circuit 5. The parity generation circuit 5
A parity of an error correction code is generated, and recording data having a structure in which sync blocks are continuous is generated. As the error correction code, for example, a product code for performing error correction coding in each of a horizontal direction and a vertical direction of a matrix arrangement of data can be adopted. A sync block synchronization signal and an ID signal are added to the encoded data and parity. The recording data in which the sync blocks continue are supplied to the channel encoding circuit 6,
It undergoes channel coding processing to reduce the DC component.

The output data of the channel encoding circuit 6 is converted into a bit stream and further supplied to a rotary head 8 via a recording amplifier 7 so that the recording data is transferred to a magnetic tape 9.
Recorded as diagonal tracks on top. Usually, a plurality of rotating heads are used, but only one head is shown for simplicity.

FIG. 5 shows the configuration of the reproduction side of the digital VTR. Reproduced data taken out of the magnetic tape 9 by the rotary head 8 is supplied to a channel decoding circuit 13 via a reproducing amplifier 12, and is subjected to channel coding decoding. The output data of the channel decoding circuit 13 is supplied to an error correction circuit 14, where separation of various data from recording data and error correction are performed. Error correction circuit 14
The output data generated from the data includes an error flag indicating the presence or absence of an error after error correction, in addition to the reproduction data.

The output data of the error correction circuit 14 is supplied to a reproduction threshold number determination circuit 15. The reproduction threshold number determining circuit 15 refers to the error flag and determines a non-error reproduction threshold number as correct. This reproduction threshold number is supplied to the block decoding circuit 16. This decoding circuit 16 performs variable length ADRC decoding using the reproduction threshold number.

The decoded data of the block decoding circuit 16, that is, restored data corresponding to each pixel is supplied to the block decomposition circuit 17. The order of the data is returned from the order of the blocks to the order of the raster scanning by the block decomposition circuit 17. The output data of the block decomposition circuit 17 is supplied to an error correction circuit 18. The error correction circuit 18 interpolates data that cannot be corrected by the error correction code with peripheral pixel data. Output data of the error correction circuit 18 is supplied to a D / A converter 19, and restored data of the order of raster scanning corresponding to each pixel is obtained at an output terminal 20.

The threshold information in the variable length ADRC or the information of the requantization step in the DCT (collectively referred to as parameters) is important information in order to perform correct decoding on the reproduction side. Since one buffering period includes at least several sync blocks, parameter information is inserted into each sync block. Conventionally, protection by error correction code,
Decoding is performed using an error-free or corrected parameter.

[0018]

Conventionally, the threshold number determination circuit 15 has used the error-free threshold number candidate passed through the error correction circuit 14 as the reproduction threshold number as it is. In this method, the obtained correct threshold number cannot be effectively used for error correction. That is, if a correct threshold number is known, a plurality of threshold number candidates stored in buffer units can be corrected. As a result, the error rate of the reproduced data can be improved. However, in the conventional configuration, since the reproduction threshold number is determined after passing through the error correction circuit 14, the error correction circuit 14 must also correct the error of the threshold number.

Accordingly, an object of the present invention is to provide a framing apparatus of a digital video signal recording apparatus capable of protecting against errors of parameters such as threshold number information and quantization step width more than conventional methods. It is in.

[0020]

SUMMARY OF THE INVENTION According to the present invention, a digital video signal is encoded with high efficiency and variable length, and the amount of encoded output data for a predetermined period is stored in a data area of a plurality of sync blocks. A framing device in a digital video signal recording device, comprising: a buffering circuit for performing control so as to be accommodated; and a circuit for recording an output of the buffering circuit as recording data having a configuration of a sync block on a recording medium. A circuit for repeatedly inserting parameters used in the buffering circuit into a plurality of sync blocks; a circuit for creating a frequency distribution table of parameters in the reproduced data; And a decoding circuit for decoding high-efficiency coding with the maximum frequency parameter being correct. A framing device in Deo signal recording apparatus.

[0021]

According to the present invention, it is possible to correct a parameter error by utilizing repetitive insertion within a buffering period. Therefore, if the error correction is performed later, the error correction capability can be substantially increased.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a digital VTR will be described below with reference to the drawings. The configuration on the recording side is the same as that in FIG. 4, and the recording data amount is compressed by the variable length ADRC. FIG. 1 shows the configuration on the reproduction side of a digital VTR to which the present invention is applied.

The reproduction data taken out of the magnetic tape 9 by the rotary head 8 is supplied to a channel decoding circuit 13 via a reproduction amplifier 12, where the channel data is decoded. Output data of the channel decoding circuit 13 is supplied to a reproduction threshold number determination circuit 21. The reproduction threshold number output from the reproduction threshold number determination circuit 21 is supplied to the block decoding circuit 16, and reproduction data other than the reproduction threshold number is supplied to the error correction circuit 14.

A product code is used as an error correction code, and Reed-Solomon codes are respectively encoded for the horizontal and vertical data. Error correction using a horizontal error correction code and error correction using a vertical error correction code are performed. Output data generated from the error correction circuit 14 includes:
In addition to the reproduction data, an error flag indicating the presence or absence of an error after error correction is included.

The block decoding circuit 16 uses the reproduction threshold number from the reproduction threshold number determination circuit 21 and other reproduction data from the error correction circuit 14 to generate a variable length ADR.
C is decrypted. The decoding of the variable-length ADRC determines the number of bits allocated to the block from the values of the plurality of thresholds identified by the reproduction threshold number and the dynamic range DR of the block. Step width and quantization code DT determined by
And the minimum value MIN is added to the multiplied output. R in which a decoding table is stored instead of the multiplication circuit
OM can also be used.

The decoded data of the block decoding circuit 16, that is, restored data corresponding to each pixel, is supplied to the block decomposition circuit 17. The order of the data is returned from the order of the blocks to the order of the raster scanning by the block decomposition circuit 17. The output data of the block decomposition circuit 17 is supplied to an error correction circuit 18. The error correction circuit 18 interpolates data that cannot be corrected by the error correction code with peripheral pixel data. Output data of the error correction circuit 18 is supplied to a D / A converter 19, and restored data of the order of raster scanning corresponding to each pixel is obtained at an output terminal 20.

The present invention provides a reproduction threshold number determining circuit 2
Applies to 1. FIG. 2 is an example of the reproduction threshold number determination circuit 21. The reproduced data is supplied to a delay circuit 22 and a threshold number candidate extraction circuit 23.
This circuit 23 is provided for extracting threshold number data inserted at a predetermined position of each sync block of the reproduction data.

FIG. 3 schematically shows an example of data to be recorded / reproduced. The length of one sync block is L bytes, and one track of the magnetic tape includes K sync blocks. Buffering for controlling the data amount to be constant is performed in units of one track. The sync block includes a synchronization signal, an ID signal, a dynamic range DR for each block, a minimum value MIN, quantized data DT, and the like, but these are not shown. Threshold number data of 1 byte each is inserted at a predetermined position of each sync block.

On the recording side, a buffering process for suppressing the amount of information generated during a period corresponding to one track to a predetermined value or less is performed. That is, a plurality of sets each including the threshold values T1 to T4 are prepared, and among these sets, a set that suppresses the generated data amount to a predetermined value or less is determined. This set of determined thresholds is defined by a threshold number. Therefore, the threshold number data is the same for the K sync blocks. The extraction circuit 23 has a total
Extract byte threshold number data.

The extracted threshold number data is supplied to the frequency distribution table creation circuit 25. Frequency distribution table creation circuit 25
Is constituted by a memory having threshold number data as an address, and a frequency distribution table in which the frequencies of the same threshold number data are stored in each address is formed. A reproduction threshold number selection circuit 26 is provided for the frequency distribution table creation circuit 25.
Is connected. The selection circuit 26 is a circuit for determining the maximum frequency in the frequency distribution table relating to the reproduction data of one track as the reproduction threshold number.

The reproduction threshold number thus determined is supplied to the block decoding circuit 16 as described above, and is used for decoding the variable length ADRC. Further, the reproduction threshold number is supplied to the threshold number candidate correction circuit 24, and the threshold number in the reproduction data passed through the delay circuit 22 is replaced with this reproduction threshold number. This correction circuit 24
Is supplied to the error correction circuit 14. The error correction circuit 14 supplies reproduced data in which the threshold number data has been corrected, so that the probability of error correction for each sync block can be increased.

The reproduction threshold number determination circuit 21 shown in FIG.
A frequency distribution table is created. Instead, an average value of the separated K threshold number data is formed, and the average value is converted to an integer to obtain a reproduction threshold number. Is also good.

The present invention can be similarly applied to the transmission of information on the quantization step width when quantizing coefficient data generated by DCT.

[0034]

The present invention focuses on the fact that the parameters are the same during the buffering period, and can correct the errors of these parameters before the error correction by the error correction code. Therefore, in addition to being able to correct an error in the parameter itself, the correction capability can be substantially improved when the error correction code is performed later.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of a reproduction circuit of a digital VTR to which the present invention is applied.

FIG. 2 is a block diagram of an example of a circuit for determining a reproduction threshold number according to the present invention;

FIG. 3 is a schematic diagram illustrating a schematic configuration of a sync block to which the present invention can be applied;

FIG. 4 is an overall block diagram of a recording circuit of a digital VTR to which the present invention can be applied.

FIG. 5 is an overall block diagram of a reproduction circuit of a digital VTR to which the present invention can be applied.

[Explanation of symbols]

 14 error correction circuit 16 block decoding circuit 21 circuit for determining reproduction threshold number 25 circuit for creating frequency distribution table

Continuation of the front page (72) Inventor Masashi Uchida 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) References JP-A-6-113275 (JP, A) JP-A-61-144989 (JP, A) JP-A-63-111781 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/91-5/956 G11B 20/10-20/12 H04N 7 / 24-7/68 H04N 9/79-9/898

Claims (4)

(57) [Claims] 1. A buffer for performing high-efficiency encoding and variable-length encoding of a digital video signal, and for controlling a data amount of an encoded output for a predetermined period so as to be within a data area of a plurality of sync blocks. A framing device in a digital video signal recording device, comprising: ring means; and means for recording an output of the buffering means as recording data having a configuration of a sync block on a recording medium. Means for repeatedly inserting parameters to be used in the plurality of sync blocks; means for creating a frequency distribution table of the parameters in the reproduced data; and maximum frequency in the frequency distribution table. And a decoding means for decoding the high-efficiency coding with the parameters of A framing device in a video signal recording device. 2. A buffer for performing high-efficiency encoding and variable-length encoding of a digital video signal, and for controlling a data amount of an encoded output for a predetermined period so as to fall within a data area of a plurality of sync blocks. A framing device in a digital video signal recording device, comprising: ring means; and means for recording an output of the buffering means as recording data having a configuration of a sync block on a recording medium. Means for repeatedly inserting parameters to be used in the plurality of sync blocks; means for forming an average value of the parameters in the reproduced data; and high efficiency with the average value as a correct parameter. Frame in a digital video signal recording device comprising decoding means for decoding the encoding. Device. 3. The high-efficiency coding is variable-length ADRC, wherein a parameter is compared with a dynamic range of each ADRC block, and a plurality of pieces of threshold information for determining the number of quantization bits are provided. 3. A framing device in a digital video signal recording device according to claim 1 or 2. 4. The digital video signal recording apparatus according to claim 1, wherein the high-efficiency coding is DCT, and the parameter is quantization step width information for requantizing the coefficient data. Framing device.