JP3216051B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a structure of a light shielding layer such as a black matrix formed on an active matrix substrate.

[0002]

2. Description of the Related Art In a liquid crystal display device as a typical flat panel display, as shown in FIGS. 28 and 29, data lines (source lines) for supplying image signals are provided.
Are arranged in a grid pattern, and one side transparent substrate in which each pixel region 501aa, 501ab... Is partitioned is formed. The liquid crystal 540 is sealed between the transparent substrate 530 (opposite substrate) on the other side on which the common electrode 533 is formed, and the common electrode 533 and the pixel electrodes 515506 of the respective pixel regions 501aa, 501ab,.
Between the pixel regions 501aa and 501a by controlling a potential applied through a thin film transistor (TFT) 508 between the pixel regions 501aa and 501a.
The alignment state of the liquid crystal is changed for each ab. In such a liquid crystal display device, for example, as shown in FIG.
Leakage of light from the gap (indicated by arrow A) degrades the quality of the display. In addition, a reverse tilt domain region in which the alignment state of the liquid crystal is disturbed due to the effect of the electric field between the data line 502a and the pixel electrode 506 is generated inside the outer edge of the pixel electrode 506, and the display region is distorted due to the region. There is also a problem that the quality deteriorates. For this reason, in order to increase the vividness of the display for each pixel,
The other transparent substrate 530 on which the common electrode 533 is formed
Then, a light-shielding black matrix 531 is formed corresponding to the boundary region between the pixel regions, and the two transparent substrates 509 and 530 are opposed to each other so that the black matrix 531 is located in the boundary region between the pixel regions. The display quality is assured. Here, if there is a displacement between the boundary area between the search areas and the black matrix 531, the display quality is reduced. Therefore, the above-described displacement is provided with a margin in the width of the black matrix 531. It prevents that from happening.

[0003]

However, the liquid crystal display device is required to have a large screen and high display quality, and the width of the black matrix is reduced as in the prior art. If the area is widened so as to have a margin, the aperture ratio (area ratio of a displayable area) in the pixel region is reduced, and there is a problem that improvement in display quality is hindered. Therefore, the inventor of the present application has also formed a black matrix on the side of the transparent substrate on which the matrix array is formed, thereby preventing displacement between the boundary region between the pixel regions and the black matrix, and reducing the width of the black matrix. It is proposed that the width can be set to the minimum necessary width. In accordance with this proposal, the present inventor first devised a liquid crystal display device shown as a comparative example in FIGS. In these figures, the data lines 502a, 502b,.
. And the gate lines 503a, 503b,... Are arranged in a grid pattern to define the respective pixel regions 501aa, 501ab,.
The black matrix 517 is formed along the boundary region of 501ab. Here, the black matrix 517 is formed, for example, in the pixel region 501bb.
The interlayer insulating films 513 and 51 are formed on the surface side of the TFT 508 formed by the source 504 to which the data line 502a is conductively connected, the gate electrode 505 to which the gate line 503a is conductively connected, and the drain 507 to which the pixel electrode 506 is conductively connected.
5, and is insulated from all of the data line 502a, the gate line 503a, and the pixel electrode 506. In the liquid crystal display device having such a configuration, each pixel region and the black matrix 517 can be aligned with high accuracy without providing an unnecessary margin for the width of the black matrix 517, so that the aperture ratio of the liquid crystal display device is reduced. There is no sacrifice. However,
This liquid crystal display device has the following new problem. Since no potential is applied to the black matrix 517 and the black matrix 517 is in a floating state,
The potential of the black matrix 517 fluctuates depending on the operation state of the liquid crystal display device, and the fluctuation of the potential disturbs the alignment state of the liquid crystal present between the pixel electrode 506 and the common electrode of the transparent substrate on the other side. It degrades the quality. In addition, any of the pixel regions 501aa and 501ab
Are also common, so, for example, the black matrix 517 includes the pixel electrode 506 and the data lines 502a and 50b in the search area 501bb.
If short-circuited to the gate line 2b or the gate lines 503a, 503b, etc., the entire liquid crystal display device will have a display failure.

[0004]

SUMMARY OF THE INVENTION In view of the above problems,
In the present invention, by optimizing the structure of the black matrix formed on the same substrate as the matrix array, without sacrificing display quality or reliability, etc.
For the purpose of realizing a liquid crystal display device capable of improving the aperture ratio, the following measures are taken for the liquid crystal display device.

According to the present invention, there is provided a transistor including a data line on a substrate, a gate line intersecting the data line, a source connected to the data line, and a gate electrode connected to the gate line; A liquid crystal display device having a conductive layer connected to a drain of the liquid crystal display and a pixel electrode connected to the conductive layer, wherein the gate electrode is disposed so as to protrude from the gate line, and the conductive layer is
The second insulating film is connected to the drain through a contact hole formed in a first insulating film on the drain, and is connected to the drain through a second contact hole formed in a second insulating film on the conductive layer. The second contact hole is connected to the upper pixel electrode, and the second contact hole is disposed between the gate electrode and the first contact hole.

[0006]

[0007]

[0008]

[0009]

[0010]

[0011]

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

(Embodiment 1) FIG. 1 is a plan view showing a part of a matrix array of a liquid crystal display device according to Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view taken along line II. It is.

In the liquid crystal display device of this embodiment, as shown in FIG. 1, the data lines 102a, 102b,.
(Signal line) and horizontal gate lines 103a, 103
b (scan lines) are arranged in a grid pattern, and the pixel regions 101aa, 101ab, 101ac, 1
., 01ba, 101bb,...

The structure of the pixel region 101bb (first pixel region) will be described below as an example. Here, the pixel regions 101ab, 101ba,
101 cb and 101 bc (second pixel region) are adjacent to each other, and a source 104 to which the data line 102 a is conductively connected, a gate electrode 105 to which the gate line 103 b is conductively connected, and a pixel electrode 106 are connected to the pixel region 101 bb. The drain 107 forms a TFT 108. Here, the pixel electrode 106 is a transparent electrode made of ITO and is formed over substantially the entire surface of the pixel area 101bb.

As shown in FIG. 2, the sectional structure of the TFT 108 is a transparent substrate 109 for supporting the entire liquid crystal display device.
A polycrystalline silicon layer 110 is formed on the surface side of
Except for the channel region 111 which is an intrinsic polycrystalline silicon region, phosphorus as an n-type impurity is introduced into the polycrystalline silicon layer 110 to form a source 104 and a drain 107. Here, the introduction of phosphorus
The source 104 and the drain 107 are self-aligned by utilizing ion implantation using the gate electrode 105 on the gate electrode oxide film 112 formed on the surface side of the polycrystalline silicon layer 110 as a mask. A lower interlayer insulating film 113 made of a silicon oxide film is deposited on the surface of the TFT 108, and a first connection hole 113a and a second connection hole 113b are opened in the lower interlayer insulation film 113. The data line 102a made of a low-resistance metal layer, for example, an aluminum layer or an alloy layer containing aluminum is conductively connected to the source 104 through the first connection hole 113a. On the other hand, the pixel electrode 106 is connected to the drain 107 through the second connection hole 113b.
Is conductively connected to

Further, in this liquid crystal display device, an upper interlayer insulating film 115 is provided on the surface side of the transparent substrate 109.
A chromium layer 116bb (conductive light-shielding layer) having light-shielding properties and conductivity is formed on the surface side. here,
The chrome layer 116bb has a T
Positions diagonal to the formation region of FTl08, that is, pixel region 101bb and pixel regions 101ab, 101ac, 10ac
At the end on the side in contact with 1bc, it is conductively connected to the pixel electrode 106 via the connection hole 115a of the upper interlayer insulating film 115. Further, the outer edge 116x of the chrome layer 116bb has the pixel region 101bb and the pixel region 101a.
b, 101ba, 101cb, and 101bc, that is, the data lines 102a and 102b and the gate lines 103a and 103b. The data lines 102a and 102b and the gate lines 103a and 103b It is in a state of being insulated and separated through the interlayer insulating film 113115. Further, the chrome layer 116
A conductive light-shielding layer such as bb is similarly formed in any pixel region, but is insulated from the chromium layer in the adjacent pixel region. For example, the outer edge 116x of the chrome layer 116bb and the chrome layer 116a
b, 116ba, 116cb, outer edge 11 of 116bc
6x is in a state of being insulated and separated at a position immediately above the data lines 102a and 102b and the gate lines 103a and 103b. Therefore, any chromium layer, for example, the chrome layer 116bb, is formed in the pixel regions 101ab, 101ba, 101ba.
Since each of the pixel electrodes cb and 101 cc is insulated and separated, the same pixel region 10
Even if a potential is applied from the 1bb pixel electrode 106, no potential is applied from the pixel electrodes in other pixel regions. In addition, substantially the entire front surface side of the data line 102a is formed by the interlayer insulating film 115 and the chrome layers 116bb and 116bb.
The potential applied to the data line 102a, which is covered by the end of ba, does not affect the liquid crystal on the surface side. The chrome layer 116bb
Are formed with a large overlapping area on the side of the previous gate line 103a, and the chrome layer 116bb
Since the capacitor is electrically connected to the capacitor 06, it is in a state of forming a storage capacitor.

In this embodiment, the transparent substrate 10 on which the black matrix 116 is formed in addition to the matrix array
9 and a transparent substrate (not shown) on the other side on which a color filter and a common electrode are formed.
A liquid crystal display device is configured. Then, the data line 102
a, 102b... and gate lines 103a, 103b
, The potential generated between the common electrode and each pixel electrode 106 is controlled to change the alignment state of the liquid crystal in each pixel region, thereby displaying information.

Here, in the conventional liquid crystal display device,
On the transparent substrate on which the common electrode is formed, a black matrix corresponding to the boundary region of the pixel region of the transparent substrate 109 is formed. Is the pixel area 10
Each chromium layer 116bb, 116ab,
Since 116ba, 116cb, 116cc... Are used as a black matrix, it is not necessary to form a black matrix on the side of the transparent substrate on which the common electrode is formed. Therefore, when two transparent substrates are opposed to each other as in the related art, the alignment accuracy between the boundary region of each pixel region and the black matrix 116 does not matter, so that the width of the black matrix 116 is The boundary areas, that is, the data lines 102a, 102b,...
In addition, the width can be set to a minimum width corresponding to the width of the gate lines 103a and 103b. Therefore, the aperture ratio of the liquid crystal display device can be improved.

The chrome layer 116bb is connected to the data line 1
02a, 102b, gate lines 103a, 103b, and adjacent pixel regions 101ab, 101ba, 101c
b and 101bc, while being insulated and separated from the pixel electrodes, and electrically connected to the pixel electrode 106 of the same pixel region 101bb, the potential of the chromium layer 116bb is always constant regardless of the operation state of the liquid crystal display device. Pixel electrode 106
In this state, the same potential as that of the above is applied. Therefore, the potential of the chromium layer 116bb does not disturb the alignment state of the liquid crystal existing between the pixel electrode 106 and the common electrode in the pixel region 101bb, so that high display quality can be obtained. Further, the black matrix 116 includes the pixel region 101bb.
Chromium layer 1 electrically independent for each pixel area
16bb, for example, in the pixel region 101bb, the chrome layer 116bb
Even if the data line 102a and the data line 102a are in a short-circuit state, only the pixel region 101bb cannot be displayed, that is, the influence is limited to the occurrence of a point defect in the display, so that the reliability of the liquid crystal display device is high.

(Embodiment 2) FIG. 3 is a plan view showing a part of a matrix array of a liquid crystal display device according to Embodiment 2 of the present invention, and FIG. 4 is a sectional view taken along line II-II.
Here, portions having functions corresponding to those of the liquid crystal display device according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

In the liquid crystal display device according to this embodiment, the vertical data lines 102a, 102b. ...
, And the horizontal gate lines 103a, 103b,.
a, 101ab, 101ac, 101ba, 101bb
, For example, in the pixel region 101bb (first pixel region), the TF
Tl08 is formed, and a lower interlayer insulating film 113 made of a silicon oxide film is deposited on the surface side thereof. The data line 102a is conductively connected to the source 104 via the first connection hole 113a. Further, an upper interlayer insulating film 115 is also formed on the surface side thereof, and these first and upper interlayer insulating films 11 and 11 are formed.
A chrome layer 116bb (conductive light-shielding layer) having light-shielding properties and conductivity is conductively connected to the drain 107 through a connection hole 115a penetrating through 3115. The pixel electrode 1 to which a potential is to be applied via the drain 107
Reference numeral 06 is formed on the surface of the upper interlayer insulating film 115 and is conductively connected to the chromium layer 116bb. Here, the chrome layer 116bb has the outer edge 11 as in the first embodiment.
6x is a pixel region 101bb and its adjacent pixel regions 101ab, 101ba 101cb, 101cb (second
Pixel region), that is, the data line 102
a, 102b and the gate lines 103a, 103b are formed immediately above the formation regions. These data lines 102a, 102b and the gate lines 103a, 103a,
103b is in a state of being insulated and separated by an interlayer insulating film 113115. Further, a conductive light-shielding layer such as the chrome layer 116bb is provided on any pixel region.
Are formed as 6ab, 116ba,..., But each chromium layer is insulated and separated from the chromium layer in the adjacent pixel region. For example, the chrome layer 116bb
Are the pixel regions 101ab, 101ba, 101bc, 1
01cb is insulated from each pixel electrode 106. Therefore, a potential is applied to the chrome layer 116bb only through the pixel electrode 106 in the same pixel region 101bb. Then, the surface side of the data line 102a is provided with the interlayer insulating film 115 and the chromium layers 116bb, 11bb.
6ba, the potential applied to the data line 102a does not affect the liquid crystal on the surface side.

In the liquid crystal display device having such a configuration, as in the liquid crystal display device according to the first embodiment, the transparent substrate 1
Since the black matrix 116 is formed on the side of the pixel array 09 in addition to the matrix array and corresponding to the boundary region of each pixel region, the width of the black matrix 116 can be set to the minimum necessary width. The aperture ratio of the liquid crystal display device is high. Further, since the chrome layer 116bb is conductively connected only to the pixel electrode 106 in the same pixel region 101bb, the same potential as the potential of the pixel electrode 106 is applied to the chrome layer 116bb regardless of the operation state of the liquid crystal display device. In this state, the potential of the chrome layer 116bb does not disturb the alignment state of the liquid crystal existing between the pixel electrode 106 and the common electrode. Further, since each chromium layer is electrically independent for each pixel region, even if the chromium layer is short-circuited with a data line or the like in one pixel region 101bb, a point defect of display occurs due to the influence. Therefore, the reliability of the liquid crystal display device remains high.

(Embodiment 3) FIG. 5 is a plan view showing a part of a matrix array of a liquid crystal display device according to Embodiment 3 of the present invention, and FIG. 6 is a sectional view taken along line III-III. Here, portions having functions corresponding to those of the liquid crystal display device according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

Also in the liquid crystal display device according to this embodiment, for example, the pixel area 101bb (first pixel area)
In the same manner as in the first embodiment, the TFT 108 formed on the front side of the transparent substrate 109 is
Is conductively connected to the source 104 via the connection hole 113a of the lower interlayer insulating film 113, while the pixel electrode 106 is conductively connected to the drain 107 via the upper interlayer insulating film 113b. The chromium layer 116 formed on the surface side of the upper interlayer insulating film 115 is provided on the pixel electrode 106.
bb is conductively connected via the connection hole 115a.

In the present embodiment, the outer edge 116x of the chrome layer 116bb has the data line 102a and the gate line 1
03a, the adjacent pixel areas 101ba, 101b
It extends to the inside of cb. On the other hand, the pixel region 10
The chrome layer 116bb is not formed on the side of the boundary region between 1bb and the pixel regions 101bc and 101ab, and the chrome layer 116bb has an L-shape on the adjacent boundary region. Then, the pixel region 101bb is located on the side of the boundary region between the pixel region 101bb and the pixel region 101bc.
The end of the chrome layer 116bc formed on the bc extends beyond the data line 102b to the inside of the pixel region 101bb. In addition, a pixel region 101a is located on the boundary region side of the pixel region 101bb with the pixel region 101ab.
The end of the chrome layer 116ab formed on the gate line 1b
The area extends beyond the pixel area 03b to the inside of the pixel area 101bb. As a result, the pixel region 101bb is defined by the chrome layer 116bb formed corresponding to itself and the chrome layers 116bc and 116ab formed corresponding to the adjacent pixel regions 101bc and 101ab. .

In this embodiment, these chromium layers 116
bb, 116bc, 116ab,...
1bb... Are partitioned to form a chrome layer 116bb.
Used as 16.

For this reason, in the liquid crystal display device of this embodiment, as in the first embodiment, the aperture ratio of the liquid crystal display device is increased, and since the black matrix 116 is not in a floating state, the potential of the liquid crystal display device is lower than that of the liquid crystal display device. Does not cause disturbance. Further, the black matrix 116 includes chrome layers 116bb, 116b electrically independent for each pixel region.
., 116ab..., the effect of a short circuit in one pixel region of the chrome layers 116bb, 116bc, 116ab.

Further, in this embodiment, unlike the liquid crystal display devices of Embodiments 1 and 2, the chrome layer 116b
, b, 116bc, 116ab... and the data lines 102a, 102b.
103b... Are not arranged close to each other over a wide range. For this reason, in the process of forming the black matrix 116, the chrome layer 11 is formed with normal accuracy.
6bb, 116bc, 116ab...
They do not short circuit each other. Further, pixel area 1
06 are formed on the surface of the interlayer insulating film 113, and the chromium layers 116bb, 116bc, 116ab... Are formed on the surface of the interlayer insulating film 115. That is, the chrome layer 116bb of the pixel area 106 and the adjacent pixel area,
Since 116bc, 116ab,... Are formed on different layers, there is no short circuit even if they are arranged close to each other. Therefore, it is possible to easily form the black matrix 116 including the chrome layers 116bb, 116bc, 116ab... Which are electrically independent for each pixel region.

In the third embodiment, the chromium layers 116bb, 116bc as conductive light-shielding layers are provided on the two adjacent boundary areas of the boundary area between the adjacent pixel areas.
116ab ..., this chrome layer and the other two
The pixel region is separated from the adjacent pixel regions by the chromium layer of the pixel region adjacent on one boundary region side. As a modification of the third embodiment, as shown in FIG. 116, chrome layers 118ab and 118bc as conductive light-shielding layers are provided on two opposing boundary areas of a boundary area between adjacent pixel areas.
.. May be formed by changing the direction belonging to each of the adjacent pixel regions. In this case, each chrome layer 118ab, 118bc, 119
ab, 119bc... are pixel regions 101aa, 101ab, 101ac in the directions indicated by “→” in the figure, respectively.
.. Are electrically connected to the pixel electrodes.

Here, the shape, structure, material, and the like of each element constituting the liquid crystal display device have properties that should be set under predetermined conditions depending on the size, application, and the like of the liquid crystal display device to be manufactured. There is no limitation.

In each of the embodiments, the chromium layer was used as the conductive light-shielding layer constituting the black matrix. However, the material is not limited. Alternatively, a metal layer such as aluminum or aluminum, a silicon layer, or a silicide compound such as molybdenum silicide or tungsten silicide can be used.

(Embodiment 4) FIG. 8 is a schematic plan view showing a part of an active matrix substrate used for a liquid crystal display device according to Embodiment 4 of the present invention, and FIG. 9 is a sectional view taken along line IV-IV. It is.

In the liquid crystal display device of this embodiment, Embodiment 1
In the same manner as the liquid crystal display device according to
(Signal lines) and horizontal gate lines 203a, 203b (scanning lines) are arranged in a grid pattern, and pixel regions 201aa, 201a are interposed therebetween.
are formed, and the structure of the pixel region 201bb (first pixel region) will be described below. Here, the counter substrate 230 shown in FIG.
Are provided with a color filter 232 for enabling color display, a common electrode 233, and a counter substrate side alignment film 234.
Are formed. In addition, a counter substrate-side black matrix 231 is formed on the side of the counter substrate 230. In the liquid crystal display device of this example, as described later,
A black matrix is also formed on the side of the active matrix substrate, and the black matrix 23 on the opposite substrate side is formed.
1 is provided for the purpose of complementing the black matrix on the active matrix substrate side.

As shown in FIG. 8, the pixel region 201bb
(First pixel region) includes pixel regions 201ab and 201b.
a, 201cb, 201bc (second pixel area) are adjacent to each other, and in the pixel area 201bb, the data line 2
02a is conductively connected to the source 204 and the gate line 203b
Gate electrode 205 and pixel electrode 206 which are conductively connected
Are conductively connected to each other to form a TFT 208
Is configured. Here, the pixel electrode 206 is a transparent electrode made of ITO as a conductive and light-transmissive material, is formed over substantially the entire surface of the pixel region 201bb, and ends thereof are connected to the data lines 202a, 202b and the gate. It is extended to a position immediately above the lines 203a and 203b. Each of the pixel electrodes 206 has a wide overlapping area on the side of the gate line 203a in the preceding stage.

The sectional structure of the TFT 208 is, as shown in FIG. 9, a transparent substrate 209 supporting the entire liquid crystal display device.
A polycrystalline silicon layer 210 is formed on the surface side of
Except for the channel region 211 which is an intrinsic polycrystalline silicon region, phosphorus as an n-type impurity is introduced into the polycrystalline silicon layer 210 to form a source 204 and a drain 207. On the surface side of the TFT 208, a lower interlayer insulating film 213 made of a silicon oxide film is provided.
A first connection hole 213a is opened therein, and a data line 202a made of an aluminum layer is conductively connected to the source 204 via the first connection hole 213a.

Further, in the liquid crystal display device of this embodiment,
An upper interlayer insulating film 215 is formed on the surface side of the lower interlayer insulating film 213, and the upper interlayer insulating film 215 is formed.
And a second connection hole 215 in the lower interlayer insulating film 213.
a is open. Then, the pixel electrode 206 is conductively connected to the drain 207 via the second connection hole 215a. Here, the pixel electrode 206 is provided in the pixel region 201bb.
And pixel regions 201ab, 201ba,
01bc and 201cb, the outer edge 206x is formed so as to be located immediately above the data lines 202a and 202b and the gate lines 203a and 203b.

In the liquid crystal display device of this embodiment, the pixel electrode 206 is located on the surface side of the upper interlayer insulating film 215.
On the lower layer side, a molybdenum silicide layer 216bb (conductive light-shielding layer) having a light-shielding property and a conductive property is formed.
b, 201ba, 201cb, and 201bc, the outer edges 216x of the data lines 202a,
02b and the gate lines 203a and 203b, and are aligned with the outer edge 206x of the pixel electrode 206. Here, a conductive light-shielding layer such as the molybdenum silicide layer 216bb is similarly formed in any of the pixel regions.
The molybdenum silicide layer 216bb is connected to the data line 202 at both outer edges 216x of the a, 216cb and 216bc.
a, 202b and gate lines 203a, 203b are insulated and separated from each other. Therefore, even when a potential is applied to the molybdenum silicide layer 216bb from the pixel electrode 206 in the same pixel region 201bb,
In this state, no potential is applied from the pixel electrodes in other pixel regions. In addition, substantially the entire front surface side of the data line 202a is covered with an interlayer insulating film 215, a molybdenum silicide layer 216bb,
Since it is covered by the end of the pixel electrode 206 and the end of the pixel electrode 206, the potential applied to the data line 202a does not affect the liquid crystal on the surface side.

With such a configuration, the transparent substrate 209
The active matrix formed on the surface side of the counter substrate 2 has the alignment side 220 formed on the surface side of the pixel electrode 206 and the molybdenum silicide layer 216bb.
Liquid crystal is filled between the gaps 30 and 30, so that display utilizing the orientation of the liquid crystal is enabled.

In the liquid crystal display device having such a configuration, each of the molybdenum silicide layers 216bb, 216a
are used as the black matrix 216, the black matrix is not required on the side of the counter substrate 230 if the data line and the gate line have a light shielding property, or the data line or the gate line If has no light-shielding property, it is only necessary to form it complementarily, as in the counter substrate-side black matrix 231 shown in FIG. 9, in consideration of the positioning accuracy when two transparent substrates face each other. The width of the black matrix 216 or the counter substrate side black matrix 231 does not need to be unnecessarily increased. Here, each molybdenum silicide layer 21
6bb, 216ab... Correspond to the pixel regions 201bb, 20
1ab}., Since it is formed on the surface side of the same transparent substrate 209, the positional accuracy is high and the data line 20
2a, 202b... And gate lines 203a, 203
Since the width can be set to the minimum width corresponding to the width such as b, the aperture ratio of the liquid crystal display device can be increased. In addition, since the potential of the molybdenum silicide layer 216bb is always in the state where the same potential as that of the pixel electrode 206 is applied, the potential of the molybdenum silicide layer 216bb does not disturb the alignment state of the liquid crystal, so that high display quality can be obtained. .

Furthermore, even if both the pixel electrode 206 and the black matrix 216 function as electrodes, the outer peripheral area of the pixel electrode 206 and the outer peripheral area of the black matrix 216 can be made to coincide with each other. A region where the alignment of the liquid crystal is disturbed (reverse tilt domain region) due to the potential wraparound can be reliably covered with the black matrix 216. Further, since the black matrix 216 is composed of the molybdenum silicide layers 216bb... Electrically independent for each pixel region, the black matrix 216 includes, for example, the pixel region 201.
In bb, even if the molybdenum silicide layer 216bb and the data line 202a are in a short-circuit state, only the point defect of the pixel region 201bb is obtained, so that the reliability of the liquid crystal display device is high.

Further, as the pixel area 201bb is miniaturized as the definition of the liquid crystal display device becomes higher, the display capacity in the pixel area 201bb decreases, and the TFT 208 having a high off-resistance is formed to reduce the leak current. Even so, there is a tendency that the display voltage is reduced during the non-selection period of the gate line 203b, and the display holding characteristics are likely to be lowered. However, in the liquid crystal display device of this example, the pixel electrode 2
06 is located above the previous gate line 203a,
A charge storage capacitor is formed between them. For this reason,
During the selection period of the pixel region 201bb, the previous gate line 2
03a is a non-selection period, by utilizing the fact that a reference potential is applied to the gate line 203a, charges are stored in the charge storage capacitor, and the retention characteristics of the liquid crystal applied voltage in the pixel region 201bb can be improved. .

Next, a part of the method of manufacturing the liquid crystal display device of the present embodiment will be described with reference to the left side region of the regions shown in FIGS. 10A to 10C are process cross-sectional views illustrating a part of the method of manufacturing the liquid crystal display device of the present example.

Here, as shown in FIG. 10A, the steps up to the formation of the TFT 208 on the transparent substrate 209 can be performed by a well-known method. After the formation, first, the lower interlayer insulating film 213 is formed. Next, a first connection hole 213a is formed, a data line 202a made of an aluminum layer is formed therein, and the data line 202a is connected to a TFT.
A conductive connection is made to a source 204 at 208. Next, after forming the upper interlayer insulating film 215 on the surface side of the lower interlayer insulating film 213, a second connection hole 215a is formed in the upper interlayer insulating film 215.

Next, after the molybdenum silicide layer is deposited, as shown in FIG. 10B, it is patterned to form a molybdenum silicide layer 216a.
In this state, the molybdenum silicide layer 216a
Are not in the state of being patterned to the pattern constituting the black matrix 216.

Next, the molybdenum silicide layer 216a
After the ITO layer 206a is formed on the surface side of
The pixel electrode 206 is formed by patterning the TO layer 206a as shown in FIG. Thereafter, the molybdenum silicide layer 216bb which should form the black matrix 216 is formed by using the mask used when the pixel electrode 206 is formed by patterning or by patterning the molybdenum silicide layer 216a using the pixel electrode 206 itself as a mask. Form. As described above, in the patterning step for the lower layer side of the pixel electrode 206 and the molybdenum silicide layer 216bb,
Patterning is performed using the mask used for patterning the outer edge of the layer on the upper layer side or the layer on the upper layer side as a mask.

As a result, the outer edge 206 of the pixel electrode 206
x and the outer edge 216x of the molybdenum silicide layer 216bb
, And all have a structure immediately above the data line 202a. In addition, since well-known processes can be adopted for the subsequent processes, the description thereof is omitted.

As described above, according to the method of manufacturing the liquid crystal display device according to this embodiment, when the pixel electrode 206 is formed by patterning, the molybdenum silicide layer 216a is provided below the pixel electrode 206, and the lower layer is protected. For this reason,
When a chlorine-based etchant is used for patterning the ITO layer 206a, even if there are pits or the like in the upper interlayer insulating film 215, the data line 202a formed of the lower aluminum layer is affected by the etchant. Nothing. For this reason, disconnection or the like does not occur in the data line 202a, so that the reliability of the liquid crystal display device is improved.

Note that, among the regions shown in FIGS. 10A to 10C, the process cross-sectional views shown in the right region are modifications of the above-described manufacturing method.

That is, as shown in FIG. 10B, the molybdenum silicide layer 216a is left inside the second connection hole 215a. Therefore, FIG.
As shown in (c), after the pixel electrode 206 is formed, the pixel electrode 206 made of the ITO layer is conductively connected to the drain region 207 made of silicon via the molybdenum silicide layer 216bb. As compared with a case where the drain region 107 is directly connected to the drain region 206, the contact resistance there can be reduced.
The display quality can be improved.

It should be noted that the active matrix substrate formed by the manufacturing method shown on either side of the left side region and the right side region in FIGS. However, the present invention is not limited to this.
It is also possible to adopt a structure in which the upper limit relation is reversed.

(Embodiment 5) FIG. 11 shows Embodiment 5 of the present invention.
FIG. 12 is a schematic plan view showing a part of the active matrix substrate used in the liquid crystal display device according to the first embodiment, and FIG. Here, parts having functions corresponding to those of the liquid crystal display device according to the fourth embodiment shown in FIGS. 8 and 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the liquid crystal display device of this embodiment, the pixel area 201bb (first pixel area) is also provided in the pixel area 201a.
b, 201ba, 201cb, and 201bc (second pixel regions) are adjacent to each other. Here, the source 204, the gate electrode 205, and the drain 2
07 constitutes a TFT 208.
On the front side of the FT 208, a lower interlayer insulating film 213 made of a silicon oxide film is deposited. A first connection hole 213 a and a second connection hole 213 b are opened in the lower interlayer insulating film 213, and the first connection hole 21
3a, a data line 202 made of an aluminum layer
a is conductively connected to the source 204, and the second connection hole 213b
, A pixel electrode 206 made of an ITO layer is conductively connected to the drain 207.

Here, the pixel electrode 206 is connected to the pixel region 20.
1bb and the pixel regions 201ab and 201 adjacent thereto.
ba, 201bc, and 201cb, and the outer edge 206x is formed on the data line 202.
a, 202b and the gate lines 203a, 203b. Also, in the liquid crystal display device of this example, the molybdenum silicide layer 216bb (conductive light-shielding layer) having light-shielding properties and conductivity is provided on the surface side of the pixel electrode 206, and the molybdenum silicide layer 216bb is provided.
Also, the pixel region 201bb and the pixel region 2 adjacent thereto
01ab, 201ba, 201bc, and 201cb.
Are the data lines 202a and 202b and the gate line 203
a, 203b, inside the pixel electrode 2
06 and the outer edge 206x. Here, as for the width of the molybdenum silicide layer 216bb, it is preferable to increase the width of the pixel region 201bb on the side where the alignment of the liquid crystal is likely to be disordered, and to narrow the width on the side where the disorder is unlikely to occur. Therefore, in the liquid crystal display device of the present embodiment, the molybdenum silicide layer 216bb on the data line 202a side is shielded for the purpose of shielding the reverse tilt domain region where the alignment of the liquid crystal is disturbed by the influence of the charge of the data line 202a on the data line 202a side. The width W1 is set to be larger than the width W2 on the side of the data line 202b, and even if an alignment error occurs, the display quality is maintained high by reliably covering the reverse tilt domain region. , The reduction of the aperture ratio is minimized.

Also in the liquid crystal display device having such a configuration, since each molybdenum silicide layer 216bb... Is used as a black matrix, the active matrix substrate side formed on the transparent substrate 209 side and the opposing substrate 230 When the molybdenum silicide layer 216bb faces the counter substrate side black matrix 2
31 is a margin in the alignment, and the alignment accuracy does not matter. Further, since the potential of the molybdenum silicide layer 216bb is in a state where the same potential as that of the pixel electrode 206 is applied, the orientation state of the liquid crystal is not disturbed, so that high display quality can be obtained. Further, since the black matrix 216 is composed of molybdenum silicide layers 216bb... Electrically independent for each pixel, the molybdenum silicide layer 216bb and the data lines 202a are in a short-circuit state in the pixel region 201bb. However, since the display is limited to the point defect of only the pixel region 201bb, the reliability of the liquid crystal display device is high.

Next, a part of the method of manufacturing the liquid crystal display device of the present embodiment will be described with reference to the left side region of the regions shown in FIGS. 13 (a) to 13 (d). 13A to 13D are process cross-sectional views illustrating a part of the method for manufacturing the liquid crystal display device of the present example.

Here, as shown in FIG. 13A, the steps up to the formation of the TFT 208 on the transparent substrate 209 can be performed by a well-known method. After forming, first,
After the lower interlayer insulating film 213 is deposited, a first connection hole 213a and a second connection hole 213b are formed in the lower interlayer insulating film 213. Next, an ITO layer 206a on which the pixel electrode 206 is to be formed is formed by sputtering.

Next, as shown in FIG. 13B, after the molybdenum silicide layer 216a is deposited, only the molybdenum silicide layer 216a is patterned. In this state, the molybdenum silicide layer 216a still has
While the pattern constituting the black matrix 216 has not been patterned yet, the ITO layer 20
6a is also a state in which the pattern constituting the pixel electrode 206 is not patterned.

Next, as shown in FIG.
Prior to patterning the O layer 206a, the edge of the molybdenum silicide layer 216a is patterned to form a molybdenum silicide layer 2 forming a black matrix.
After forming 16 bb, the ITO layer 206 a is patterned using the same mask as it is to form a pixel electrode 206.
To form Here, for the purpose of ensuring high etching accuracy, the molybdenum silicide layer 216a is
While performing plasma etching with _four gases, ITO
For the layer 206a, the molybdenum silicide layer 216
Subsequent to the plasma etching for a, anisotropic dry etching is performed using a mixed gas of CH ₄ gas and H ₂ gas. As a result, the outer edges 206x and 216x of the pixel electrode 206 and the molybdenum silicide layer 216bb are
In each case, the pixel region 201bb and its adjacent pixel regions 201ab, 201ba, 201bc, 201cb
A structure is obtained in the vicinity of the boundary region with. The plasma etching using the CF ₄ gas can be performed in the same manner by employing a molybdenum silicide layer or a tungsten silicide layer instead of the molybdenum silicide layer 216a.

Next, after forming an aluminum layer for forming the data lines 202a and 202b, FIG.
As shown in FIG.
a is formed.

As for the subsequent steps, well-known steps can be employed, and thus the description thereof is omitted.

As described above, according to the method of manufacturing the liquid crystal display device of the present embodiment, even if both the pixel electrode 206 and the black matrix 216 function as electrodes, the outer peripheral area of the pixel electrode 206 and the outer Since the ranges can be matched with each other, the black matrix 216 can reliably cover the disorder of the alignment of the potentials from these electrodes on the liquid crystal.

The process cross-sectional views shown on the right side of the regions shown in FIGS. 13A to 13D are modifications of the above-described manufacturing method.

That is, as shown in FIG. 13B, in the regions a-1 and a-2 after the formation of the lower interlayer insulating film 213, the ITO layer 206a is formed on the surface side of the lower interlayer insulating film 213. After the formation of the first connection hole 21
3a and a second pier hole 213b are formed.

Next, as shown in FIG. 13B, a molybdenum silicide layer 216a is formed. As a result, T
The molybdenum silicide layer 216a is conductively connected to the source 204 and the drain 207 of the FT 208.

Next, as shown in FIG. 13C, the molybdenum silicide layer 216a is patterned to form a molybdenum silicide layer 216bb constituting the black matrix 216, and the regions c-1 and c-2 are formed.
, The molybdenum silicide layers 216b and 216c are left inside the first connection holes 213a and 213b. Thereafter, the pixel layer 206 is formed by patterning the ITO layer 206a using the end of the molybdenum silicide layer 216bb as a mask. As a result, the pixel electrode 20
6 and outer edge 20 of molybdenum silicide layer 16bb
Each of 6x and 216x is a pixel area 201bb and pixel areas 201ab, 201ba, 201ba adjacent thereto.
The structure is the same in the vicinity of the boundary region between bc and 201cb.

Thereafter, as shown in FIG.
The data line 202a is formed on the surface side of the molybdenum silicide layer 216b in the region d-1, and the data line 202a is conductively connected to the source 204 via the molybdenum silicide layer 216bb.

As for the subsequent steps, well-known steps can be adopted, and thus the description thereof is omitted.

According to such a manufacturing method, the data line 202a, which is an aluminum layer, is connected to the source 204 made of silicon via the molybdenum silicide layer 206b, so that silicon is added by eutectic reaction with aluminum. Since the TFT 208 can be formed from a thin silicon thin film, its ON / OFF
The ratio can be improved.

Further, in a region d-2 in FIG. 13D, the pixel electrode 206 made of the ITO layer and the drain 207 made of silicon are connected to the molybdenum silicide layer 2.
06a, the pixel electrode 206 is electrically connected.
The contact resistance can be reduced as compared with the case where the drain and the drain 207 are directly connected, and the display quality can be improved.

It should be noted that, in the manufacturing method shown on either side of the left region and the right region in FIGS.
The case where the pixel region 206 is on the lower layer side of the black matrix 216 has been described.

(Embodiment 6) FIG. 14 shows Embodiment 4 of the present invention.
15 is a schematic plan view showing a part of the active matrix substrate used in the liquid crystal display device according to the first embodiment, and FIG. 15 is a sectional view taken along line VI-VI of FIG.

The liquid crystal display device of this embodiment has the same basic structure as the liquid crystal display device of the fourth embodiment. Since only the types are different, corresponding parts are denoted by the same reference numerals and detailed description thereof will be omitted.

In these figures, the liquid crystal display device of this example also has a pixel region 2 similar to the liquid crystal display device of the fourth embodiment.
01bb has a molybdenum silicide layer 216bb (conductive light-shielding layer) having light-shielding properties and conductivity on the surface side of the pixel electrode 206.
6bb is a pixel area 201bb and pixel areas 201ab, 201ba, 201bc, 201cbb adjacent thereto.
And the outer edge 216x of the data line 202a, 202b and the gate line 203a, 203
Immediately above b, it coincides with the outer edge 206x of the pixel electrode 206.

A counter substrate 230 is arranged so as to face the active matrix substrate having such a configuration, and a liquid crystal 241 is filled between these substrates. Here, in the liquid crystal display device of this example, since the polymer dispersed liquid crystal is filled, no alignment film is formed on the surface side of the active matrix substrate and the counter substrate 230. Other configurations are the same as those of the liquid crystal display device according to the fourth embodiment.

In the liquid crystal display device of this embodiment, Embodiment 4
Although the type of liquid crystal is different from the liquid crystal display device according to the above, each molybdenum silicide layer 216bb, 216ab, 216
Since ba... are used as the black matrix 216, a black matrix is not required on the side of the counter substrate 230, or as shown in FIG. Therefore, the positioning accuracy when the transparent substrates of the two sticks face each other does not matter. Therefore, it is not necessary to provide a margin unnecessarily in the widths of the black matrix 216 and the counter substrate side black matrix 231, so that the aperture ratio of the liquid crystal display device can be increased. Effect.

(Embodiment 7) FIG. 16 shows Embodiment 7 of the present invention.
FIG. 17 is a schematic plan view showing a part of the active matrix substrate used in the liquid crystal display device according to the third embodiment.
It is sectional drawing in the I line.

In the liquid crystal display device of this embodiment, the vertical data lines 302a, 302b... (Signal lines) and the horizontal gate lines 303a, 303b.
The source 311 to which the data line 302a is conductively connected as in the pixel region 301bb (first pixel region) in any of the pixel regions defined by
a, the gate electrode 30 to which the gate line 303b is conductively connected
5, and the drain 31 to which the pixel electrode 306 is conductively connected
1b constitutes a TFT 308. Here, the TFT 308 is functionally similar to the TFT of the liquid crystal display device of the first embodiment, but is configured as a so-called inverted staggered TFT in the liquid crystal display device of the present embodiment. That is, an insulating film is formed on the surface side of the transparent substrate 309 that supports the entire liquid crystal display device, and the gate electrode 305 is formed on the surface. Further, on their surface side, a gate electrode insulating film 305a, a non-doped amorphous silicon layer 310, and an amorphous silicon layer (sources 311a, 31
1b) is formed, and a source electrode 304a is formed on the amorphous silicon layer (sources 311a and 311b).
And a drain electrode 307a. Among them, the interlayer insulating film 31 is formed on the drain electrode 307a.
3, the pixel electrode 306 is conductively connected.

Further, in the liquid crystal display device of this embodiment,
On the surface side of the interlayer insulating film 313, a molybdenum silicide layer 316bb (conductive light-shielding layer) having light-shielding properties and conductivity is provided below the pixel electrode 306.
And pixel regions 301ab, 301ba,
The outer edge 306x is formed so as to be located immediately above the data lines 302a and 302b and the gate lines 303a and 303b in the boundary region between the first and second lines 301bc and 301cb. Here, the molybdenum silicide layer 316b
The conductive light-shielding layer b is similarly formed in any of the pixel regions, but is insulated from the search electrode and the molybdenum silicide layer of the adjacent pixel region. Other configurations are the same as those of the liquid crystal display device according to the fourth embodiment.

In the liquid crystal display device having such a configuration, although there is a structural difference due to the difference in the structure of the TFT 308 from the liquid crystal display device according to the fourth embodiment, the display principle is the same. The same effects as those of the liquid crystal display device according to the fourth embodiment can be obtained. For example, each pixel area 301b
molybdenum silicide layer 316bb formed
Are used as the black matrix 316, so that the black matrix is not required on the side of the counter substrate 330, or the data lines 302a, 30
It is only necessary to form a complementary member that blocks only light passing through 3a, and the width of the black matrix 316 or the active matrix 331 on the counter substrate side in consideration of the positioning accuracy when the transparent substrates of the two sticks face each other. Need not be unnecessarily wide. Moreover, since the molybdenum silicide layers 316bb are formed on the surface side of the same transparent substrate 309 as the pixel regions 301bb,..., The positional accuracy is high, and the data lines 302a, 302b.
.. and the width of the gate lines 303a and 303b can be set to the minimum width, so that the aperture ratio of the liquid crystal display device can be increased. Further, since the potential of the molybdenum silicide layer 316bb does not disturb the alignment state of the liquid crystal, high display quality can be obtained. In addition, since the outer peripheral area of the pixel electrode 306 and the outer peripheral area of the black matrix 316 can be matched with each other, the black matrix 316 can surely cover the disturbance of the alignment of the potential from these electrodes on the liquid crystal. It works.

(Eighth Embodiment) FIG. 18 shows an eighth embodiment of the present invention.
FIG. 19 is a schematic plan view showing a part of the active matrix substrate used in the liquid crystal display device according to the third embodiment.
It is sectional drawing in the III line. Here, parts having functions corresponding to those of the liquid crystal display device according to the fourth embodiment shown in FIGS. 8 and 9 are denoted by the same reference numerals.

Also in the liquid crystal display device of this embodiment, as shown in FIG. 18, a source 204 to which the data line 202a is conductively connected and a gate to which the gate line 203b is conductively connected are provided in the pixel region 201bb (first pixel region). A TFT 208 is constituted by the electrode 205 and the drain 207 to which the pixel electrode 206 is conductively connected. Here, the pixel electrode 206 is made of ITO as a conductive and light transmissive material.
And is formed over substantially the entire surface of the pixel region 201bb.
2a, 202b and the gate lines 203a, 203b. Each of the pixel electrodes 206 has a wide overlapping area on the side of the gate line 203a in the preceding stage.

As shown in FIG. 19, the sectional structure of the pixel region 201bb is such that the polycrystalline silicon layer 210 formed on the surface side of the transparent substrate 209 supporting the entire liquid crystal display device.
In addition, except for the channel region 211, phosphorus as an n-type impurity is introduced, so that the source 204 and the drain 20
7 are formed. On the surface side of this TFT 208,
A lower interlayer insulating film 213 made of a silicon oxide film is deposited, and has a first connection hole 213a and a second connection hole 213b. The data line 202a made of an aluminum layer is conductively connected to the source 204 via the first connection hole 213a.

On the other hand, through the second connection hole 213b,
A stacked electrode layer 214 made of ITO, which is a conductive and light-transmissive material like the pixel electrode 206, is conductively connected to the drain 207. Here, the surface of the lower interlayer insulating film 213 reflects irregularities corresponding to the shape of the TFT 208, but the stacked electrode layer 214
08 is not formed on the flat region 208a (TFT
208 (on the non-formation area). Therefore, the stacked electrode layer 21 on this region 208a
The surface of No. 4 is flat.

Further, in this liquid crystal display device, an upper interlayer insulating film 215 made of a silicon oxide film is formed on the surface side of the transparent substrate 209, and the pixel electrode 206 is formed on the surface side. Here, the pixel electrode 20
6 is conductively connected to the stacked electrode layer 214 via a connection hole 215a of the upper interlayer insulating film 215, and the connection hole 215a is formed on a flat region 208a where the TFT 208 is not formed. Therefore, the pixel electrode 206 is conductively connected to the flat region of the stacked electrode layer 214. Note that a polyimide layer or the like may be used as the upper-layer interlayer insulating film 215 to planarize the surface thereof to further improve the orientation of the liquid crystal.

In this embodiment, liquid crystal is sealed between a transparent substrate 209 on which a matrix array is formed and a transparent substrate (not shown) on the other side on which a color filter and a common electrode are formed. The device is configured. .. And the gate lines 203a, 203b,... Control the potential generated between the common electrode and each pixel electrode 206 to control the liquid crystal in each pixel region. Is changed to display information. Here, the pixel electrode 20
6, a potential is applied through the drain 207 of the TFT 208 and the stacked electrode layer 215.

In the liquid crystal display device of this embodiment, the pixel electrode 206 is located on the surface side of the upper interlayer insulating film 215.
On the lower layer side, a molybdenum silicide layer 216bb (conductive light-shielding layer) having a light-shielding property and a conductive property is formed.
b, 201ba, 201bc, and 201cb, the outer edges 216x of the data lines 202a,
02b and the gate lines 203a and 203b, and are aligned with the outer edge 206x of the pixel electrode 206. Here, a conductive light-shielding layer such as the molybdenum silicide layer 216bb is similarly formed in any of the pixel regions.
a, 216bc and the outer edge 216x of the 216cb, the molybdenum silicide layer 216bb
a, 202b and gate lines 203a, 203b are insulated and separated from each other.

Since the molybdenum silicide layers 216bb... Are used as a black matrix in the liquid crystal display device of this embodiment having such a structure, as shown in FIG. When the matrix substrate side and the counter substrate 230 side are opposed to each other, the molybdenum silicide layer 216bb serves as a margin in the positioning of the counter substrate side black matrix 231 and the positioning accuracy does not matter. Further, since the potential of the molybdenum silicide layer 216bb is in a state where the same potential as that of the pixel electrode 206 is applied, the orientation state of the liquid crystal is not disturbed, so that high display quality can be obtained. In addition, the black matrix 216 includes a molybdenum silicide layer 216 that is electrically independent for each pixel.
bb..., the pixel region 20
In 1bb, even if the molybdenum silicide layer 216bb and the data line 202a are in a short-circuited state, only a point defect in display of the pixel region 201bb alone is obtained, so that the reliability of the liquid crystal display device is high.

In the liquid crystal display device of this embodiment, the data line 202a is formed on the lower interlayer insulating film 213 and is conductively connected to the source 204 of the thin film transistor 208 via the first connection hole 213a. On the other hand, the pixel electrode 206 is formed on the upper interlayer insulating film 215 in a state of being stacked on the stacked electrode layer 214 as a pad. That is, since the data line 202a and the pixel electrode 206 are formed on different layers,
There is no danger of short circuit. Therefore, since the end portion 206x of the pixel electrode 206 can be arranged up to a position above the data line 202a, the vicinity of the data line 202a can also be used as a display unit. Therefore, the aperture ratio of the pixel region 201bb is high.

Further, the pixel electrode 206 is connected to the data line 202.
a, the data line 20
The potential of 2a does not disturb the alignment of the liquid crystal. Therefore, display quality is improved. Further, the stacked electrode layer 214
Has a conductive property, so that there is no problem in forming a matrix array. Unlike the case where a metal layer is used as a stacked electrode layer, the stacked electrode layer 214 made of ITO has light transmittance. The pixel area 206
Even if the stacked electrode layer 214 is formed so as to be easily conductively connected, the aperture ratio of the pixel region 201bb is not sacrificed. In addition, since the pixel electrodes 206 are stacked via the stacked electrode layers 214, the connection holes 2 of the lower and upper interlayer insulating films 213 and 215 are formed.
13b and 215a have a structure with a low aspect ratio, so that the reliability of the conductive connection portion inside the connection holes 213b and 215a is high.

In this embodiment, the stacked electrode layers 2
14, the connection resistance between the stacked electrode layer 214 and the pixel electrode 206 is low because ITO is used similarly to the pixel electrode 206. Therefore, the resistance between the drain 207 and the pixel electrode 206 can be maintained at a low level. Further, the surface side of the stacked electrode layer 214 and the upper interlayer insulating film 215 has irregularities reflecting the shape of the TFT 208, but the connection holes 215a of the upper interlayer insulating film 215
Since the FT 208 is formed on the flat region 208a where it is not formed, the reliability of the contact between the stacked electrode layer 214 and the pixel electrode 206 is high, and the contact resistance is low. In addition, such a connection structure also has an effect of raising the level of a flat portion, flattening the surface of the pixel electrode 206, and improving the alignment state of the liquid crystal.

Further, as the pixel region 201bb is miniaturized with the increase in the definition of the liquid crystal display device, the display capacity in the pixel region 201bb is reduced, and the TFT 208 having a high off-resistance is formed to reduce the leak current. Even so, there is a tendency that the display voltage is reduced during the non-selection period of the gate line 203b, and the display holding characteristics are likely to be lowered. However, in the liquid crystal display device of this example, the pixel electrode 2
06 is located above the previous gate line 203a,
A charge storage capacitor is formed between them. For this reason,
During the selection period of the pixel region 201bb, the previous gate line 2
03a is a non-selection period, by utilizing the fact that a reference potential is applied to the gate line 203a, charges are stored in the charge storage capacitor, and the retention characteristics of the liquid crystal applied voltage in the pixel region 201bb can be improved. . Moreover, in this example,
Since the pixel electrode 206 is formed so as to have a large overlapping area on the side of the gate electrode 203a in the preceding stage, the effect of improving the holding characteristics is remarkable.

(Embodiment 9) FIG. 20 shows Embodiment 9 of the present invention.
21 is a schematic plan view showing a part of the active matrix substrate used in the liquid crystal display device according to the first embodiment, and FIG. 21 is a cross-sectional view taken along the line IX-IX. Here, the liquid crystal display device according to the fourth embodiment shown in FIGS. 8 and 9 or FIGS.
Parts having functions corresponding to those of the liquid crystal display device according to Example 8 shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In these figures, the pixel region 201bb
Includes a source 204 to which the data line 202a is conductively connected;
A TFT 208 is constituted by a gate electrode 205 to which the gate line 203b is conductively connected and a drain 207 to which the pixel electrode 206 is conductively connected. Here, the pixel electrode 206 is made of IT as a conductive and light-transmitting material.
O is a transparent electrode formed over substantially the entire surface of the pixel region 201bb, and its end is connected to the data line 2
02a, 202b and the gate lines 203a, 203b. Each of the pixel electrodes 206 has a wide overlapping area on the side of the gate line 203a in the preceding stage.

The sectional structure of the pixel region 201bb is the same as that of the polycrystalline silicon layer 2 formed on the surface side of the transparent substrate 209.
In 10, a source 204 and a drain 207 are formed except for a channel region 211. This TFT 208
A lower interlayer insulating film 213 made of a silicon oxide film is deposited on the surface side of the first connection hole 21.
3a and the second connection hole 213b are opened. The data line 202a made of an aluminum layer is conductively connected to the source 204 via the first connection hole 213a.

On the other hand, through the second connection hole 213b,
Stacked electrode layer 214 is conductively connected to drain 207. Here, the surface of the lower interlayer insulating film 213 is
Although the unevenness is reflected according to the shape of T208, the stacked electrode layer 215 is formed to extend to the flat region 208a where the TFT 208 is not formed (the region where the TFT 208 is not formed). Therefore, this region 20
The surface of the stacked electrode layer 214 on 8a is flat. An upper interlayer insulating film 215 made of a silicon oxide film is formed on the surface of the transparent substrate 209, and the pixel electrode 206 is formed on the surface. The pixel electrode 206 is conductively connected to the stacked electrode layer 214 via the connection hole 215a of the upper interlayer insulating film 215. The connection hole 215a is formed on the flat region 208a where the TFT 208 is not formed. ing. Therefore, the pixel electrode 206 is conductively connected to the flat region of the stacked electrode layer 214.

In the liquid crystal display device of this embodiment, the data line 202a is connected to the lower first layer made of an aluminum layer.
The data line 202a _1, has a configuration is redundant wiring structure in the second data lines 202a ₂ of the upper layer side composed of a molybdenum silicide layer. On the other hand, the stacked electrode layer 214 also includes a lower first stacked electrode layer 214a made of an aluminum layer and an upper second stacked electrode layer 214b made of a molybdenum silicide layer. In addition, the source layer 202a and the stacked electrode layer 214 are in the same layer, and
2a ₁ and the first stacked electrode layer 214a be one that is co-formed, in which the second data line 202a ₂ and the second stacked electrode layer 214b are formed simultaneously. As the material for constituting the second data lines 202a ₂ and the second stacked electrode layer 214b, a material which is insoluble in an etchant when patterning the pixel electrode 206, to other molybdenum silicide, titanium silicide, Tungsten silicide, tantalum silicide, titanium, tungsten, tantalum, titanium nitride, or the like can be used.

In the liquid crystal display device of this embodiment, the pixel electrode 206 is located on the surface side of the upper interlayer insulating film 215.
On the lower layer side, a molybdenum silicide layer 216bb (conductive light-shielding layer) having a light-shielding property and a conductive property is formed.
b, 201ba, 201bc, and 201cb, the outer edges 216x of the data lines 202a,
02b and the gate lines 203a and 203b, and are aligned with the outer edge 206x of the pixel electrode 206. Here, a conductive light-shielding layer such as the molybdenum silicide layer 216bb is similarly formed in any of the pixel regions.
The molybdenum silicide layer 216bb is connected to the data line 202 at both outer edges 216x of the a, 216cb and 216bc.
a, 202b and gate lines 203a, 203b are insulated and separated from each other.

In the liquid crystal display device of this embodiment having such a configuration, since each of the molybdenum silicide layers 216bb...
9 side of the active matrix substrate,
When the opposing substrate side is opposed, the alignment accuracy does not matter. The molybdenum silicide layer 216
Since the potential of bb is in the state where the same potential as that of the pixel electrode 206 is applied, the alignment state of the liquid crystal is not disturbed, so that high display quality can be obtained. Further, since the black matrix 216 is composed of molybdenum silicide layers 216bb... Electrically independent for each pixel, the molybdenum silicide layer 216bb and the data lines 202a are in a short-circuit state in the pixel region 201bb. However, since the display is limited to the point defect of only the pixel region 201bb, the reliability of the liquid crystal display device is high.

Further, in the liquid crystal display device of the present embodiment, the data lines 202a have a redundant wiring structure, so that the reliability is high. Moreover, the stacked electrode layer 214 is also formed of the first stacked electrode layer 214a made of an aluminum layer.
And a second stacked electrode layer 214b formed of a molybdenum silicide layer, and the pixel electrode 206 formed of an ITO layer is formed of an aluminum layer via a second stacked electrode layer 214b formed of a molybdenum silicide layer. Since the molybdenum silicide layer functions as a contact layer between the ITO layer and the aluminum layer because it is conductively connected to the first stacked electrode layer 214a thus formed, the contact resistance thereat is reduced. Moreover, since the upper layer side second stacked electrode layer 214b is made of molybdenum silicide, the stacked electrode layer 214 is not affected by the etchant when the pixel electrode 206 is formed by etching.

Further, the data line 202a and the pixel electrode 20
6 is formed on layers different from each other, so there is no danger of short-circuiting. Therefore, since the end portion 206x of the pixel electrode 206 can be arranged up to a position above the data line 202a, an aperture ratio as much as possible can be secured. Further, since the pixel electrode 206 exerts a shielding effect on the data line 202a, the potential of the data line 202a does not disturb the alignment of the liquid crystal. Therefore, display quality is improved.

Since the pixel electrodes 206 are stacked via the stacked electrode layers 214, the connection holes 213 of the lower and upper interlayer insulating films 213 and 215 are formed.
Since both b and 215a have a structure with a low aspect ratio, the reliability of the conductive connection portion inside the connection holes 213b and 215a is high. In addition, the surface sides of the stacked electrode layer 214 and the upper interlayer insulating film 215 are
Although it has irregularities reflecting the shape of the FT 208, the connection hole 215a of the upper interlayer insulating film 215 is
8 is formed on the flat region 208a where the stacked electrode layer 214 and the pixel electrode 206 are not formed, the contact reliability between the stacked electrode layer 214 and the pixel electrode 206 is high, and the contact resistance is low. In addition, such a connection structure also has an effect of raising the level of a flat portion, flattening the surface of the pixel electrode 206, and improving the alignment state of the liquid crystal.

Further, in the liquid crystal display device of this embodiment,
The end of the pixel electrode 206 is located above the gate line 203a in the previous stage, and the pixel electrode 206 is formed to have a large overlapping area on the side of the gate electrode 203a in the previous stage, so that the retention characteristics are improved. The effect is remarkable.

(Embodiment 10) FIG. 22 is a schematic plan view showing a part of an active matrix substrate used in a liquid crystal display device according to Embodiment 10 of the present invention, and FIG. It is. Here, portions having functions corresponding to those of the liquid crystal display device according to the first embodiment illustrated in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Also in the liquid crystal display device of this embodiment, the vertical data lines 102a, 102b... (Signal lines) and the horizontal gate lines 103a, 103b.
Are arranged in a grid pattern, and each pixel region 101 is located between them.
aa, 101ab, 101ac, 101ba, 101b
.. are partitioned to form a matrix array. Among them, in the pixel region 101bb,
A source 104 to which the data line 102a is conductively connected, a gate electrode 105 to which the gate line 103b is conductively connected, and a drain 107 to which the pixel electrode 106 is conductively connected,
A TFT 108 is configured. Here, the pixel electrode 10
Reference numeral 6 denotes a transparent electrode made of ITO as a conductive and light-transmissive material, and is formed over substantially the entire surface of the pixel region 101bb. Here, on the surface side of the TFT 108, a lower interlayer insulating film 11 made of a silicon oxide film is formed.
3, the first connection hole 113a and the second connection hole 113b are opened. The data line 102a made of an aluminum layer is conductively connected to the source 104 via the first connection hole 113a.
On the other hand, through the second connection hole 113b, the pixel electrode 10
6 is conductively connected to the drain 107. Further, an upper interlayer insulating film 115 made of a silicon oxide film is formed on the surface side of the transparent substrate 109, and a molybdenum silicide layer 116bb is formed on the surface side. Here, the molybdenum silicide layer 116bb is connected to the pixel electrode 106 via the connection hole 115a of the upper interlayer insulating film 115.
And the connection hole 115a is connected to the TFT
As a flat region 108a where no 08 is formed, the flat region 108a is formed at a position diagonal to a position where the TFT 108 is formed in the pixel region 102bb. Therefore, the molybdenum silicide layer 116bb is conductively connected to the flat region of the pixel electrode 106.

Further, in the liquid crystal display device of this embodiment,
The gate electrode 105 has a thickness of 1 × 10 ^{20 on the} polycrystalline silicon layer.
/ Cm ^{3 in} a two-layer structure of a lower gate electrode layer 105a having a thickness of 1500 angstroms or less and a lower gate electrode layer 105b of a molybdenum silicide layer having a thickness of 2000 angstroms or less and a thickness of 2000 angstroms or less. Has become. Such a two-layer gate electrode is
First, after forming a polycrystalline silicon film to a thickness of 1000 angstroms, it is diffused in phosphorus and oxychloride in an oxygen and nitrogen atmosphere at a temperature of 850 ° C. to form a lower gate electrode layer 105a. , 200
A layer in which a 0-Å-thick molybdenum silicide layer is formed by sputtering to form an upper gate electrode layer 105b is dry-etched using a CF ₄ —O ₂ -based gas. Here, when the composition formula of molybdenum silicide constituting the upper layer side gate electrode 105b is represented by MoSix, the value of X is preferably set to 2.0 to 3.5, and a value larger than this range is preferable. In the case of (1), the resistance value becomes large, and it is suitable to prevent the occurrence of cracks when the resistance value is around 2.5. Note that tungsten silicide or titanium silicide can be used instead of molybdenum silicide.

In the liquid crystal display device of this example having such a configuration, since each molybdenum silicide layer 116bb... Is used as the black matrix 116, the active matrix substrate side formed on the transparent substrate 109 side and When the opposing substrate is opposed to the opposing substrate, the molybdenum silicide layer 116bb serves as a margin in the alignment of the opposing substrate-side black matrix, and the alignment accuracy does not matter. Further, since the potential of the molybdenum silicide layer 116bb is in the state where the same potential as that of the pixel electrode 106 is applied, the orientation of the liquid crystal is not disturbed, so that high display quality can be obtained. Further, since the black matrix 116 is electrically independent for each pixel, even if the molybdenum silicide layer 116bb and the data line 102a are in a short-circuit state in the pixel region 101bb, only a point defect in display occurs.

In the liquid crystal display device of this embodiment, the gate electrode 105 has a lower gate electrode layer 105a having a thickness of 1500 angstroms or less in which phosphorus is diffused into a polycrystalline silicon layer, and a thickness of 2000 angstroms or less. While adopting a polycide structure with the upper-side gate electrode layer 105b composed of a molybdenum silicide layer, the film thickness and the amount of introduced impurities are optimized to prevent the occurrence of cracks. The resistance of the gate lines 103a and 103b is reduced.
In addition, it is possible to prevent the lower interlayer insulating film 113 and the upper interlayer insulating film 115 from cracking.

In this example, the upper surface of the upper interlayer insulating film 115 has irregularities reflecting the shape of the TFT 108.
Reference numeral 15a denotes a TFT 108 in the pixel region 102bb as a flat region 108a where the TFT 108 is not formed.
08 is formed at a diagonal position from the formation position,
The reliability of the contact between the molybdenum silicide layer 116bb and the pixel electrode 106 is high.

(Embodiment 11) FIG. 24 is a schematic plan view showing a part of an active matrix substrate used in a liquid crystal display device according to Embodiment 11 of the present invention, and FIG.
It is sectional drawing in the I line. Here, FIG. 18 and FIG.
Parts having the same functions as those of the liquid crystal display device according to the eighth embodiment shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Also in the liquid crystal display device of this example, phosphorus as an n-type impurity is introduced into the polycrystalline silicon layer 210 formed on the surface side of the transparent substrate 209 in the pixel region 201bb except for the channel region 211. Thus, a source 204 and a drain 207 are formed. On the front side of the TFT 208, a lower interlayer insulating film 213 made of a silicon oxide film is deposited.
The connection hole 213a and the second connection hole 213b are opened. The data line 202a is conductively connected to the source 204 via the first connection hole 213a.

On the other hand, through the second connection hole 213b,
A stacked electrode layer 214 made of a chromium layer as a metal wiring layer having acid resistance is conductively connected to the drain 207. Here, the formation position of the connection hole 213b and the connection hole 21
The relationship between the connection hole 215a and the formation position of the connection hole 2a is as follows.
13b and the gate electrode 205.

In the liquid crystal display device of this embodiment, the pixel electrode 206 is located on the surface side of the upper interlayer insulating film 215.
On the lower layer side, a molybdenum silicide layer 216bb (conductive light-shielding layer) having a light-shielding property and a conductive property is formed.
b, 201ba, 201bc, and 201cb, the outer edges 216x of the data lines 202a,
02b and the gate lines 203a and 203b, and are aligned with the outer edge 206x of the pixel electrode 206. Here, a conductive light-shielding layer such as the molybdenum silicide layer 216bb is similarly formed in any of the pixel regions.
The molybdenum silicide layer 216bb is connected to the data line 202 at both outer edges 216x of the a, 216cb and 216bc.
a, 202b and gate lines 203a, 203b are insulated and separated from each other.

Further, in the liquid crystal display device of this embodiment, a driving circuit for driving the active matrix array is formed on the front surface side of the transparent substrate 209 with a CMOS circuit as shown in FIGS. 26 and 27. . Here, FIG. 26 is a cross-sectional view of a CMOS circuit of a driving circuit, and FIG.
Is a plan view thereof.

In these figures, an n-channel TFT
The TFT 410 and the p-channel TFT 420 are formed simultaneously with the active matrix side, but the gate electrode 205 and the data line 202 are formed on the active matrix side.
By utilizing the fact that the pixel electrode 206 and the pixel electrode 206 have the lower interlayer insulating film 213 or the upper interlayer insulating film 215 between the respective layers, a multilayer wiring structure is also formed on the drive circuit side. That is, the drive circuit side and the active matrix side are connected to the drive circuit side gate electrode 441, the drive circuit side gate electrode wiring layer 442, and the lower layer side interlayer insulating film 21.
3 up to the formation step, the respective steps are formed in cooperation with each other, and thereafter, the source lines 411 and 421 on the drive circuit side are formed.
Is formed, an upper interstitial insulating film 215 is formed.
Then, connection holes 415a and 415b are formed in the upper interlayer insulating film 215 and the lower interlayer insulating film 213,
The aluminum wiring layer 430 is conductively connected to the drains 417 and 427 of the n-channel TFT 410 and the p-channel TFT 420 via the connection holes 415a and 415b. The aluminum wiring layer 4
30 is formed on the surface side of the surface protection layer 230.
It is.

Also in the liquid crystal display device of this embodiment having such a configuration, since each molybdenum silicide layer 216bb is used as a black matrix, the same effect as that of the liquid crystal display device according to the eighth embodiment can be obtained. Therefore, the following effects are also obtained. That is, on the active matrix side, the gate electrode 205, the data line 202a, and the pixel electrode 206 are formed between the respective lower layers by the lower interlayer insulating film 2
13 or the upper layer side interlayer insulating film 215, the aluminum wiring layer 430 for the drains 417 and 427 of the n-channel TFT 410 and the p-channel TFT 420 is formed with a multilayer wiring structure. There is no problem such as a short circuit between wiring layers. In addition, because of the multilayer wiring structure, the n-channel type TF
The area required to form a drive circuit including the T410 and the p-channel TFT 420 is also small, and the pixel area can be expanded if the substrate area is the same, and if the pixel side area is the same, the substrate area can be increased. The whole, that is, the liquid crystal display device can be reduced in size.

[0122]

As described above, in the liquid crystal display device according to the present invention, the data line, the gate line crossing the data line, the source connected to the data line, and the gate line connected to the data line are formed on the substrate. A liquid crystal display device including a transistor having a gate electrode, a conductive layer connected to a drain of the transistor, and a pixel electrode connected to the conductive layer, wherein the conductive layer is a first layer on the drain. The pixel on the second insulating film is connected to the drain via a first contact hole formed in the insulating film, and is connected to the drain via a second contact hole formed in a second insulating film on the conductive layer. The second contact hole is connected to an electrode, and the second contact hole is disposed between the gate electrode and the first contact hole. According to the present invention, the second contact hole is formed more than the first contact hole.
Since the contact hole is disposed on the upper side, the orientation failure is more likely to occur in the second contact hole, which is the upper contact hole. Therefore, by arranging the position of the second contact hole as far as possible from the opening region, that is, between the first contact hole and the gate electrode, it is possible to suppress the influence of the alignment failure due to the second contact hole.

[0123]

[0124]

[0125]

[0126]

[0127]

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a part of a matrix array of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II of FIG.

FIG. 3 is a plan view illustrating a part of a matrix array of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a sectional view taken along line II-II in FIG.

FIG. 5 is a plan view illustrating a part of a matrix array of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 6 is a sectional view taken along line III-III in FIG. 5;

FIG. 7 is a schematic plan view of a matrix array of a liquid crystal display device according to a modification of the third embodiment of the present invention.

FIG. 8 is a plan view illustrating a part of a matrix array of a liquid crystal display device according to a fourth embodiment of the present invention.

9 is a sectional view taken along line IV-IV in FIG.

10A to 10C are process cross-sectional views illustrating a part of the method for manufacturing the liquid crystal display device illustrated in FIG. 8;

FIG. 11 is a plan view showing a part of a matrix array of a liquid crystal display device according to Embodiment 5 of the present invention.

FIG. 12 is a sectional view taken along line VV in FIG. 11;

13 (a) to 13 (d) are cross-sectional views showing steps of a method for manufacturing the liquid crystal display device shown in FIG. 11;

FIG. 14 is a plan view showing a part of a matrix array of a liquid crystal display according to a sixth embodiment of the present invention.

FIG. 15 is a sectional view taken along the line VI-VI in FIG. 14;

FIG. 16 is a plan view showing one matrix array of a liquid crystal display device according to Example 7 of the present invention.

FIG. 17 is a sectional view taken along line VII-VII in FIG. 16;

FIG. 18 is a plan view showing a part of a matrix array of a liquid crystal display device according to Example 8 of the present invention.

FIG. 19 is a sectional view taken along line VIII-VIII in FIG. 18;

FIG. 20 is a plan view showing a part of a matrix array of a liquid crystal display device according to Embodiment 9 of the present invention.

21 is a sectional view taken along line IX-IX in FIG.

FIG. 22 is a plan view showing a part of a matrix array of a liquid crystal display device according to Embodiment 10 of the present invention.

FIG. 23 is a sectional view taken along line XX of FIG. 22.

FIG. 24 is a plan view showing a part of a matrix array of a liquid crystal display device according to Embodiment 11 of the present invention.

FIG. 25 is a sectional view taken along line XI-XI in FIG. 24;

FIG. 26 is a cross-sectional view illustrating a configuration of a part of a drive circuit formed on the same substrate as a matrix array of a liquid crystal display device according to Embodiment 11 of the present invention.

FIG. 27 is a plan view showing a configuration of a part of a drive circuit formed on the same substrate as a matrix array of a liquid crystal display device according to Embodiment 11 of the present invention.

FIG. 28 is a plan view showing a part of a matrix array of a conventional liquid crystal display device.

29 is a sectional view taken along line XII-XII in FIG.

FIG. 30 is a plan view showing a part of a matrix array of a liquid crystal display device according to a comparative example.

31 is a sectional view taken along line XIIII-XIIII in FIG. 30.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuo Yudasaka 3-5-5 Yamato, Suwa-shi, Nagano Inside Seiko Epson Corporation (72) Inventor Takashi Inoue 3-3-5 Yamato, Suwa-shi, Nagano (56) References JP-A-4-291240 (JP, A) JP-A-2-245741 (JP, A) JP-A-59-194783 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/136

Claims (1)

(57) [Claims] A transistor including a data line on a substrate, a gate line intersecting the data line, a source connected to the data line, and a gate electrode connected to the gate line; and a drain of the transistor. A liquid crystal display device having a conductive layer connected to the conductive layer and a pixel electrode connected to the conductive layer, wherein the gate electrode is disposed so as to protrude from the gate line, and the conductive layer is formed on the drain. Connected to the drain through a contact hole formed in the first insulating film, and formed in a second insulating film formed in the second insulating film on the conductive layer.
A liquid crystal display, wherein the liquid crystal display is connected to the pixel electrode on the second insulating film via a contact hole, and the second contact hole is disposed between the gate electrode and the first contact hole. apparatus.