JP3289371B2 - Heterojunction Hall element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) or G
The present invention relates to a heterojunction Hall element having a semiconductor heterojunction (heterojunction) made of, for example, InAs and InP. In particular, the electron mobility of a crystal layer serving as a base material of the element is improved, thereby increasing the sensitivity of the Hall element. On how to make it.

[0002]

2. Description of the Related Art A Hall element is known as one of the so-called magnetoelectric conversion elements which detects a magnetic field and generates an electric signal according to the strength. This Hall element is a kind of magnetic sensor that uses a Hall (Hall) voltage generated by the movement of electrons in the semiconductor constituting the Hall element when a magnetic field is applied as a detection amount. It is used extensively in industry.

As semiconductor materials for the Hall element, in addition to elemental semiconductors such as silicon (Si) and germanium (Ge), elements such as indium antimonide (InSb), indium arsenide (InAs) and gallium arsenide (GaAs) are used. A III-V binary compound semiconductor obtained by combining two elements belonging to Group V as well as an element belonging to Group III of the periodic table is also used.

However, looking at conventional Hall elements made of compound semiconductors, there are advantages and disadvantages in the characteristics of Hall elements depending on the physical properties of the semiconductor used. For example, a Hall element made of GaAs has a small temperature change in element characteristics due to a relatively large band gap of a GaAs semiconductor. On the contrary, the product sensitivity is lower than that of a Hall element made of InSb because electron mobility is somewhat low. There is a disadvantage that. On the other hand, the InSb Hall element has a large temperature change in characteristics due to the low band gap of the InSb semiconductor, but has an advantage of obtaining high product sensitivity.

Recently, the need for precision sensing technology in a high-temperature environment, such as precise rotation control of an automobile engine, has increased, and the device has a capability of outputting a high Hall voltage and has a low change in element characteristics due to temperature. There has been a demand for a new suppressed high-performance Hall element. Here, the Hall voltage depends on the Hall coefficient of the semiconductor material,
The larger the Hall coefficient, the higher the output capability of the Hall voltage. The Hall coefficient increases in proportion to the mobility of the semiconductor material. Therefore, in order to obtain a high Hall output voltage, that is, to obtain a high-sensitivity Hall element, it is necessary to use a semiconductor material that exhibits high electron mobility.

[0006] For this reason, in consideration of the demand for high-performance Hall elements from the industry, studies have been made on the physical properties of semiconductor materials. More recently, three types of elements have been mixed even in the same group III-V compound semiconductors as before. Attempts have also been made to apply a material having a heterojunction composed of ternary mixed crystal of gallium indium arsenide (GaInAs) and indium phosphide (InP) as a material for a high-sensitivity Hall element (Shinobu Okuyama) Et al., Proceedings of the 53rd Autumn Meeting of the Japan Society of Applied Physics, 1992, No. 3
6a-SZC-16, p. 1078). This new GaI
An nAs Hall element has a relatively small change in characteristics with temperature and an extremely high electron mobility at room temperature, so that it has excellent product sensitivity. Hereinafter, this GaInAs heterojunction Hall element will be described as an example of the heterojunction Hall element, and the present invention will be described.

[0007] Such a GaInAs Hall element is generally composed of Ga _x In ₁ -x As (x is a mixed crystal ratio (composition) which is grown on a high-resistance semi-insulating InP single crystal substrate to which an appropriate amount of Fe is added. The film is configured as a magnetically sensitive portion. However, the Ga _x In _1-x As film is simply made of Fe-added In.
This Ga _x In is merely deposited on a P single crystal substrate.
High mobility is not always provided stably to the _1-X As film. This is mainly because Fe impurities contained in a high-resistance InP single crystal used as a substrate are exposed to a certain high-temperature growth environment to epitaxially grow a desired Ga _X In _1-X As film on the InP single crystal. This is due to thermal diffusion into the Ga _x In _{1- x} As film growing from the InP single crystal substrate side when exposed. That is, the Fe impurity acts as a so-called electron trap and hinders the movement of electrons, thereby hindering the improvement of the mobility.
In order to prevent this, a high resistance, for example, InP
Ga _x In as a buffer layer (buffer layer)
_1-X As inserted between the magneto-sensitive film and the InP substrate,
Attempts have also been made to reduce the propagation of impurities or crystal defects in the P-substrate crystal to the magnetosensitive layer and increase the electron mobility.

However, even if such a buffer layer made of InP crystal is provided on a high-resistance InP crystal, the G layer can be stably formed.
not yet been improve the electron mobility of a _X In _1-X As sensing section layers at present. In order to stably impart high mobility characteristics to the GaInAs magnetosensitive layer, for example, the Fe concentration in a Fe-added semi-insulating InP single crystal used as a substrate is defined within a certain range, and only a substrate satisfying the conditions is specified. It is also conceivable to use flameless and flameless
s) An InP semi-insulating substrate having a desired Fe concentration may be appropriately selected based on the results of quantitative analysis of Fe impurities by a micro-quantitative analysis technique such as atomic absorption spectroscopy or high-frequency induction argon plasma spectroscopy. Is Fe in the substrate crystal
It is necessary to provide a process for analyzing impurities and for selectively separating the substrate crystal, and it is a fact that the process is complicated.

On the other hand, when the InP crystal layer is used as a buffer layer in accordance with the amount of Fe impurities added to the semi-insulating InP crystal substrate, the buffer layer is used in accordance with the magnitude of the Fe concentration. It is thought that the thickness of the film may be appropriately increased or decreased. However, this is also a complicated operation, and G
In order to prevent a decrease in the electron mobility of the aInAs magnetosensitive layer, the amount of Fe impurities diffused from the InP substrate side into the GaInAs crystal layer is kept constant.
It is not easy to change the thickness of the buffer layer for each InP substrate crystal, and a good yield based on the electron mobility that should be provided in the GaInAs magnetosensitive layer in order to increase the sensitivity of the GaInAs Hall element. Judging from the above, at present, it cannot be a method capable of stably increasing the yield of non-defective products.

In order to overcome such a situation and to improve the electron mobility of the GaInAs magnetically sensitive layer, the inventors conducted intensive studies on factors that strongly influence the electron mobility of the GaInAs magnetically sensitive crystal layer. The inventors have found that the degree is greatly influenced by the distribution of the carrier concentration near the heterojunction interface, and have reached the present invention.

[0011]

SUMMARY OF THE INVENTION The present invention provides a new technique for achieving a high mobility of a heterojunction crystal layer serving as a base material of a heterojunction Hall element without complicated operations and steps.

[0012]

SUMMARY OF THE INVENTION In a heterojunction Hall element comprising semiconductor crystal layers having different band gaps, the carrier concentration of a semiconductor crystal layer having a small band gap is made larger than that of a semiconductor crystal layer having a large band gap. By increasing the carrier concentration in the vicinity of the hetero-interface of the semiconductor crystal layer having a small band gap and making it higher than that in the portion other than the vicinity of the hetero-interface in the semiconductor crystal layer having the small band gap, High electron mobility can be imparted to the heterojunction Hall element.

Hereinafter, GaInAs / InP as described above is used.
This will be described in more detail by taking a heterojunction Hall element as an example.
Usually, in forming a GaInAs / InP heterojunction Hall element, a high-resistance semi-insulating InP single crystal substrate is used. Practical resistance is 10 ⁶ Ω · cm
It is common to use a substrate of the above InP single crystal,
These crystals are liquid sealed Czochralski (Liquid Enc
apsulated Czochralski (LEC) method and recently VB
(Vertical Bridgman) method can be easily manufactured by the vertical Bridgman method or the like. In addition, when there is a concern that the Fe impurity in the Fe-doped InP single crystal may adversely affect the electrical characteristics such as the electron mobility of the crystal layer, the InP
A single crystal is dissolved with hydrochloric acid, etc., and is dissolved in pure water, etc., and wet instrument analysis such as atomic absorption spectrometry or high-frequency induction argon plasma spectrometry, or solid instrument analysis such as secondary ion mass spectrometry It suffices to quantitatively analyze the concentration of the Fe impurity by using and select a crystal having a desired Fe concentration. Therefore, the GaInAs / GaInA according to the present invention.
There is no danger of obstructing the acquisition of an InP substrate crystal having an Fe concentration within a certain range necessary for realizing the s Hall element.

[0014] While forming the deposited heterojunction the InP layer and the n-type Ga _X In _1-X As layer to the InP single crystal substrate is not limited to the stacking order of these epitaxial layers, the InP single crystal substrate An InP layer may be first grown on it, followed by GaInAs deposition, or it may be deposited in the reverse order. However, in order to improve the electron mobility of the GaInAs layer, which is usually a magnetic sensing portion, the Fe impurity G from the InP single crystal substrate is required.
Generally, first, InP is generally deposited as a buffer layer on an InP single crystal substrate in order to suppress diffusion into the aInAs epitaxial growth layer. Providing this buffer layer produces effects such as suppressing propagation of crystal defects and the like to the epitaxial growth layer.
The advantage is that the high sensitivity characteristic of the GaInAs Hall element can be maintained without unnecessarily reducing the electron mobility of the GaInAs layer.

The above InP buffer layer and GaInA
The growth method of the s layer is not particularly limited, and is, for example, a liquid phase epitaxial growth method (LPE method) or a molecular beam epitaxial growth method (Molecular Beam Eptaxial method).
A metal organic vapor phase epitaxy (MOVPE) method or a metal organic vapor phase epitaxy (MOVPE) method.
It may be called OCVD or OMVPE. ) Or an MO / MBE method in which both MOVPE and MBE are combined. However, at present, In containing phosphorus (P) having a relatively high vapor pressure In
The MOVPE method is frequently used for growing a semiconductor thin film such as P from the viewpoint of stoichiometric composition control rather than the MBE method. In particular, a monovalent cyclopentadienyl indium having a valence of 1 is used as a starting material for In. In the MOVPE method using (C ₅ H ₅ In), high-quality InP, GaInAs, and the like can be obtained even under normal pressure (atmospheric pressure), which has been conventionally difficult. Further, an InP layer is grown by the MOVPE method, and a Ga _{x In 1 -x} As layer containing no P is formed by MB.
There is no problem even if the growth method is different for each layer such as by the E method, and it is not necessary to provide each layer forming the heterojunction by one growth method, and the growth method may be different for each layer. Of course.

Further, the mixed crystal ratio x of Ga _x In ₁ -x As is as follows.
Is desirably 0.37 ≦ x ≦ 0.57. Because Ga _x In _{1 -x} A lattice-matched to InP
As the mixed crystal ratio deviates from the mixed crystal ratio x = 0.47, Ga
The difference between the lattice constants of _X In _{1 -X} As and InP, that is, the degree of lattice mismatch, is also remarkable, causing a large number of crystal defects and the like, leading to a decrease in crystallinity as well as electrical properties such as a decrease in electron mobility. Is also deteriorated, which greatly impairs the improvement of the product sensitivity due to the characteristics of the Hall element.

Further, the n-type Ga _X I serving as the above-mentioned magneto-sensitive section layer
The n _1-x As crystal layer increases the carrier concentration in the depth direction toward the hetero interface with the InP crystal layer. It is relatively easy to form such a carrier concentration distribution. For example, sulfur (element symbol S) which becomes an n-type dopant when growing the Ga _x In ₁ -x As crystal layer after growing the InP crystal It can be achieved by changing the amount of doping gas containing silicon or silicon (element symbol Si) to the growth system, that is, by changing the flow rate of the doping gas with time.

Further, the supply amount of the source gas containing the group III element such as Ga or In at the initial stage of the growth of the Ga _x In _1-x As crystal layer without changing the flow rate of the doping gas added to the growth system. The carrier concentration distribution can be maintained even if the ratio of the supply amount of the source gas containing As, which is a group V element, to the so-called V / III ratio is gradually changed. Specifically, for example, trimethylgalim (trimet) used as a Ga source
yl gallium: (CH ₃ ) ₃ Ga) and C ₅ H _{5 as} In source
The supply ratio of arsine (AsH ₃ ) to the total supply amount of In may be changed appropriately. Whether the V / III ratio is changed from the high ratio side to the low ratio side, or conversely, from the low ratio side to the high ratio side, depends on whether the background growth layer in the undoped (non-added) state. What is necessary is just to determine in consideration of various factors, such as a conductivity type, a carrier density, and the doping efficiency at the time of doping. Further, when the GaInAs crystal layer already has an appropriate electron concentration in an undoped state without doping, the V / III ratio is appropriately changed without performing any doping operation to distribute the carrier concentration. It is also possible to have.

Further, the Ga _x In _1-x As crystal layer and the InP
The carrier concentration at the interface with the crystal layer is basically G
a _X In _1-X As it is sufficient that exceeded that of the surface of the crystal layer, but is increased from 2-fold of the carrier concentration at the surface to about 20 times a significant improvement in electron mobility can play.

Next, the Ga _X In _{1 -X} A according to the present invention is used.
There is no particular limitation on the thickness of the s layer. However, in the actual manufacture of the Hall element, a step called mesa etching for removing a crystal layer in a specific region is generally adopted in order to electrically insulate the elements. Therefore, if the thickness of the layer exhibiting conductivity to be removed by mesa etching and the overall thickness of the epitaxial growth layer increase, the time required for mesa etching necessarily increases, and etching due to the crystal orientation is inevitable. Significant differences in volume as well as in etched shape. This leads to an increase in the unbalance rate, which is one of the important characteristics of the Hall element, which hinders the improvement of the element characteristics and lowers the yield of non-defective elements. Accordingly, in forming the heterostructure described in the present invention, good results can be obtained by setting the total thickness of the Ga _x In ₁ -x As layer and the InP layer, which are the constituent elements, to be less than about 5 μm.

As described above, a GaInAs Hall element was manufactured using a heterojunction epitaxial wafer composed of a GaInAs magnetosensitive layer and an InP buffer layer grown on an InP single crystal substrate as a base material. In this fabrication, a well-known processing technique such as a photolithography technique and an etching technique is used, and first, a so-called mesa etching is performed on the GaInAs magnetic sensing portion layer and the InP layer exhibiting a function as a Hall element, and the element function is improved. The area is processed into a mesa shape. A method of obtaining the mesa structure will be described here. First, a general photoresist material is applied to the surface of the Ga _x In _1-x As layer which is the outermost surface of the base material, and then, the usual photolithography is performed. According to the technique, the resist material is left only in the area where the magnetic sensing portion and the input and output electrodes are formed, and the resist material in the other areas is peeled off. Then, the GaInAs layer and the In in the region where the resist material was removed by using an inorganic acid were
The P buffer layer is removed by etching. By this etching, the electrode forming portion and the magneto-sensitive portion region are trapezoidal, a so-called regular mesa shape, or an inverted trapezoidal shape, a so-called inverted mesa plateau (depending on the axial direction of the crystal). Mesa). By this mesa etching, the electrical insulation of the electrode function part and the element function part including the magnetic sensing part area can be secured. However, in the mesa etching, when the total thickness of the growth layer exceeds 5 μm, the difference in the etching shape based on the crystal axis (crystal orientation) becomes remarkable as described above. This leads to an increase in the voltage, which leads to a worsening of the unbalance rate. Therefore, as described above, the overall thickness of the epitaxial growth layer used for manufacturing the Hall element is approximately 5 μm.
The setting below is more advantageous in that the imbalance rate is not increased.

After mesa etching, input and output electrodes are formed. In this formation, a general photoresist material is applied to the entire surface of the mesa-etched wafer. Thereafter, the area where the electrode is to be formed is patterned by a known photolithography method (pattern).
ning) to remove and remove only the photoresist material in the region where the input / output electrodes are formed, and to remove the GaInA
s Exposing the magnetic sensing layer layer surface.

Next, a gold (Au) -germanium (Ge) alloy serving as an electrode material is vacuum-deposited on the processed resist material. Here, an Au.Ge alloy was used as the electrode material, but the electrode material is not particularly limited to this, and other metal materials may of course be used. Further, in parallel with the stripping of the resist material, a so-called lift-off method is used to remove an alloy film unnecessary on device fabrication, which is adhered on the resist material. Incidentally, there is no problem even if the shape of the electrode is rectangular, polygonal, circular, or elliptical.

Next, silicon dioxide (SiO ₂ ) having an insulating property is deposited by a known plasma CVD method to cover the wafer surface. In the present invention, general SiO ₂ is used as the insulating coating film, but another insulating film such as silicon nitride (SiN) may be used. Next, the SiO ₂ insulating film manufactured as described above is covered with a general resist material. After that, the resist material at a position corresponding to a position for forming a dicing line necessary for so-called dicing, which is separated into an electrode portion and an individual element, is subjected to a patterning method using a known photolithography technique. Utilization is used to expose the underlying SiO ₂ insulating film. Further, the exposed SiO ₂ insulating film is immersed in hydrofluoric acid (chemical formula HF) to dissolve and remove the SiO ₂ insulating film in that portion. As a result, the surface of the GaInAs layer is exposed at the surface of the input / output electrode and the portion where the dicing line is formed.

In actual separation into individual elements,
GaI exposed at the portion corresponding to the dicing line
The nAs layer may be removed by etching using a suitable inorganic acid. Thereafter, the InP layer immediately below the GaInAs layer is removed with an inorganic acid. Usually, etching is further advanced to remove a part of the surface layer of the InP single crystal substrate. The scriber used for dicing (su
This is to reduce in advance the occurrence of mechanical damage to the epitaxial growth layer and the hetero interface at the time of element isolation by a criber or a blade.

The main electrical characteristics of the new GaInAs Hall element according to the present invention, especially the product sensitivity,
These were compared with those of the As Hall element. In the conventional Hall element, the carrier concentration profile in the GaInAs magneto-sensitive layer is almost flat from the surface side of the layer to the hetero interface of the InP crystal layer. Refers to a Hall element made of a wafer that is not provided. However, even in the conventional example, only the distribution of the carrier concentration in the depth direction is different, and other components such as the thickness of the crystal layer are the same. As a result of comparing both,
There is a remarkable difference in the product sensitivity, which is an important characteristic that determines the superiority of the Hall element, and the novel Ga
In the InAs Hall element, the product sensitivity was remarkably improved. To find out the cause of this problem by comparing and examining the material with the conventional example, it was found that G
This is considered to be due to the distribution of the carrier concentration in the vicinity of the aInAs / InP hetero interface.

[0027]

The distribution of the carrier concentration in the GaInAs magnetic sensing layer has a function of improving the electron mobility of the magnetic sensing layer, so that the high sensitivity GaInAs can be easily obtained.
Provide a Hall element.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will now be described with reference to GaInAs / In.
A specific description will be given using a P heterojunction Hall element as an example.
FIG. 1 shows an example of a schematic plan view of a GaInAs / InP heterostructure Hall element according to the present invention. FIG.
FIG. 2 is a schematic cross-sectional view of the Hall element shown in FIG. 1 in a vertical direction along a broken line AA ′. In forming the heterojunction, a semi-insulating InP single crystal (101) having a plane orientation of (100) obtained by adding iron (Fe) was used as a substrate. The thickness of the InP single crystal (101) is about 350 μm.
m. In FIG. 1, reference numeral (102) denotes a MOCV at normal pressure (atmospheric pressure) using C ₅ H ₅ In as an In source on a crystal substrate (101).
This is an undoped (undoped) InP epitaxial crystal layer having a thickness of about 100 nm and grown by the method D. The InP layer (102) serving as a buffer layer was grown at a temperature of 610 ° C. Further, an n-type Ga having a mixed crystal ratio of 0.47 and a thickness of about 400 nm is formed on the InP buffer layer (102).
_{A 0.47} In _0.53 As epitaxial layer (103) was provided using the normal pressure MOCVD growth method described above. The Ga _0.47 In _0.53 As epitaxial layer (10
The growth temperature of 3) is 610 ° C. like the InP layer (102).
And the above InP layer (102) and n-type GaInAs
The carrier concentration of each layer (103) is 2 × 10 ¹⁵ cm ^−3.
And 2 × 10 ¹⁶ cm ⁻³ . In addition, this GaInAs
The carrier concentration of the layer (103) is achieved by so-called doping by intentionally adding sulfur (S) belonging to Group VI of the periodic table, and the InP layer (102) and the GaInAs layer (103) Near the hetero interface of
The doping amount was changed so that the carrier concentration of the aInAs layer (103) was 8 × 10 ¹⁶ cm ⁻³ , which is four times the carrier concentration on the surface, 2 × 10 ¹⁶ cm ⁻³ . From the surface side of the GaInAs layer (103) to the InP single crystal substrate (1) through the hetero interface with the InP layer (102).
FIG. 3 shows the distribution of the carrier concentration up to 01) in comparison with that of the conventional example.

The electron mobility of a wafer having such a carrier concentration distribution is 11,000 cm ² / V at room temperature.
-It was s. On the other hand, that of a conventional wafer having a flat carrier concentration profile is about 8,000 cm ² /
V · s.

First, the wafer having such a structure is subjected to mesa etching using a well-known photolithography method and an etching method to leave a trapezoidal element function area exhibiting the function of the Hall element, and to perform a magnetic sensing section and the like. The mesa region (104) containing is formed. Thereafter, the surface of the wafer is covered with a photoresist material, and through processes such as patterning, resist peeling, and lift-off, G serving as an input and output electrode is formed.
Au-Ge alloy containing 13wt%
An ohmic input / output electrode (105) was formed by vacuum evaporation to a thickness of nm. The shape of each of these electrodes (105) is the same, and the plane has a long side of about 200 μm and a short side of about 7 μm.
It has a rectangular shape of 0 μm.

Further, the entire surface of the wafer was once covered with an SiO ₂ insulating film (106) by a plasma CVD method. The thickness of the SiO ₂ film (106) was about 300 nm. Next, a photoresist material was applied on the insulating film (106), and the surface of the input / output electrode (105) was exposed through photolithography, patterning, and other steps. A dicing line (107) for separating into individual Hall elements was formed. Thereafter, scribing was performed along the dicing line (107) to separate the individual elements (chips). In forming the chip, a part of the back surface of the InP single crystal substrate (101) is removed by etching to reduce the thickness of the substrate from an initial thickness of 350 μm to about 130 μm,
Scribing made easy.

After chipping by scribing, the chip is mounted on a very common metal frame,
One end of the lead wire was bonded to a pad electrode by an ultrasonic bonding method, and the other end of the lead wire was connected to a lead terminal attached to a metal frame. After the appropriate connection operation, the Hall element was surrounded with epoxy resin and molded.

The electrical characteristics of the Hall element manufactured as described above were evaluated. The conventional GaI
The characteristics of the nAs Hall element were also evaluated. Here, the conventional Hall element has the same laminated structure of the wafer, and the carrier concentration distribution does not show a distribution in the hetero-interface direction.
Refers to nAs Hall element. Among the results of comparing the characteristics,
Particularly, regarding the sensitivity of the Hall element, a remarkable difference was recognized between the Hall element of the present invention and the conventional Hall element. In the Hall element according to the present invention, the obtained sensitivity is increased by about 20% as compared with the conventional Hall element. This rate of increase is in very good agreement with the increase in electron mobility, indicating that the present invention has improved the electron mobility of the base material of the Hall element and, consequently, has increased the sensitivity of the Hall element. confirmed. In the above-described embodiment, G
The effect was shown by taking an aInAs / InP heterojunction Hall element as an example.
As, GaInAs / AlInAs heterojunction Hall elements can also be exhibited.

[0034]

According to the present invention, a new limitation is added to the distribution of the carrier concentration of the semiconductor magneto-sensitive layer constituting the hetero junction.
This improves the electron mobility of the magnetosensitive layer, thereby providing an effect of easily achieving high sensitivity of the heterojunction Hall element.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a GaInAs Hall element according to the present invention.

FIG. 2 is a schematic diagram of a cross section taken along a broken line AA ′ of the schematic plan view shown in FIG.

FIG. 3 is a diagram illustrating a distribution of a carrier concentration of a base material of a GaInAs Hall element according to the present invention and a conventional example in a depth direction.

[Explanation of symbols]

(101) InP semi-insulating single crystal substrate (102) Undoped InP buffer layer (103) Ga _0.47 In _0.53 As magnetic sensing part layer with a mixed crystal ratio of 0.47 (104) Mesa-shaped element function part region ( 105) Ohmic input / output electrodes (106) SiO ₂ insulating film (107) Dicing line

Continuation of the front page (56) References JP-A-5-275767 (JP, A) JP-A-60-198877 (JP, A) The 53rd Autumn Meeting of the Japan Society of Applied Physics, Proc. 3, p. 1078 Revue de Physique Applique, Vol. 18, No. 12 (1983) pp. 757-761 (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 43/06 G01R 33/07 JICST file (JOIS)

Claims (2)

(57) [Claims] A first semiconductor crystal layer and a second semiconductor having a larger band gap than the first semiconductor crystal layer on the semiconductor single crystal substrate and having a lower carrier concentration than the first semiconductor crystal layer; A heterojunction comprising a crystal layer, and the carrier concentration of the first semiconductor crystal layer in the vicinity of the hetero interface is determined by comparing the carrier concentration in a portion of the first semiconductor crystal layer other than the vicinity of the hetero interface. A heterojunction Hall element characterized by having a higher height. 2. The method according to claim 1, wherein the first semiconductor crystal layer is a gallium indium arsenide (GaInAs) crystal layer, and the second semiconductor crystal layer is an indium phosphide (InP) crystal layer. The heterojunction Hall element according to claim 1.