JP3287436B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on an insulating substrate and a method of manufacturing the same, and more particularly, to a silicon device.
The present invention relates to a semiconductor device having an On Insulator (hereinafter referred to as SOI) structure and a method for manufacturing the same.

More specifically, after a semiconductor device such as a high-performance, high-performance electronic device or integrated circuit is formed on a single crystal semiconductor substrate, the semiconductor device is supported by a support substrate, and the semiconductor device of the single crystal semiconductor substrate is formed from the back surface. SOI having a structure in which a semiconductor device is arranged on an electrical insulating layer by removing a single crystal semiconductor substrate except for a portion and finally forming an electrical insulating layer
The present invention relates to a semiconductor device having a structure and a manufacturing method thereof.

[0003]

2. Description of the Related Art Much research has been made on SOI technology because it has a number of advantages that cannot be attained with a bulk silicon substrate for fabricating ordinary silicon integrated circuits.

[0004] That is, by using the SOI technology, 1. Dielectric separation is easy and high integration is possible. 2. Excellent radiation resistance. 3. Higher speed due to reduced stray capacitance. Advantages such as latch-up can be prevented and high withstand voltage characteristics can be improved.

[0005] Relatively recently, Zone Meltin
g Recrystallization method (hereinafter referred to as Z
MR), Separation by Ion
Implanted Oxygen method (hereinafter referred to as SIM
OX), a bonding SOI method, and the like, have been proposed.

In the ZMR method, an opening is provided in a part of a single crystal silicon substrate covered with a SiO ₂ film, and an amorphous or polycrystalline silicon layer deposited thereon is exposed to an electron beam, a laser beam, or the like. A single crystal silicon layer is grown on a SiO ₂ film by converging an energy beam and irradiating it, or by scanning a molten region in a strip shape using a rod-shaped heater and melting and recrystallizing the single crystal substrate surface at the opening as a seed. It is. In this method, a relatively large-scale integrated circuit is also experimentally manufactured, but a large number of crystal defects such as sub-grain boundaries still remain, and a minority carrier device has not been manufactured.
In addition, there are many problems in controllability and productivity.

The SIMOX method is a method in which oxygen is ion-implanted into a silicon single crystal substrate to form an SiO ₂ layer inside the silicon single crystal substrate. This technique is currently the most mature technique because it can form an ultra-thin silicon active layer of 0.1 μm or less and has good compatibility with a silicon process.

However, it is necessary to implant oxygen ions of 10 ¹⁸ ions / cm ² or more in order to form the SiO ₂ layer, and the implantation time is long, and there is a problem in productivity. In addition, there is a problem that the production cost is inevitably high because an expensive ion implantation apparatus is required.
Further, expansion of internal silicon single crystal by the SiO ₂ layer, there is a problem of generating a crystal defect caused by a stress in the silicon single crystal thin film layer on the SiO ₂ layer to extend.

On the other hand, in the bonding SOI method, a support substrate of the same or different type from a single crystal silicon substrate is mirror-polished with each other, and the flat surfaces thereof are bonded together via an SiO ₂ layer or the like, and after heat treatment, One of the single-crystal silicon substrates to be an active layer is polished to leave a single-crystal silicon thin film on the insulating film.

In this method, since the bulk itself is used as the active layer, good crystal quality is obtained, and attention has recently been paid to a technique for easily obtaining an SOI substrate.

On the other hand, if the flatness and cleanliness of the bonding surface are not ensured due to the bonding of the hard substrate, unbonded voids will remain at the bonding interface, and after bonding, single-crystal silicon having a thickness of generally 1 μm or less will be obtained. Silicon for thin film
Active layers are likely to be missing, which can cause significant problems in the process steps.

Further, unlike the previous example, it is necessary to reduce the thickness of the single crystal silicon substrate by mechanical polishing or chemical etching. Assuming a silicon thin film of 1 micron as the SOI, the thickness accuracy is required to be ± 0.1 microns or less.

On the other hand, when a different material such as glass is used for the support substrate due to the requirement for transparency, the substrate is likely to be broken or peeled off due to a difference in thermal expansion coefficient in the heat treatment at the time of bonding up to 1100 ° C. There's a problem.

In general, expensive quartz glass having excellent heat resistance is used in order to match a high temperature silicon process. However, in order to reduce thermal stress, the thickness of a single crystal silicon thin film before heat treatment is 0.5 μm. The polishing accuracy is further restricted as follows.

In addition, since one substrate is necessarily produced from two substrates, there is a problem that the cost is increased. From the viewpoint of cost reduction, the use of a low-cost substrate such as low-melting glass as a support substrate is also being considered, but there is a problem with heat resistance and the development of a low-temperature silicon process is premised. Process not established.

Moreover, various compounds are added to the low melting point glass. In particular, contamination of the silicon process by alkali ions causes serious problems in the operational stability of the semiconductor device.

In contrast to these methods of manufacturing an SOI substrate before forming a semiconductor device, a semiconductor device is formed on a single-crystal silicon substrate, and then polyimide, epoxy, or boron-phosphorous silicate glass (hereinafter, referred to as “polysilicon”) is formed on the surface. BPS
G) or an adhesive such as wax or the like, is adhered to the first support substrate, the back surface of the single crystal silicon substrate is polished or the like is removed, and another second surface is attached to the removed surface via an adhesive. There has also been proposed a method of bonding a support substrate, removing the first support substrate and its adhesive, and completing a substrate having an SOI structure in which integratedly arranged elements are formed.

In this method, a circuit to be laminated is prepared in advance, bonded to a support substrate in the final stage, and a semiconductor device is polished from the back surface of the semiconductor substrate. Device transfer (hereinafter referred to as DT)
This method is called the SOI method, and was first proposed by Nieren et al. (JA van N).
IElen, M .; J. J. Theunissen an
d J. A. Appels, Philips Tech
physical Review, vol. 31, no. 7 /
8/9, pp. 271-275, 1970. Or,
U.S. Pat. No. 3,677,846).

The manufacturing method will be described with reference to FIGS.

First, as shown in FIG. 5A, an n-type epitaxial layer 37 on an n ⁺ -type single crystal silicon wafer 36 is formed.
Next, a UHF band MOS transistor 38 is formed using a well-known silicon process. Next, as shown in FIG. 5B, a glass substrate 40 is attached to the surface via a wax 39. Further, as shown in FIG. 5C, the n ⁺ -type single crystal silicon 36 and the n-type epitaxial layer 37 on the back surface of the transistor are removed by electrochemical etching to reduce the thickness to 2 μm. Next, as shown in FIG. 5D, the wax and the glass substrate are removed. Finally, as shown in FIG. 5E, a polymer 41 is applied to the back surface of the transistor (the etched surface), and is adhered and supported on a ceramic substrate.

Then, as an improvement of the thinning method, LOCOS (Local Oxidation of LOCOS) is utilized by utilizing the selectivity of the single crystal silicon thin film to the etching solution.
Hamaguchi et al. Reported a method of transferring a bipolar transistor to a quartz substrate by a selective polishing transfer method using a combination of mechanical polishing by polishing and chemical etching with an amine-based etchant using an oxide layer as a stopper (No. 46th Annual Meeting of the Japan Society of Applied Physics, Proceedings of the Lecture, Lecture No. 1p-V-9, 1
985).

In this case, the structure is such that polyimide is supported on a quartz glass substrate as an adhesive.

On the other hand, a technique of molding a block made of a glass material as an optical lens using, for example, a mold having an aspherical shape has been industrially practically used (Japanese Patent Publication No. 54-38126; Japanese Patent Application Laid-Open No. Sho 52-38126). 45613. JP-A-58-84134, Kenzo Matsuzaka: Applied Mechanical Engineering, April, pp. 159-165, 1986).

This is similar to a pressure molding method, in which a glass material is heated to about its yield point (At) temperature in a nitrogen atmosphere to soften the glass material, and then pressed by a mold and deformed into its shape. . Since one-shot processing can be performed in a mold without cutting and polishing a complicated aspherical shape, it is attracting attention as a means of saving labor and cost of lens processing. Moreover, there are more than 200 types of optical glass depending on the optical performance such as the refractive index and dispersion, and the sag points are distributed over a wide range of 400 to 750 ° C. Further, from the viewpoint of a glass material that can be press-formed, a wide variety of materials are provided, from electrically insulating materials to conductive materials.

However, the semiconductor integrated circuit technology, in particular, an example in which a low melting point glass flat plate is used as a support substrate is generally used in a semiconductor device using an amorphous silicon semiconductor thin film which can be deposited at a low temperature. However, it has not been applied to the single crystal silicon process whose mainstream is the fabrication of minority carrier devices for the above-mentioned reason.

FIG. 6 shows a general expansion curve of a glass material. When a glass material is heated from room temperature, it expands in a shape close to a straight line, and at a certain temperature, the expansion suddenly increases. This means that the glass transitions from an elastic state to a viscoelastic state, and the intersection of two straight extensions is defined as the transition point (T
g). When the temperature is further increased, the growth stops,
Conversely, it becomes a curve that shrinks. This is due to sagging due to softening of the glass, and this temperature is called the yield point (At).
Above this temperature, the glass can be deformed relatively easily, but deformation may occur due to a compositional change such as recrystallization during cooling or a tensile stress due to a difference in shrinkage and solidification between the surface and the inside. Therefore, pressure forming is performed to compensate for insufficient softening by further applying pressure using a rapid change in elongation in a temperature range from the transition point to the yield point.

As is well known, in a high-temperature silicon process, a thin film of SiO ₂ , BPSG, phosphorus silicate glass (hereinafter, referred to as PSG) or the like as an inorganic passivation material as a final layer is used as a chemical layer.
Examples of deposition and formation by l Vapor Deposition (hereinafter, referred to as CVD) and a method of forming a low melting point glass thin film containing PbO or SiO ₂ as a main component by a glass deposition method have been put to practical use. When a thick film is formed so as to be a supporting substrate, there is a problem that a crack is generated due to a difference in linear expansion coefficient due to heat, and the method is used only for a thin film of about several thousand angstroms.

As a polishing technique that replaces the conventional polishing technique, Mori et al.
n Machining (hereinafter referred to as EEM) method and C
chemical Vaporization Mach
Plasma-Assisted Ch by ining (hereinafter referred to as CVM) method or Bollinger or the like.
A surface processing method such as an electronic etching (hereinafter referred to as PACE) method has been proposed (for the EEM method, Yuzo Mori, et al .: Precision Machinery, Vol. 43, No. 5, p.
p. 20-26, 1977. For the CVM method, Mori
Yuzo, et al .: Proceedings of the Japan Society for Precision Engineering Spring Conference
M23, pp. 517-518, 1991. PASE
As for the law, D. Bollinger and
C. B. Zarowin, "Rapid, Non-me
chemical, Damage Free Figur
ing of Optical Surfaces U
sing Plasma-Assisted Chem
Ial Etching (PACE), "SPIE
Vol. 966, Advances in Fabri
Cation and Metrology for
Optics and Large Optics, P
P. 82-90 (1988)).

The CVM method is a kind of plasma dry etching and has a high pressure S of 1 × 10 ⁵ Pa (Pascal).
In a F ₆ (sulfur hexafluoride) gas atmosphere, a VHF band high frequency of 144 MHz (megahertz) is applied between parallel plate electrodes to generate high-density plasma localized at the cathode electrode,
The workpiece surface is etched away using electrically neutral fluorine radicals. It has been reported that when removing the silicon surface, a processing speed similar to conventional machining can be obtained at a processing speed of 50 μm / min or more, and a surface accuracy of 0.01 μm or more can be obtained.

The conventional polishing has a rough processing accuracy of ± 3 μm, and damage to a processed surface is evaluated by a change in a localized level density distribution using a surface photovoltaic effect (hereinafter referred to as SPV). It is reported that damage such as crystal defects and impurity contamination on the processed surface of the CVM method is as low as that of chemical etching, as compared with that of argon ion sputtering. Moreover, since it is possible to process a large area, it is considered to be an ideal processing method for wafer surface processing.

The EEM method is a processing method utilizing a fluid lubrication phenomenon generated between a low-elastic polyurethane rotating sphere in a suspension and the surface of a workpiece, and powder particles such as ZrO ₂ (zirconium oxide) are used. To the surface of the workpiece,
(Angstrom) A kind of interatomic bond is generated in a very small area in contact with each other, and the surface of the workpiece is removed by an extremely small amount of elastic destruction in atomic units due to the bond. The removal area is moved by NC (Numerica)
(Controlled), processing is performed in a relatively narrow area, but with high accuracy similar to the CVM method.
In addition, in the evaluation by the SPV method, it is possible to perform surface processing while suppressing damage to the level of chemical etching.

[0032]

As described above, although the conventional method has reached a level at which a high-performance semiconductor device characterized by an SOI structure can be manufactured on a trial basis, its productivity is high. It is difficult to evaluate that the method has reached a sufficiently practical level from the viewpoint of manufacturing cost.

For example, even a bonded SOI substrate is expected to be about five times as expensive as silicon wafers currently commercially available. Therefore, for practical use, it is necessary to develop a high-performance semiconductor device having an added value commensurate with the wafer fabrication cost and to reduce the fabrication cost to the level of the current LSI.

In comparison with the above, the DT method is not only advantageous in that a conventional silicon process can be used, but also advantageous in that a semiconductor device can be supported by an inexpensive substrate after element formation.

On the other hand, since a semiconductor device formation surface having a complicated unevenness having a height of several microns and a width of several tens to several hundreds of microns is bonded to a support substrate, the adhesive used is Is required to have a low viscosity before curing as a property for sufficiently filling and flattening. In addition, after curing, it is necessary to compensate for the adhesive strength between the semiconductor device and the supporting substrate when the back surface is removed, and at the same time, to prevent the disconnection of the wiring due to the contraction of the adhesive and the fluctuation of the characteristics of the semiconductor device due to the stress during the curing. Is done.

After the transfer of the semiconductor device to the supporting substrate, it depends on the element structure and the gate length.
When the back surface of the base region is removed, the processing accuracy sensitively affects the operation characteristics of the transistor, for example, the threshold voltage (Vth) and the maximum mutual inductance (gm). The active layer thickness is 0.
It is reported that the effect becomes significant when the thickness is less than 3 microns.

In the final polishing of the silicon wafer, polishing is used to remove the final layer in order to avoid generation of crystal defects in the silicon active layer due to mechanical polishing, but the accuracy is as low as about ± 3 μm. . For this reason, a silicon oxide film etching stop region is formed on a single crystal silicon substrate as proposed by Hamaguchi et al., And high precision is achieved by a selective polishing method based on mechanochemical etching using a polishing cloth and an amine-based etchant together. It is necessary to remove the back surface. However, as described above, there is a problem that damage due to polishing is inevitable.

Conventionally, a method using only chemical etching using a high-concentration impurity layer as an etching stop layer as an etching stop layer by the above-mentioned Nieren, etc. has been studied. This involves the problem of impurity diffusion from the active layer to the active layer.

In the conventional DT method, the transistor layer is supported by the first substrate when the silicon layer on the back surface of the transistor is removed, and after thinning, the transistor layer is removed and adhered to the second support substrate again, so that the process is complicated. Thus, the first support substrate and its adhesive layer are used only in the step of removing the back surface of the transistor, so that unnecessary material consumption is forced.

Therefore, there has been proposed a method in which an SOI structure is formed only by one transfer step, and a back wiring is formed through the LOCOS oxide film. Thereby, the process can be simplified, and at the same time, the back electrode can be formed, and secondary effects such as control of the substrate potential can be expected.

However, since an epoxy-based or polyimide-based adhesive is conventionally used as an adhesive layer with the support substrate, the backside wiring is formed by, for example, sputtering or EB.
It is difficult to use a metal film deposition method that requires substrate heating at 100 ° C. or higher, such as an (electron beam) vapor deposition method, because of problems such as heat resistance and gas release of the adhesive.

In addition, after the single crystal silicon substrate is removed, the back surface of the transistor needs a passivation process to have an SOI structure. The supporting substrate, the adhesive, and the passivation film must be selected from materials and processing conditions that do not affect each other. Therefore, the properties of the adhesive with the support substrate have been an important key in determining the subsequent process conditions, particularly the processing temperature.

Conventionally, when a polymer or wax is used as an adhesive, the same material as the first adhesive is used by forming a structure in which the back surface passivation layer also functions as an adhesive layer with the supporting substrate. However, the first support substrate and the method for removing the adhesive have many restrictions, such as selecting a method that does not adversely affect the passivation effect and the adhesive strength of the second adhesive.

[Object of the Invention] In view of the above-mentioned problems of the prior art, the first object of the present invention is to form a large-scale integrated circuit having a highly reliable SOI structure using a conventional silicon process. I do.

Further, it is a second object of the present invention to simply manufacture the SOI wafer without going through a complicated and large-scale SOI wafer manufacturing process as in the prior art.

Still another object of the present invention is to manufacture a large-scale integrated circuit having an SOI structure at low cost without using an expensive support substrate.

It is another object of the present invention to provide a method for eliminating the adverse effect of an adhesive in the DT method.

[0048]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising:
Forming a semiconductor device on the surface of the single crystal semiconductor substrate;
The device surface is sealed with an impurity barrier layer and thermally softened
The supporting substrate material is pressed with a molding die to
Along the undulations of the surface on which the semiconductor device is formed via an object barrier layer.
By deforming and contacting, and cooling and curing,
Bonding to the surface side of the semiconductor device, and thereafter,
Leave the semiconductor device region on the back side of the semiconductor substrate
To make the semiconductor device thinner,
An electrically insulating material on the exposed back surface of the semiconductor device
Of manufacturing a semiconductor device, characterized by forming a material layer
Act, provide.

Further , the single crystal semiconductor substrate is formed on the surface thereof.
Semiconductor device and impurity burrs formed on the semiconductor device
Arrange multiple chips with the same layer on the same plane,
Press the supporting substrate material softened to
The plurality of chips through the impurity barrier layer.
It is deformed along the undulation of the semiconductor device formation surface and brought into close contact,
Slowly cooling and bonding to the semiconductor device forming surface
Thereby, the plurality of chips are integrally supported, and thereafter,
The back-side portion of each of the single crystal semiconductor substrates is
The semiconductor device area is removed so as to remain, and the respective
The semiconductor device is thinned, and each of the thinned
Form an electrically insulating material layer on the exposed back surface of the semiconductor device
And a method for manufacturing a semiconductor device.
I do.

The portion on the back side of the single crystal semiconductor substrate
After removing the portions, the terminal portions of the plurality of semiconductor devices are exposed.
After connecting the terminals, it is preferable to cover the terminals with an electrical insulating layer.
New

[0051]

Further, the support substrate material is press-moldable.
Glass material that softens when heated
The process is performed at a temperature equal to or higher than the transition point (Tg) of the glass material,
(At) It is preferable to carry out in the following temperature range.

Further, the glass material may include the semiconductor material.
Yield point lower than the irreversible electrical property fluctuation temperature of the body device
It is preferable that the material has a degree.

Further , the electrically insulating material layer is formed by the glass
Deposited or deposited at temperatures below the transition temperature (Tg)
It is preferable to form by making it.

[0055]

According to the semiconductor device and the method of manufacturing the same of the present invention, first, a semiconductor integrated circuit formed on a single crystal silicon wafer by a well-known silicon process, except for external input / output terminals, is used to remove humidity and / or glass material. It is sealed with an inorganic passivation material layer as an impurity barrier layer for preventing diffusion of mobile ions and impurities and stably maintaining its electric operation characteristics.

In the present invention, it is essential that the glass material serving as the support substrate does not have any thermal or mechanical influence on these semiconductor integrated circuits. Therefore, it is preferable that the material softens thermally at a low temperature and that the coefficient of linear expansion in this temperature range is close to the material used for the semiconductor integrated circuit. For example, assuming that the linear expansion coefficient of single-crystal silicon from room temperature to 300 ° C. is 3.8 × 10 ⁻⁶ / ° C., the linear expansion coefficient of the glass material used in the present invention is also of the order of 10 ⁻⁶ / ° C. Is preferred. Most optical glasses satisfy this requirement.

Here, when the semiconductor device is heated to a temperature near the sagging point temperature as the molding temperature of the glass material, a problem is the heat resistance of the metal wiring material.

Aluminum, which is generally used as a wiring material, is a preferable material because of its low electric resistivity. However, when heated to 450 ° C. or more, there is a problem that disconnection due to generation of voids and increase in resistance value due to deposition of silicon. There is. If a glass material whose molding temperature exceeds the composition change temperature of the wiring material is used, a known high melting point metal alloy, such as a molybdenum silicon alloy or a tungsten silicon alloy, which has been developed as a migration countermeasure, is used as the wiring material. It is preferable to use as.

In the present invention, the inorganic passivation material layer is disposed at the interface with the supporting substrate, but is not provided with an adhesive layer or a thick film layer for flattening which requires polishing or the like for the purpose of simplifying the process. And Therefore, the surface on which the semiconductor integrated circuit is formed has an uneven shape of several microns, and it is necessary for the glass material to have a sufficiently low surface viscosity at the time of softening so as to fill and closely adhere to the gap. For the purpose of lowering the surface viscosity, raising the molding temperature to the melting temperature of the glass material causes local recrystallization of the glass material, further expanding the difference in thermal linear expansion coefficient, and regarding the processing conditions. Careful consideration is required.

Further, in the room temperature state after the slow cooling, the semiconductor device plays a role of supporting the semiconductor device, so that it must have excellent mechanical strength. Shape measurement after processing confirms that the glass material is a material that can sufficiently satisfy these requirements, and that there is no void due to water vapor or the like when the glass material is brought into close contact with the mold by heating. In addition, on the contrary, after the curing, the processed surface having the unique uneven shape as in the present invention can be expected to increase the support strength due to the anchor effect.

It is not difficult to imagine a structure in which it is bonded to a flat glass substrate via a flattened low-melting-point glass adhesive layer and is supported, but it is not preferable from the viewpoint of the object of the present invention because the process is complicated.

The next important processing element in the present invention is the step of removing the single crystal silicon substrate on the back surface of the semiconductor device.

For example, in the case of a MOS FET, since the lower part of the channel region is removed, a processing method that does not involve the generation of crystal defects or the influence of impurities in the removing step is premised, as well as the processing accuracy. This is because it is difficult to apply a general gettering process in the high-temperature process after the back surface is removed in the DT method in which the process temperature is gradually lowered as the process proceeds.

Further, since most of the silicon wafers having a thickness of up to 600 microns are removed, the processing speed needs to be as high as that of mechanical processing.

As described above, the removal processing of silicon by the CVM method or the EEM method sufficiently satisfies these requirements.

However, unlike the conventional surface processing for the purpose of only the spatial resolution of the surface, regarding the control of the processing amount, the thickness of the channel region of the MOS FET directly affects the operation characteristics. Measurement of the remaining thickness, that is, the thickness of the channel region, and its feedback to the processing speed are required.

In the present invention, after the shape of the entire workpiece is measured, the processing amount is removed by controlling the processing amount with time at a constant processing speed until the optical film thickness can be measured. Is removed sequentially to the final thickness. This increases the degree of freedom in application to various semiconductor devices as compared with the selective polishing method using a LOCOS oxide film as in the conventional example.

Since it is necessary to seal the back surface of the MOSFET which has been exposed to the air after the removal, as described above, an example in which a thick film made of an organic material is conventionally applied has been used in the present invention. , An inorganic passivation material can be used. Moreover, since all the materials used up to this step have a heat resistance of about 450 ° C., use of an inorganic thin film such as a SiO ₂ film or a Si ₃ N ₄ film using a plasma CVD method or a sputtering method. Can be. When the final step is a passivation treatment step, an organic film may be used.However, when a metal film is further deposited on the passivation film via a contact hole to form a back wiring, problems such as gas generation during metal film deposition are caused. Inorganic films are preferred.

[0069]

【Example】

(Embodiment 1) As an embodiment of a semiconductor device using the present invention, an n-channel MOS FET is manufactured in the order of its manufacturing steps as shown in FIG.
This will be described with reference to FIGS.

FIG. 1A shows a cross-sectional structure of an n-channel MOSFET formed by using a conventional silicon process.

In the figure, a gate oxide film 2 is thermally oxidized (indicated by a mask) on the surface of a p-type Czochralski (hereinafter referred to as CZ) single crystal silicon substrate 9 which has been subjected to intrinsic gettering (hereinafter referred to as IG). Wet oxidation: 10
(00 ° C.).

Next, the mask is removed, phosphorus (P) is ion-implanted from the opening of the oxide film, and an annealing process (800 ° C.) for activation is performed to form an n ⁺ type source region 3 and a drain region 4. . Further, W / W is formed on the source region 3, the drain region 4 and the gate oxide film 2 by sputtering.
A Si alloy laminated film is deposited as a source electrode 5, a drain electrode 6, and a gate electrode 7 and patterned. Finally, an amorphous SiO ₂ film is deposited as a passivation layer by a plasma CVD method to complete the element substrate 9. Although omitted here, a LOCOS oxidized region for element isolation may be formed. External input / output terminals are also formed.

Next, the pressure molding step of the glass material is shown in FIG.
This will be described with reference to FIG.

First, the element substrate 9 is placed on the lower mold 10, and the entire compression molding machine 13 including the upper mold 11 and the body mold 12 is heated to the yield point temperature of the glass material in an atmosphere of nitrogen at atmospheric pressure. deep. Next, SF4 which is a flint optical glass
(Transition point 453 ° C, yield point 477 ° C, coefficient of linear expansion 8.9
The glass block 14 of (× 10 ⁻⁶ / ° C.) is heated in a preheating chamber (not shown) and inserted into the compression molding machine 13. Since the shape of the glass block 14 is processed without melting it, it is preferable that the shape is close to the final shape.

When the temperature of the glass block 14 reaches the sagging point temperature, the upper mold 11 is lowered, the glass block 14 is pressed against the element forming surface of the element substrate 9, and the surface is pressed by pressing. The mold 11 is deformed into a planar shape and an uneven shape on the element formation surface. Here, the surface of the mold is coated with a titanium nitride (TiN) film or the like so that the element forming surface is in close contact with the mold, but not in close contact with the mold, so as to ensure releasability from glass.

Next, as shown in FIG. 1C, the pressure is released, the upper mold 11 is raised, and the DT substrate 15a in which the element substrate 9 is in close contact with and supported by the glass block 14 is taken out. Slowly cool to.

FIG. 1C shows a cross section of a DT substrate 15a in which the element substrate 9 is supported by a glass support substrate 14.

Next, the step of removing the back surface of the element substrate 9 will be described with reference to FIG.

In the figure, a CVM device 16 has a structure in which a cathode electrode plate 17 and an anode electrode plate 18 are arranged in parallel in a container that can withstand a pressure of 1 × 10 ⁵ Pa or more. Ground. On the other hand, the cathode electrode 17 is electrically insulated from the
Hz high frequency power supply 19 via a joining device (not shown).

The DT substrate 15a to be processed is the anode electrode 1
The element substrate 9 is placed on the electrode 8 with the back side facing the cathode electrode 17.

Next, 1 × SF ₆ gas was supplied to the CVM device 16.
Was introduced until a pressure of 10 ⁵ Pa, the RF power is applied to the cathode electrode 17 from the high frequency power source 19, to rise to a high density plasma region 20 to cathode electrode 17 surface by exciting the SF ₆ molecule. Due to the high-pressure atmosphere, the ion species do not reach the processing surface, and only electrically neutral fluorine radicals contribute to silicon etching. Here, the life of the fluorine radical is short due to the high-pressure atmosphere, and contributes to the etching only in the vicinity of the cathode electrode 17. Therefore, only the silicon surface of the DT substrate 15a reacts with the fluorine radical and is removed as SiF ₄ gas. .

The silicon removal region 9a of the DT substrate 15a is uniformly and flatly removed up to the p-type channel region 21 of the MOS FET. Here, as described above, in the final phase of the removal, the removal processing is continued while measuring the silicon layer thickness of the channel region 21 using the optical thickness measurement method, and the thickness of the channel region becomes 0.5 μm. The machining is completed when the process is completed.

Finally, the final passivation step will be described with reference to FIG.

The DT substrate 15a from which the silicon region 9a on the rear surface has been removed is placed in a plasma CVD apparatus (not shown), and a SiH ₄ (silane) gas and an O ₂ (oxygen) gas are introduced thereinto to supply 13.56 MHz high frequency power. To excite and decompose the amorphous SiO ₂ film 22 at a substrate temperature of 300 ° C.
It is deposited on the entire back surface of the T substrate.

Thus, the MOS FE having the SOI structure
The DT substrate 15a on which T is integrated is completed.

In this state, the wafer-shaped DT substrate 15a of the present invention can be cut and divided and handled like a conventional semiconductor chip.

In this embodiment, an n-channel MOS FET is taken as an example of a semiconductor device. However, other than this, for example, a p-channel MOS, a CMOS combining these,
It may be a bipolar transistor, a diode, or the like.

FIG. 2A shows a cross-sectional shape of a bipolar transistor manufactured by using the present invention.

In the figure, a p ⁺ type base region 261, an n ⁺ type emitter region 262, n ⁻ type and n ⁺ type collector regions 263 and 264 have been transferred into the glass support substrate 14, and the collector region 264 has silicon removed. It is exposed to the surface. In this example, element isolation is performed in the LOCOS oxidized region 241, but it is not necessary to perform island isolation.

FIG. 2B shows a cross-sectional shape of a PN diode manufactured by using the present invention.

In the figure, a cathode electrode 271, an anode electrode 272, n-type and n ^- type cathode regions 273 and 274, and p-type and p ^- type anode regions 275 and 276 are transferred to the glass support substrate 14, and n ^The- type cathode region 274 is exposed to the silicon removal surface.

In this embodiment, a glass material is used as an example of a material that can be press-molded. However, since this is a process after completion of a semiconductor device, other dielectric materials may be used if they meet the requirements of the present invention. Materials, conductor materials, materials having excellent thermal conductivity, and materials containing lead and the like, which have an excellent shielding effect against radiation, can also be used.

Further, the method for removing silicon is not limited to the above method, and another method may be used as long as the influence on the semiconductor device can be tolerated. The method of measuring and controlling the processing amount may be a method other than the above example.

(Embodiment 2) In the above-mentioned embodiment 1, the glass support substrate 14 was pressed and adhered to and supported by the wafer-shaped element substrate 9; however, the element substrate 9 was completed in FIG. It is also possible to cut and divide the element substrate 9 into chip shapes later and collectively support a plurality of semiconductor integrated circuit chips having different functions on a glass support substrate.

Therefore, a semiconductor device according to another embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. Here, the semiconductor device manufacturing process is shown in FIG.
The description of the steps is omitted because it is the same as that shown in FIG.

However, the structure is different from the above-mentioned semiconductor device in that it has a LOCOS oxidized region through which backside contact holes 25 and 29 filled with metal wiring reaching the silicon removal surface (FIG. 3). (Illustrated in (A))
Is formed.

As shown in FIG. 3A, a plurality of semiconductor integrated circuit chips having different cut and separated functions and different manufacturing processes,
For example, a CMOS transistor chip (p-channel MOS is omitted in the drawing) 23 and a bipolar transistor chip 24 are arranged on the lower mold 10 in the pressure molding machine 13.

A semiconductor device in which CMOS transistors and bipolar transistors are connected to each other, that is, Bi-CM
OS has recently been receiving attention due to its low power consumption and high speed. However, when two types of transistors are formed over the same substrate, there is a problem in that the structure and the manufacturing process are different, and the process becomes complicated. Therefore, in the present invention, it is possible to manufacture a multifunctional semiconductor device by manufacturing each chip individually, supporting these chips on the same substrate, and connecting wirings.

In the figure, 26 is a base electrode of a bipolar transistor, 27 is an emitter electrode, and 28 is a collector electrode.

As shown in FIG. 3 (B), the glass support substrate 14 is pressed and formed in close contact with the chips 23 and 24 as in the first embodiment. At this time, the height of each chip from the lower mold surface differs depending on the thickness of the silicon wafer, the element structure, the presence or absence of multilayer wiring, and the like. Therefore, FIG.
As shown in (B), the height of the silicon-side surface of the DT substrate 15b in this embodiment is the same, but the depth embedded in the glass support substrate 14 is different.

Back silicon 23a, 2 of DT substrate 15b
In the step of removing 4a, first, as shown in FIG.
Over the entire back surface of the DT substrate 15b, for example, to the surface 30 of the chip 23 where the channel region 21 remains,
And it is removed flat. However, since the required remaining thickness of each semiconductor chip is different, next, silicon is removed from the region of the chip 24 to the remaining surface 31 by using the EEM method. Even when the EEM method is used, the remaining thickness is controlled using an optical thickness measurement method.

By removing the silicon on the back surface, the metal wiring of the back contact hole 25 of each chip is also exposed on the removed surface.

However, not all chips need an SOI structure. For a chip that does not require an SOI structure, the LOCOS oxide layer and the back contact hole 26 may be formed sufficiently deep, and the silicon region may be uniformly removed only by the CVM method until it is exposed.

Next, as shown in FIG. 3D, an amorphous SiO ₂ film is deposited as the back surface passivation film 22, and only the back surface contact holes 25 and 29 are opened using lithography. Further, a metal wiring 32 is deposited and patterned to electrically connect the drain electrode 6 of the MOS transistor and the base electrode 26 of the bipolar transistor. Finally, the final passivation film 3
As No. 3, an amorphous SiO ₂ film is deposited on the entire surface.

As described above, according to the present invention, an IC having an SOI structure having a different function like a conventional hybrid IC is used.
Chips can also be integrated and mounted.

In this embodiment, a semiconductor device other than the above two examples of semiconductor integrated circuit chips may be used.

As for the silicon removing method, a method other than the above may be combined.

[0108] Naturally, the backside wiring process does not limit the scope of the present invention.

Further, a back surface electrode may be formed on the electrically insulating member on the back surface of the semiconductor device to control the substrate potential. (Embodiment 3) Next, a structure made possible by a processing method unique to the present invention will be described with reference to FIGS.

The present embodiment is different from the above-described embodiment in that the upper mold 34 and the lower mold 35 of the pressure molding machine 13 have different shapes.

In general, an IC chip is packaged with a mind that it is directly mounted on a ceramic substrate or the like on which wiring is formed.

Since the present invention is for forming a glass support substrate by pressure, as shown in FIG. 4A, the working surfaces of the molds 34 and 35 of the pressure forming machine 13 are formed into desired shapes, By performing the removal and the passivation processing, the DT substrate 15c as shown in FIG. 4B is completed. However, in this embodiment, the element substrate 9 is cut and separated on the chip before the pressure molding.

Similarly, the above-mentioned mold shape can be set to a structure in which a semiconductor chip to which external lead terminals are attached is collectively supported by a glass support substrate.

(Embodiment 4) Next, a part of the internal structure of a CVM apparatus in a silicon removing step according to the present invention will be described with reference to FIG.

In the present invention, the silicon on the back surface of the semiconductor device must be removed very accurately as described above.

Therefore, in the present invention, the silicon thickness is measured during the processing in addition to the conventional shape measurement before the processing, and the data is fed back to the processing time and processing conditions to improve the processing accuracy. In the figure, a plurality of DT substrates 15 which are workpieces are arranged on a rotatable anode electrode 18, and a cathode electrode 17 fixed to a part of the rotating area is connected to a high frequency power supply 19 and arranged. It is.

Similarly, the DT substrate 15 is provided in a part of the rotation area.
An optical film thickness measuring device 171 movable in the X and Y directions over the entire area of the DT substrate for measuring the silicon thickness of the DT substrate is arranged.

In the processing, first, the silicon of the DT substrate is removed to a thickness where the optical film thickness can be measured immediately below the cathode electrode 17, and the anode electrode 18 is rotated to move the DT substrate sequentially. Next, DT immediately below the optical film thickness measuring device 171
The silicon thickness of the entire substrate is measured, the data is stored in the controller 172, and the data is moved again directly below the cathode electrode 17 to control the processing time and the like based on the data to accurately remove silicon.

In this embodiment, the optical film thickness measuring method is used, but other measuring methods may be used as long as the measuring accuracy is satisfied. Further, other than the rotational movement, there may be a linearly moving body that moves forward and backward, or may have a plurality of removal stages, and the above-described embodiment does not limit the applicable range of the present invention.

[0120]

As described above, according to the present invention,
An advantage is obtained that a high-performance and high-performance semiconductor device can be manufactured by a simple method using a conventional highly reliable silicon process.

Further, since an inexpensive support substrate is used, a semiconductor device having an SOI structure can be manufactured at low cost.

Further, the range of materials that can be used for the supporting substrate can be greatly expanded, and a new function can be provided to the semiconductor device by the material of the supporting substrate.

Further, unlike the conventional DT method, no adhesive is used, so that adverse effects due to the adhesive can be eliminated.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a final form of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view for explaining a step of producing a unique support substrate shape in a pressure forming step according to a third embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device by a conventional device transfer method.

FIG. 6 is a schematic diagram for explaining expansion characteristics of general glass.

FIG. 7 is an internal schematic diagram of a CVM device used in the silicon removing step of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor device region 2 gate oxide film 3 source region 4 drain region 5, 6, 7, 26, 27, 28 electrode 8, 22, 33 passivation film 9 device substrate 10, 11, 34, 35 mold 12 body mold 13 Compression machine 14 Glass support substrate 15 DT substrate 16 CVM device 17 Cathode electrode 18 Anode electrode 19 High frequency power supply 20 Plasma 21 MOS channel region 23, 24 Semiconductor integrated circuit chip 25, 29 Back contact electrode 30, 31 Silicon removal surface 32 Back wiring Reference Signs List 36 silicon substrate 37 epitaxial layer 38 MOS FET 39 wax 40 glass substrate 41 polymer adhesive layer 42 ceramic substrate 171 optical film thickness measuring device 172 controller

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-196264 (JP, A) JP-A-5-152332 (JP, A) JP-A-64-74751 (JP, A) JP-A-5-1995 152476 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 27/12 H01L 21/02 H01L 21/762

Claims (6)

(57) [Claims] In a method of manufacturing a semiconductor device, a semiconductor device is formed on a surface of a single crystal semiconductor substrate, the surface of the semiconductor device is sealed with an impurity barrier layer, and thermally softened .
The supporting lifting the substrate material by pressing in motor Rudo molding die, through said impurity barrier layer in close contact by deforming along the undulations of the forming surface of the semiconductor device, by chill
Bonded to the surface side of the semiconductor device, then, the single crystal
Leave the semiconductor device region on the back side of the semiconductor substrate
To make the semiconductor device thinner,
Forming an electrically insulating material layer on an exposed back surface of the semiconductor device. Wherein the semiconductor <br/> body device formed on a single crystal semiconductor substrate surface, arranging a plurality of chips on the same plane with impurity barrier layer formed on the semiconductor device, the heat the supporting lifting substrate material softened in manner by pressing with motor Rudo molding die,
Through the impurity barrier layer, the plurality of chips are deformed along the undulations of the semiconductor device formation surface of the plurality of chips and brought into close contact with each other, gradually cooled and cured, and joined to the semiconductor device formation surface, thereby bonding the plurality of chips to the semiconductor device formation surface. Integrally support, then it
A portion on the back surface side of each of the single crystal semiconductor substrates is removed so as to leave the semiconductor device region, and the respective semiconductor layers are removed.
Body devices, and each of the thinned semiconductor devices
A method for manufacturing a semiconductor device, comprising: forming an electrically insulating material layer on an exposed back surface of a body device . 3. The method according to claim 1, further comprising the step of :
3. The method of manufacturing a semiconductor device according to claim 2 , wherein after removing, the terminal portions of the plurality of semiconductor devices are exposed, and after connecting the terminals, the terminals are covered with an electrical insulating layer. 4. 4. Before Ki支 lifting the substrate material is a glass material softened by heat can pressing, the bonding step
Is the transition point (Tg) or more of the glass material and the yield point (A)
The method for manufacturing a semiconductor device according to any one of claims 1 to 3, carried out in a temperature range of t) below. 5. The method for manufacturing a semiconductor device according to claim 4 , wherein the glass material is a material having a yield point temperature lower than the irreversible electric characteristic fluctuation temperature of the semiconductor device. Wherein said electrically insulating material layer, Ru deposited or deposited at a temperature transition point below (Tg) of the glass material
The method for manufacturing a semiconductor device according to claim 4 , wherein the semiconductor device is formed by :