KR20030085996A - Method for fabricating wafer - Google Patents
Method for fabricating wafer Download PDFInfo
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- KR20030085996A KR20030085996A KR1020020024328A KR20020024328A KR20030085996A KR 20030085996 A KR20030085996 A KR 20030085996A KR 1020020024328 A KR1020020024328 A KR 1020020024328A KR 20020024328 A KR20020024328 A KR 20020024328A KR 20030085996 A KR20030085996 A KR 20030085996A
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- wafer
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- heat treatment
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- -1 fluorine ions Chemical class 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 238000000137 annealing Methods 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 2
- 238000004064 recycling Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 56
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 229910008045 Si-Si Inorganic materials 0.000 description 2
- 229910006411 Si—Si Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910008284 Si—F Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
본 발명은 웨이퍼의 제조방법에 관한 것으로, 보다 상세하게는 웨이퍼에 이온주입을 통하여 제조공정상의 문제점을 개선시키고 웨이퍼를 재생할 수 있는 웨이퍼의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a wafer, and more particularly, to a method for manufacturing a wafer capable of reproducing a wafer and improving problems in the manufacturing process through ion implantation into the wafer.
반도체 소자의 고성능화가 진행됨에 따라 벌크(bulk) 실리콘으로 이루어진 단결정(single crystal) 실리콘 웨이퍼를 대신하여 지지수단인 베이스(base) 기판과 소자가 형성될 반도체층 사이에 매몰 산화막(buried oxide)이 개재된 실리콘-온-인슐레이터(silicon on insulator:이하, SOI) 웨이퍼를 이용한 반도체 집적기술이 주목되고 있다.As the performance of semiconductor devices increases, buried oxide is interposed between the base substrate, which is a support means, and the semiconductor layer on which the device is to be replaced, instead of a single crystal silicon wafer made of bulk silicon. A semiconductor integrated technology using a silicon on insulator (hereinafter referred to as SOI) wafer is attracting attention.
종래 기술에 있어서는 수소를 이온주입(implantation)시켜 웨이퍼를 절단하거나, 또는 두 개의 웨이퍼를 결합하고 난 후에 어느 하나의 웨이퍼를 백그라인더(back grinder)를 이용하여 그라인딩(grinding)하는 방식 등으로 SOI 웨이퍼를 제조한다.In the prior art, SOI wafers may be cut by wafer implantation by implanting hydrogen, or by grinding two wafers together using a back grinder. To prepare.
상기와 같이 제조된 SOI 웨이퍼에 집적된 반도체 소자는 통상의 단결정 실리콘 웨이퍼에 집적된 반도체 소자에 비해서 접합 용량(junction capacitance)의 감소에 따른 고속화 및 완전한 소자 분리에 따른 래치업(latch up) 감소 등의 장점을 갖는다.The semiconductor device integrated on the SOI wafer manufactured as described above is faster than the semiconductor device integrated on a conventional single crystal silicon wafer, and the latch up is reduced due to the reduction of junction capacitance. Has the advantage of.
그러나, 종래 기술에 따른 웨이퍼의 제조방법에 있어서는 다음과 같은 문제점이 있다.However, there is the following problem in the wafer manufacturing method according to the prior art.
종래 기술에 있어서, 수소 이온을 주입하여 웨이퍼를 절단하는 제조방법은 폭발의 위험이 높은 수소를 사용하며 약 1.000℃ 이상의 고온에서 장시간 열처리(annealing)를 하여야 한다는 문제점이 있다. 또한, 두 개의 웨이퍼를 결합하여 그라인딩 하는 제조방법에 있어서는 어느 하나의 웨이퍼를 완전히 연마하여야 하기 때문에 제조원가가 높다는 문제점이 있다.In the prior art, a manufacturing method of cutting a wafer by injecting hydrogen ions has a problem of using hydrogen having a high risk of explosion and performing annealing at a high temperature of about 1.000 ° C or longer. In addition, in the manufacturing method of bonding and grinding two wafers, there is a problem in that manufacturing cost is high because one wafer must be completely polished.
이에, 본 발명은 종래 기술에 따른 제반 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 실리콘 웨이퍼에 불소 이온 주입 공정을 적용하여 열처리 온도을 낮추어 공정을 단순화시키고 웨이퍼를 재생하여 사용할 수 있는 웨이퍼의 제조방법을 제공함에 있다.Accordingly, the present invention has been made in order to solve various problems according to the prior art, an object of the present invention is to apply a fluorine ion implantation process to a silicon wafer to lower the heat treatment temperature to simplify the process and to reclaim the wafer To provide a manufacturing method.
도 1 내지 도 5는 본 발명에 따른 웨이퍼의 제조방법을 설명하기 위한 공정별 단면도.1 to 5 are cross-sectional views for each process for explaining a method for manufacturing a wafer according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10; 제1웨이퍼12; 절연막10; First wafer 12; Insulating film
14,14a,22; 실리콘층20; 제2웨이퍼14,14a, 22; Silicon layer 20; 2nd wafer
상기한 목적을 달성하기 위한 본 발명에 따른 웨이퍼의 제조방법은, 반도체 원소로 구성된 제1웨이퍼와 제2웨이퍼를 준비하는 단계; 상기 제1웨이퍼 상면에는 절연막을 형성하고, 상기 제2웨이퍼 상면에는 소정의 이온을 주입하는 단계; 상기 제1웨이퍼와 제2웨이퍼를 접합한 후 제1열처리하여 상기 제1웨이퍼와 제2웨이퍼를 분리하는 단계; 및 상기 분리된 제1웨이퍼와 제2웨이퍼 상면 각각을 화학기계적 연마와 제2열처리하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a wafer, the method including: preparing a first wafer and a second wafer made of a semiconductor element; Forming an insulating film on the upper surface of the first wafer and implanting predetermined ions into the upper surface of the second wafer; Bonding the first wafer and the second wafer to separate the first wafer and the second wafer by first heat treatment; And chemical mechanical polishing and second heat treatment of the separated first and second wafers, respectively.
이하, 본 발명에 따른 웨이퍼의 제조방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a wafer according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명에 따른 웨이퍼의 제조방법을 설명하기 위한 공정별 단면도이다.1 to 5 are cross-sectional views for each process for explaining a method of manufacturing a wafer according to the present invention.
본 발명에 따른 웨이퍼의 제조방법은, 도 1에 도시된 바와 같이, 먼저 반도체 원소, 예를 들어, 실리콘(Si)으로 구성된 제1웨이퍼(10;wafer)와 제2웨이퍼(20)를 준비한다. 이중 제1웨이퍼(10) 상면에 절연막(12;insulator layer)을 약 1,000 ~ 2,000Å 두께로 성장시킨다.In the method of manufacturing a wafer according to the present invention, as shown in FIG. 1, first, a first wafer 10 and a second wafer 20 made of a semiconductor element, for example, silicon (Si) are prepared. . An insulating layer 12 is grown on the upper surface of the first wafer 10 to a thickness of about 1,000 to 2,000 Å.
또한, 상기 절연막(12) 형성 단계와 병행하여 소정의 이온, 예를 들어, 약 2.0 ×1018이온수/cm2이상의 불소(Fluorine) 이온을 약 150 ~ 250 keV의 에너지를 사용하여 제2웨이퍼(20) 상면으로부터 약 2.000Å 깊이로 이온주입(implantation) 공정을 진행한다.In addition, in parallel with the step of forming the insulating layer 12, a second ion may be formed by using predetermined ions, for example, about 2.0 × 10 18 ions / cm 2 or more of fluorine ions using energy of about 150 to 250 keV. 20) An implantation process is performed at a depth of about 2.000 mm from the top surface.
이어서, 도 2에 도시된 바와 같이, 상기 제1웨이퍼(10)와 제2웨이퍼(20)를세정(cleaning)한 후에 접합시킨다. 이때, 결합되는 에너지는 판 데르 발스(Van der Waals) 힘을 이용하게 되는데, 상기 제1웨이퍼(10) 및 제2웨이퍼(20)를 접합할 때의 분위기(atmosphere)는 1 Torr 이하의 진공 상태에서 진행한다. 또한, 상기 제1웨이퍼(10)와 제2웨이퍼(20)를 약 100 MPa 이상의 압력을 가한다.Subsequently, as shown in FIG. 2, the first wafer 10 and the second wafer 20 are cleaned and bonded. At this time, the combined energy is used to van der Waals (Van der Waals) force, the atmosphere (atmosphere) when joining the first wafer 10 and the second wafer 20 is a vacuum state of 1 Torr or less Proceed from In addition, the first wafer 10 and the second wafer 20 are applied with a pressure of about 100 MPa or more.
그다음, 도 3에 도시된 바와 같이, 상기 접합된 제1웨이퍼(10)와 제2웨이퍼(20)를 약 700℃ 이상의 온도에서 약 1시간 이상 동안 질소(N2) 분위기에서 제1열처리 공정을 진행하여 주입된 불소 이온(F+) 들이 실리콘(Si)과 실리콘(Si)간의 결합(Si-Si)을 끊고 실리콘(Si)과 결합(Si-F)을 하게 된다.Next, as shown in FIG. 3, the bonded first wafer 10 and the second wafer 20 are subjected to a first heat treatment process in a nitrogen (N 2 ) atmosphere for about 1 hour or more at a temperature of about 700 ° C. or more. The fluorine ions (F + ) implanted in the process break the bond (Si-Si) between silicon (Si) and silicon (Si) and combine with silicon (Si).
그결과, 도 4에 도시된 바와 같이, 상기 Si-F 결합들이 모여 휘발성 물질인 SiF4를 형성하게 되고, 상기 SiF4가 휘발되려는 성질과 Si-Si 결합의 파괴에 의하여 이온 주입된 부분이 둘(14)(22)로 나뉘어지게 된다. 이때, 상기 제1웨이퍼(10)와 제2웨이퍼(20)도 둘로 나뉘게 됨은 물론이다.As a result, as shown in FIG. 4, the Si-F bonds are gathered to form a volatile SiF 4 , and the portion to which the SiF 4 is volatilized and the ion implanted by the destruction of the Si-Si bond are divided into two. It is divided into (14) and (22). At this time, of course, the first wafer 10 and the second wafer 20 are also divided into two.
그다음, 도 5에 도시된 바와 같이, 상기 분리된 제1웨이퍼(10)의 상면(14)과 제2웨이퍼(20)의 상면(22)의 조도(roughness)를 제곱 평균(root mean square)이 1.5Å 이하로 되도록 조절하기 위해 최소한 100Å 이상의 두께를 화학기계적 연마(CMP) 한다. 그런다음, 상기 제1웨이퍼(10)와 제2웨이퍼(20) 표면에 발생한 결함(defect)을 제거하기 위하여 약 800℃ 이상의 온도에서 제2열처리 공정을 진행한다.Next, as shown in FIG. 5, the root mean square of the roughness of the upper surface 14 of the separated first wafer 10 and the upper surface 22 of the second wafer 20 is determined. Chemical mechanical polishing (CMP) of a thickness of at least 100 kPa is used to adjust to less than 1.5 kPa. Then, a second heat treatment process is performed at a temperature of about 800 ° C. or more to remove defects occurring on the surfaces of the first wafer 10 and the second wafer 20.
그결과, 절연막(12)상에 실리콘층(14a)이 형성된 웨이퍼(10), 즉 SOI 웨이퍼가 완성된다. 한편, 상기 제2웨이퍼(20)를 다시 화학기계적연마 공정을 진행하여 표면 조도(surface roughness)를 개선시켜 재사용이 가능하도록 할 수 있다.As a result, the wafer 10 in which the silicon layer 14a is formed on the insulating film 12, that is, the SOI wafer is completed. Meanwhile, the second wafer 20 may be subjected to a chemical mechanical polishing process again to improve surface roughness and to reuse the second wafer 20.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.
이상에서 살펴 본 바와 같이, 본 발명에 따른 웨이퍼의 제조방법에 의하면 웨이퍼를 재생하여 사용할 수 있어 제조원가를 절감할 수 있고, 열처리 온도를 낮추어 제조공정을 단순화 시킬 수 있는 효과가 있다.As described above, according to the method for manufacturing a wafer according to the present invention, the wafer can be regenerated and used, thereby reducing manufacturing costs and reducing the heat treatment temperature, thereby simplifying the manufacturing process.
Claims (7)
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| KR10-2002-0024328A KR100465630B1 (en) | 2002-05-03 | 2002-05-03 | Method for fabricating wafer |
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| KR10-2002-0024328A KR100465630B1 (en) | 2002-05-03 | 2002-05-03 | Method for fabricating wafer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101144842B1 (en) * | 2010-06-08 | 2012-05-14 | 삼성코닝정밀소재 주식회사 | Method for producing bonded substrates |
| KR101400699B1 (en) * | 2007-05-18 | 2014-05-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor substrate, semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3250722B2 (en) * | 1995-12-12 | 2002-01-28 | キヤノン株式会社 | Method and apparatus for manufacturing SOI substrate |
| FR2748850B1 (en) * | 1996-05-15 | 1998-07-24 | Commissariat Energie Atomique | PROCESS FOR MAKING A THIN FILM OF SOLID MATERIAL AND APPLICATIONS OF THIS PROCESS |
| KR100232886B1 (en) * | 1996-11-23 | 1999-12-01 | 김영환 | Soi wafer fabricating method |
| JP3395661B2 (en) * | 1998-07-07 | 2003-04-14 | 信越半導体株式会社 | Method for manufacturing SOI wafer |
| KR100549258B1 (en) * | 2000-06-02 | 2006-02-03 | 주식회사 실트론 | Method for manufacturing silicon on insulator wafer |
| KR20020002998A (en) * | 2000-06-30 | 2002-01-10 | 박종섭 | Method for making a soi silicon wafer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101400699B1 (en) * | 2007-05-18 | 2014-05-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor substrate, semiconductor device and manufacturing method thereof |
| KR101144842B1 (en) * | 2010-06-08 | 2012-05-14 | 삼성코닝정밀소재 주식회사 | Method for producing bonded substrates |
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| KR100465630B1 (en) | 2005-01-13 |
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