JP3281454B2 - Imaging recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording apparatus,
For example, it is suitable for use in an imaging and recording device that performs digital signal processing.

[0002]

2. Description of the Related Art There have been proposed many image pickup recording apparatuses for processing an output signal of an image pickup device such as a CCD to obtain a video signal, and recording and reproducing the video signal on a video tape. Of these imaging and recording devices, especially in recent years,
Many systems using a high-speed analog-digital converter (hereinafter, AD converter) and a digital-analog converter (hereinafter, DA converter) have been proposed.

[0003] In the above-mentioned imaging and recording apparatus, a video signal obtained from an imaging signal is converted into a digital signal by an AD converter, and then digitally modulated and recorded on a magnetic tape. Also,
The signal reproduced from the magnetic tape is digitally demodulated, converted into an analog signal using the digital reproduced video signal, and output.

[0004] In addition, an image pickup video signal is converted by using a field memory, a line memory, a digital arithmetic circuit, or the like.
Methods for performing special effects such as enlargement / reduction of images, still photography, intermittent photography, and conversion of colors and gradations have also been proposed.

[0005]

However, in these conventional imaging / recording apparatuses using the digital signal processing system, the imaging signal processing circuit performs analog processing, and the output of the analog processing circuit is converted into a digital-to-analog signal. It was a method to do. Therefore, there is a problem that the number of components increases due to a large circuit scale, and current consumption increases. Also, the device cannot be downsized,
Another problem is that the cost cannot be reduced.

Further, since the analog signal processing circuit and the digital signal processing circuit coexist, the S / N ratio cannot be sufficiently obtained or the size cannot be reduced due to interference such as mixing of the digital signal into the analog signal. There was also.

In addition, since the image signal processing circuit performs analog processing, the image quality is determined by the performance of the analog circuit, such as frequency characteristics, noise characteristics, temperature changes, and variations in characteristics of each circuit. Was difficult.

Further, in order to perform a special effect using a frame memory or a digital operation, more circuits are required, making it difficult to reduce the size of the device and increasing power consumption.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to simplify the circuit configuration of an apparatus for recording an image signal digitally.

[0010]

According to the present invention, there is provided an imaging and recording apparatus comprising: an imaging means for imaging an object to form an image signal; and a recording means for recording the image signal formed by the imaging means. Electronic zoom means for electronically enlarging or reducing an image formed by the imaging means, and zoom magnification signal input means for inputting a zoom magnification signal for changing the electronic zoom magnification in the electronic zoom means. , A first for driving the imaging means.
A first clock generating means for generating a second clock; a second clock generating means for generating a second clock for driving the recording means at a different frequency from the first clock; And a calculating means for correcting the zoom magnification signal according to the ratio of the second clock to the second clock.

Another feature of the present invention is that
A conversion ratio between the clock rates of the first clock and the second clock and the zoom magnification can be independently changed. According to another feature of the present invention, the input side of the electronic zoom unit is driven by the first clock, and the output side of the electronic zoom unit is driven by the second clock. And Another feature of the present invention is that the electronic zoom means has a switching means for switching to either an image signal formed by the imaging means or an external input signal inputted from outside. It is characterized by:

[0012]

Since the imaging and recording apparatus of the present invention is provided with arithmetic means for correcting the zoom magnification signal in accordance with the ratio between the first clock and the second clock, the clock rate for imaging and the recording rate for recording are provided. Can be simultaneously performed.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an imaging and recording apparatus according to the present invention. FIG. 1 is a configuration diagram of the imaging recording apparatus of the present embodiment. In FIG. 1, reference numeral 1 denotes an imaging lens, which includes an aperture and an optical filter.

Reference numeral 2 denotes a CCD which is a color image pickup device, and reference numeral 3 denotes a camera timing generator for generating timing pulses required for the CCD 2 and a signal processing circuit to be described later. Reference numeral 4 denotes a sample and hold for making the output of the CCD 2 continuous.

Next, 5, 13, 15, and 16 are AD converters, 6 is a camera signal processing circuit, and a filter,
Performs digital separation such as color separation, gamma, gain adjustment, and clipping. Reference numeral 7 denotes an electronic zoom circuit for enlarging or reducing an image using a memory, 8 denotes an external video signal input terminal of Y (luminance) and C (color) separation type, and 9 denotes an external video input terminal of a composite video signal.

Reference numeral 10 denotes a YC separation circuit for extracting a Y signal and a C signal from the input composite video signal. 11 and 12 are YC
A switch circuit for switching the type of an external input signal in accordance with a switching signal for a separation (S) signal / composite (CO) signal;
Reference numeral 4 denotes a color demodulation circuit for separating and demodulating the color difference signals RY and BY from the input C signal.

Reference numeral 17 denotes a zoom terminal for inputting a zoom signal ZOOM; 18, 19, and 20 switch circuits for switching the type of input signal in accordance with a CAMERA (image pickup signal) / LINE (external input) switching signal; It is a digital recorder circuit that performs signal processing such as data compression, expansion, digital modulation, and demodulation.

Reference numeral 22 denotes a recording / reproducing head, 23 denotes a digital video tape, and 24, 25 and 26 denote REC (recording) / P.
A switch circuit for switching the type of output signal in response to a B (reproduction) switching signal; 28, 29, and 30 are DA converters; 31, 32, and 33 are low-pass filters; and 34 is input with color difference signals RY and BY. , A color modulation for outputting a modulated color signal C; and 35, a YC separation type video output terminal.

The imaging and recording apparatus according to the present embodiment having the above-described configuration has switches 18, 19, 20, and 24 in accordance with CAMERA / LINE and REC / PB signals generated by control signals (not shown) in FIG. , 25 and 26 are switched, so that camera recording can be roughly divided,
There are three operation modes of external input recording and reproduction. The operation in each of these modes will be described sequentially.

First, the camera recording mode will be described. In this case, the switches 18, 19 and 20 are set to CAMER
A (C) side and switches 24, 25, 26
It is connected to the EC (R) side.

The subject image formed on the image pickup surface of the CCD 2 by the image pickup lens 1 is photoelectrically converted into an electric signal here. The electric signal is sequentially read out in accordance with a drive signal generated by the camera timing generator 3 and imaged. Signal. Then, the signal is made continuous by the sample-and-hold circuit 4 and converted into a digital image signal by the AD converter 5.

Next, in the camera signal processing 6, the luminance signal Y and the color difference signals RY and BY are obtained through signal processing such as filtering, color separation, gamma adjustment, and clipping as described above. These signals are then input to the electronic zoom circuit 7 and the zoom signal ZOOM input from the zoom terminal 17
The enlargement process or the reduction process is performed at a magnification according to the following, and then input to the digital recorder circuit 21 via the switches 18, 19, and 20.

The digital recorder circuit 21 performs processes such as data compression and digital modulation. Then, the digital recording signal of the output is transmitted to the magnetic head 22.
Is recorded on the digital video tape 23 via the.
The outputs of the switches 18, 19 and 20 are connected to the switch 2
DA converter 2 via each of 4, 25 and 26
8, 29, 30 and these DA converters 2
The digital-to-analog conversion is performed by 8, 29, and 30, respectively.

The D / A converted switches 18, 1
The outputs of 9 and 20 are then passed to low-pass filters 31 and 3
2, 33, where the low-frequency signal is extracted.
Then, the output of the low-pass filter 31 is directly output as a luminance (Y) signal from the output terminal 35 to an external device such as a television monitor (not shown) as a monitor signal.

The outputs of the low-pass filters 32 and 33 are balanced-modulated by a color subcarrier in a color modulation circuit 34 to become a chrominance signal C, which is output from an output terminal 35 together with the aforementioned Y signal. The electronic zoom circuit 7 receives synchronization signals HD and VD generated by the camera timing generator 3, and the electronic zoom circuit 7 operates in synchronization with these signals.

At this time, the CCD 2, the sample-and-hold circuit 4, the AD converter 5, and the camera signal processing circuit 6 include a camera clock (hereinafter referred to as CCLK) generated by the camera timing generator 3 as a clock signal for performing the operation of each section. ) Is used.

In the electronic zoom circuit 7, CCLK is used in the first half of the circuit, and a recorder clock (hereinafter, RCLK) generated by the digital recorder circuit 21 in the middle.
And the clock rate is converted at the joint. Further, the digital recorder circuit 21,
The DA converters 28, 29, 30 use RCLK.

As described above, the difference between the clocks is that
D2 is a reference clock frequency corresponding to the number of pixels of the CCD (for example, 10 MHZ for a CCD having 250,000 pixels).
z, about 14MHZ for CCD with 380,000 pixels
z), and the digital recorder 21 uses a reference clock frequency (for example, 13.5 MHz) determined from its recording format.

Therefore, in this case, the clock frequency must be converted between the two. By the way, when the clock frequency is converted, as shown in FIG. 1, if the frequency is converted in the electronic zoom circuit 7, the memory and the interpolation circuit in the electronic zoom circuit can be shared, thereby simplifying the configuration of the entire apparatus. can do.

Next, the external input recording mode will be described. In this case, the switches 18, 19 and 20 are set to LINE
(L) side, and switches 24, 25, 26
It is connected to the C (R) side.

When the external input signal is a YC separated signal, S
The Y signal input from the input terminal 8 and passed through the switch circuits 11 and 12 is given to the AD converter 13 to be A / D converted and become a digital Y signal.

The C signal is supplied to a color demodulation circuit 14 where the C signal is color-demodulated to be color difference signals RY and BY. Then, the AD converters 15 and 16 respectively
It is converted to digital color difference signals RY and BY.

When the external signal is the composite video signal CO, the composite signal is input from the external input terminal 9 of the composite signal. Then, the signal is separated into a Y signal and a C signal by the YC separation circuit 10, and the color demodulation circuit 14 via the switches 11 and 12.
The A / D converters 13, 15, and 16 convert the signals into digital Y signals and digital color difference signals RY and BY in the same manner as described above.

These signals are supplied to the switch circuits 18, 1
The digital video tape 2 is input to the digital recorder circuit 21 via the magnetic heads 9 and 20 and passes through the magnetic head 22.
3 recorded. The outputs of the switches 18, 19, and 20 are output as monitor signals from the video signal output terminal 35, as in the case of the camera recording mode.

At this time, the clock signals for performing the operation of each part include the AD converters 13, 15, 16 and the digital recorder circuit 21, the DA converters 28,
Reference numerals 9 and 30 use RCLK.

As described above, the digital recorder 21
Uses a reference clock frequency determined by its recording format, so that the AD converters 13, 15, and 16 are also operated using the clock to simplify the entire apparatus.

Next, the reproduction mode will be described. In this case, the switches 24, 25, 26 are connected to the PB (P) side. The digital video signal recorded on the digital video tape 23 is converted into an electric signal reproduced by the magnetic head 22. The digital video signals Y and R are supplied to a digital recorder circuit 21 where digital demodulation and data expansion are performed.
-Y and BY are generated.

These signals are supplied to switches 24, 25, 2
6 are output as monitor signals from the video signal output terminal 35 in the same manner as in the two modes described above. At this time, the digital recorder circuit 21, the DA converter 2
8, 29 and 30 use RCLK.

In this embodiment, the camera signal processing system is CC
Since operation is performed using a clock that is optimal for D and its processing system, a high-quality signal can be obtained. Further, since the processing system of the external input signal directly uses the clock of the digital recorder, the circuit configuration can be simplified. In particular, even if there is a temporal change component (jitter) in the synchronization signal of the external signal, the influence can be minimized.

FIG. 2 is a detailed example of the electronic zoom circuit 7 in the embodiment shown in FIG. In FIG.
8 is an input terminal, 109 is a coefficient unit, 110 is a multiplier, 11
Reference numeral 1 denotes a control circuit; 112, a zoom processing circuit for enlarging one signal; 113, a field memory for storing image signals for one vertical period; 114, a line memory for storing image signals for one horizontal period; Reference numeral 116 denotes a flip-flop (FF) that delays an image signal for one pixel. 117, 118, 119 and 120 are multipliers, 12
1, 122 and 123 are adders, 126, 127 and 128
Is an output terminal.

The zoom processing circuits 124 and 125 are the same as the zoom processing circuit 112, but their illustration is omitted for the sake of simplicity. Note that among the signals, the image signal has a signal line having a data width of, for example, 8 bits, but is represented by a single line for simplification of description.

The zoom signal ZOOM input from the zoom signal input terminal 102 is input to the control circuit 111 as a vertical zoom coefficient VZOOM, and a multiplier 110
Is input to

The coefficient signal from the coefficient unit 109 is input to the other input terminal of the multiplier 110. Coefficient unit 10
Reference numeral 9 is written with the frequency FCCLK of CCLK given from the camera timing generator 3 in FIG. 1 and the ratio FRCLK / FCCLK of the frequency FRCLK of RCLK given from the digital recorder circuit 21. Is output from the multiplier 110 and input to the control circuit 111 as the horizontal zoom coefficient HZOOM.

In the control circuit 111, the input HD, V
D, RCK to find the position on the screen, HZOOM, V
The ZOOM generates interpolation coefficients X1, X2, X3, X4, a horizontal clock enable signal CE, and a readout horizontal synchronization signal RHD, and controls the operation of the zoom processing circuit 7 using these signals.

The luminance signal Y input from the Y input terminal 103 is input to the zoom processing circuit 112. First, a signal for one vertical period is stored in the field memory 113.
The field memory 113 is a type of memory called a dual-port memory. The field memory 113 synchronizes with a write-side clock WCK, a horizontal synchronization signal HD, a vertical synchronization signal VD, and a horizontal synchronization enable signal WHC to input an image signal DI.
N and the clock RCK on the read side,
When the horizontal synchronization enable signal RHC and the clock enable signal RCE are input, the output image signal D corresponding to these is output.
OUT is obtained. The output is input to the data input DIN of the line memory 114.

The line memory 114 stores the horizontal synchronizing signal H
D, the input signal is stored according to the clock enable signal CE, and is output from DOUT. The output signal of the field memory 113 and the output signal of the line memory 114 are input to multipliers 117 and 119, respectively, and are also flip-flops 115 and 116, respectively.
Are delayed by one pixel, and their outputs are
8, 120.

The other inputs of the multipliers 117, 118, 119, 120 are provided with outputs X 1, X 2, X
Signals 3 and X4 are input, respectively, and the signals multiplied by their outputs are summed and added by adders 121, 122 and 123 to become a Y output signal YOUT, which is output from a Y output terminal 126.

The color difference signals RY and BY are supplied to the input terminal 10.
7 and 108, are processed by the zoom processing circuits 124 and 125 in the same manner as the above-described Y signal, and are output from the color difference output terminals 127 and 128, respectively.

Next, the details of this operation will be described. In addition,
For simplicity, the operation of the Y signal system when the coefficient unit 109 is 1 and the zoom signal ZOOM is 2 will be described.
The output RHC of the control circuit 111 occurs once every two horizontal periods 2H, and the field memory 113 outputs a signal of the same horizontal line over two horizontal periods.

Further, the horizontal clock enable signal RC
Since E is generated once every RCLK2 clock,
The same output is obtained for each output two pixels. Further, a signal obtained by delaying each line by one horizontal period is obtained from the line memory 114.

From the flip-flops 115 and 116, a signal obtained by delaying them by one horizontal pixel is obtained, so that the multipliers 117 to 120 supply the current pixel P (x, y) to the multipliers 117 to 120.
P (x-1, y), upper P (x, y-1), upper left P
Signals of four pixels adjacent to (x-1, y-1) are obtained every two clock periods.

The other inputs of the multipliers 117 to 120 are as follows: X1 = 0, X2 = 0, X3 = 0, X4 = 1 in the first clock of the two clock periods, and the upper left pixel of the current pixel Is extracted.

In the next clock, X1 = 0, X2 = 0, X3 = 0.5, X4 = 0.
5 and the average value of the upper left and upper pixels is extracted.

In the next horizontal period, as described above, R
Since HC is not output, the same pixel signal is obtained at the same horizontal position as described above. Therefore, the multiplier 1
17 to 120, the same signal as the previous line is input in the same manner as the previous line for each RCLK2 clock period.

At this time, the other inputs of the multipliers 117 to 120 are: X1 = 0, X2 = 0.5, X3 = 0, X4 = 0.
5. The signal of the average value of the upper left pixel and the left pixel of the current pixel is extracted.

In the next clock, X1 = 0.25, X2 = 0.25, X3 = 0.2
5, X4 = 0.25, and the average value of the four pixels of the upper left, upper, left, and current pixels is extracted.

In this way, the signal between the pixels is obtained by the primary interpolation, and the image is enlarged twice. When the value of the zoom signal ZOOM is other than 2 or when the value of the coefficient unit 109 is not 1, VZOOM and HZOO of the control circuit are used.
Although a value different from that described above is input to M, the input signal is output from the output of the adder 123 in the horizontal direction similarly to the above-described operation.
An image which is magnified ZOOM times and VZOOM times in the vertical direction and primary-interpolated is obtained.

The zoom processing circuits 124 and 125 convert the color difference signals RY and BY into a zoom signal ZO
According to M and the output of the coefficient unit 109, an image enlarged in the horizontal and vertical directions is obtained. In this example, since the enlargement of the image and the conversion of the clock rate are performed by the primary interpolation correction, the deterioration of the image due to the processing can be minimized. In addition, since the conversion ratio of the clock rate and the zoom ratio can be given independently, when using different clock rates, only the conversion ratio of the clock rate needs to be changed, and the circuit does not need to be changed.

FIG. 3 is a detailed diagram showing a second example of the electronic zoom circuit 7 shown in the embodiment of the present invention. The same or corresponding parts as those in the previous figures are denoted by the same reference numerals. In FIG. 3, reference numerals 130 and 131 denote frame memories similar to 113.

The control circuit 111 receives a zoom signal ZOOM as input to CZO and VZOOM as in FIG.
A value obtained by multiplying the output of the coefficient unit 109 by the multiplier 110 to the zoom signal ZOOM is input to HZOOM.

The output WHC of the control circuit 111 is a write horizontal synchronizing signal enable of the frame memories 113, 130 and 131, and WCE is the frame memory 113, 13
Write clock enable signals 0 and 131 are input to the respective frame memories and control these operations.

Next, the operation of this example will be described. For simplicity, the operation of the Y signal system when the output of the coefficient unit 109 is 1 and the zoom signal ZOOM is 0.5 will be described.

The output WHC of the control circuit 111 occurs once every two horizontal periods 2H.
A signal is written at the same horizontal line position over the horizontal period. Further, the write clock enable signal W
Since CE is generated once every two CCLK clocks, it is written in the same position by two input pixels.

On the read side, the horizontal synchronization signal HD is input to the read horizontal synchronization enable and the RCLK is input to the read clock, so that the input image is reduced horizontally and vertically by 画像. Is read. In this way, the image of each pixel is reduced to 1/2 by thinning out the signal of each pixel to 1/2.

When the value of the zoom signal ZOOM is other than 0.5 or when the output value of the coefficient unit 109 is not 1,
A value different from that described above is input to VZOOM and HZOOM of the control circuit.
From the output of No. 3, an image obtained by reducing the input signal by HZOOM times in the horizontal direction and by VZOOM times in the vertical direction is obtained.

In the frame memories 130 and 131, images obtained by reducing the color difference signals RY and BY in the horizontal and vertical directions according to the output of the ZOOM and the coefficient unit 109 are obtained in the same manner as described above. In this case, since the image can be enlarged and the clock rate can be converted without providing any external circuit in addition to the frame memory, the mounting area, power consumption, and cost can be reduced.

The circuits shown in FIGS. 2 and 3 are examples in which the image is enlarged and reduced, respectively. However, by combining these to switch the operation by a switch, the reduction and enlargement can be performed by a single circuit. It is easy to make the configuration feasible. In this case, if the control circuit and the field memory are configured to be commonly used for enlargement and reduction, FIG.
Since it is only necessary to add a switch circuit to the above circuit, the increase in the circuit is small.

Further, by adding means for controlling the writing and reading operations of the field memory used here, it is easy to realize a special effect such as a still or a strobe.

FIG. 4 is a block diagram showing a second embodiment of the present invention. The same or corresponding parts as those in the previous figures are denoted by the same reference numerals. In FIG. 4, reference numeral 201 denotes an AGC circuit for varying the gain of an input signal, and reference numeral 202 denotes a synchronization separation circuit, which separates a synchronization signal from a digital Y signal with a synchronization signal to be input, and a clock synchronized with the synchronization signal. LCLK
Is to be generated.

The switches 203 and 204 have the same S / S
A switch circuit for selecting an input signal in accordance with a switching signal of CO, 205 is a switch circuit similar to switches 18, 19 and 20.
This is a switch circuit that switches the input according to the / L switching signal. The YC separation 10 and the color demodulation circuit 14
Is configured to handle digital signals, unlike the case of FIG.

In FIG. 2, a CAMERA / LINE signal and REC /
Switches 18, 19, 20, 24, 2 according to the PB signal
By switching between 5 and 26, the operation is performed in three operation modes of camera recording, external input recording, and reproduction roughly as in FIG. Next, the operation in each of these modes will be sequentially described.

First, the camera recording mode will be described. In this case, switches 18, 19, 10, and 205 are C
Connected to the AMERA (C) side, switches 24, 25,
Reference numeral 26 is connected to the REC (R) side.

The operation from the lens 1 to the camera signal processing circuit 6 is the same as that of the circuit shown in FIG. The luminance signal Y, color difference signals RY and B- of the output of the camera signal processing circuit 6
Y is input to the electronic zoom 7 via the switch circuits 18, 19, 20. At this time, the CCLK generated from the camera timing generator 3 is input to the electronic zoom circuit 7 via the switch 205.

The electronic zoom circuit 7 performs enlargement processing or reduction processing at a magnification corresponding to the zoom signal input from the zoom terminal 17 as in the case of FIG. The clock rate conversion is performed at the joint using the RCLK generated by the digital recorder circuit 21 from. The output is input to the digital recorder circuit 21 in the same manner as described above, and operates in the same manner as in the case of FIG.

Next, the external input recording mode will be described. In this case, the switches 18, 19, 20, and 205 are L
The switches 24, 25, 26 are connected to the INE (L) side.
Are connected to the REC (R) side.

If the external input signal is a YC separation signal, S
The Y signal input from the input terminal 8 passes through the switch circuit 11, and the AGC circuit 201 adjusts the signal level so that the synchronization signal portion becomes a predetermined level in accordance with a synchronization signal SYNC to be described later. Are AD converted by the AD converter 13.

The digital Y signal output from the AD converter 13 is first input to the electronic zoom circuit 7 via the switch circuits 203 and 18. Further, the digital Y signal is input to the sync separator 202, and a sync signal SYNC and an external input clock LCLK synchronized with the sync signal SYNC are generated.

The external input clock LCLK is generated by a phase locked loop (PLL) or the like so as to have a frequency equal to an integer multiple of the horizontal synchronizing frequency and the color subcarrier in the synchronizing signal. 10, and is supplied to the electronic zoom circuit 7 via the color demodulation circuit 14 and the switch circuit 205.

The chrominance signal C input from the S input terminal 8 is AD-converted by the AD converter 15 to become a digital chrominance signal.
Are supplied to the color demodulation circuit 14 through which the color difference signals RY and BY are demodulated.
It is input to the electronic zoom circuit 7 via 9 and 20.

When the external signal is the composite video signal CO, the composite signal is input from the external input terminal 9 and supplied to the AGC circuit 201 via the switch circuit 11, and in response to the synchronization signal SYNC in the same manner as described above. The signal level is adjusted so that the synchronization signal portion has a predetermined level, and the output thereof is AD-converted by the AD converter 13.

The digital composite video signal as the output is separated into Y and C in the YC separation circuit 10, and Y is input to the electronic zoom circuit 7 via the switch circuits 203 and 18.

The chrominance signal C out of the output of the YC separation circuit 10 passes through the switch circuit 204 and is output by the color demodulation circuit 14 to the digital color difference signal R in the same manner as described above.
−Y and BY. The signal is supplied to the switch circuit 19,
The signal is input to the electronic zoom circuit 7 via 20.

In the electronic zoom circuit 7, as in the case of the circuit of FIG. 1, an enlargement process or a reduction process is performed at a magnification corresponding to the zoom signal input from the zoom terminal 17, and at the same time,
In the first half of the circuit, LCLK is used, and in the middle, RCLK generated by the digital recorder circuit 21 is used, and the clock rate is converted at the joint. The output of the electronic zoom circuit 7 is input to the digital recorder circuit 21 in the same manner as described above, and operates in the same manner as in FIG.

Next, the reproduction mode is the same operation as that of FIG. 1 and its description is omitted. In the configuration of this embodiment, since the level of the Y signal of the S input signal and the composite input signal among the external input signals is adjusted by the same AGC circuit, the level of the external input signal is not a regular value, or Even when the level fluctuates, it is possible to suppress the deterioration of the image.

Further, since the YC separation, the color demodulation and the synchronization separation are performed by digital signals, there is no crosstalk of signals between circuits, deterioration in characteristics due to temperature changes of circuit components and individual variations, and changes over time.

When the circuit is configured as a single semiconductor integrated circuit, a device with high integration, low cost and low power consumption can be realized. Also, two AD converters for external input may be used. In addition, special effects such as enlargement and reduction can be performed on an external input signal as in the case of shooting with a camera.

FIG. 5 shows a second embodiment of the present invention.
A detailed example of a part of the electronic zoom circuit 7 is shown. Parts other than those shown in FIG. 5 are the same as those in FIG. 2 or FIG.

In FIG. 5, reference numeral 210 denotes a switch circuit,
11 and 212 are coefficient circuits having coefficients K1 and K2, respectively. The zoom signal ZOOM input from the zoom input terminal 102 is sent to the control circuit 111 by the vertical zoom signal VZ.
The signal is input to the multiplier 110 at the same time as being input as OOM, and the output is input to the control circuit 111 as the horizontal zoom signal HZOOM.

Coefficients K1 and K of coefficient circuits 211 and 212
2 is selected by the switch circuit 210 in accordance with the camera / external input switching signal, and the multiplier 110
Is input as the other input.

In the control circuit 111, the interpolation coefficients X1, X2, X3, X4 and CE, RH are inputted in accordance with RCLK, HD, VD, VZOOM, HZOOM input as described above.
D is generated and the operation of enlargement, reduction, and clock rate conversion is performed in the same manner as in the case of FIG. 2 or FIG. In this case, the clock rate can be converted at an appropriate ratio according to the camera recording mode and the external input mode. In addition, an increase in the number of circuits at that time can be minimized.

Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 6, 1 is an imaging lens, 2 is a CCD which is a color imaging device, 4 is a sample and hold, and 5 is an AD converter.

[0092] Also, 55 is a filter color separation block, from the input digital image signal, the luminance signal Y _0, and Y ₀ than 1 horizontal period (hereinafter 1H) delayed luminance signal Y _1, the color signals Y _L , C _R , and C _B.

Reference numeral 56 denotes a low-pass filter, and reference numeral 57 denotes a color separation matrix circuit, which receives the input color signals Y _L , C _R , and C.
_This is for obtaining primary color signals R, G, B by performing a matrix operation on B.

Reference numeral 58 denotes a white balance circuit for multiplying the input R, G, and B signals by a coefficient corresponding to the color temperature of the subject illumination light, and 59 denotes gamma correction of the input R, G, and B signals. The gamma circuit 60 performs the input R,
A color difference matrix 61 for synthesizing the color difference signals RY and BY from the G and B signals, and 61 is a modulation circuit for quadrature two-phase modulating the input RY and BY signals with a color subcarrier.

Reference numeral 62 denotes a burst adder, 63 denotes a color signal output terminal, 64 denotes a subtractor, 65 denotes a vertical aperture signal processing circuit (VAPC processing) including variable gain, base clip, and low-pass filter processing, 66 denotes an adder, 67 Is a gamma circuit, 68 is a white / black clip circuit, 69 is a delay circuit, 70 is a synchronous adder, and 71 is a Y output terminal.

In the present embodiment configured as described above,
A subject image (not shown) is formed on the photoelectric conversion surface of the CCD 2 by the imaging lens 1, and is photoelectrically converted by the CCD 2 and output as an imaging signal. Then, while being made continuous by the sample and hold circuit 4, A
The digital signal is converted by the D converter 5 into a digital image signal. The digital imaging signal by the filter color separation block 55, the color signals Y _L, C _R, and converted into C _B and the luminance signal Y _0, Y _1.

[0097] The color signals Y _L, C _R, C _B are formed as follows. That is, on the photoelectric conversion portion of the CCD2 _{is, Y e, C y, M} g, the four fine color filters of G are formed. At the time of reading, the CCD 2 uses an interlace operation to combine the four combinations Y _e + M _g ,
_{C y + G, Y e +} G, reads are added by C _y + M _g.
These convenience _{W r, G b, G r} , referred to as W _b.

[0098] This on filter color separation _{block, Y L = W r + G} b or G _r + W _b,, and _{C R = W r -G b C} B = G r -W b.

The primary color components in each are Y _L = 2R + 3G + 2B C _R = 2R-GC _B = G−2B. These are subjected to a matrix operation using a color separation matrix described later to obtain primary color components R, G, and B. . From the Y _L, C _{R, and} C _B thus obtained, low-pass components are extracted by a low-pass filter 56, and a color separation matrix is used for input signals Y _L, C _{R, and} C _B.

[0100]

(Equation 1)

By the matrix operation, the primary color components R,
G and B are separated. R, G, B obtained in this way are
The white balance RGB is multiplied by the inverse ratio of the color component ratio in the object illumination light by the white balance circuit 58 to make the RGB of the white object 1: 1:
The gamma correction is performed by the gamma circuit 59.

Next, color difference signals RY and BY are obtained by a predetermined operation in a color difference matrix 60, and a modulation circuit 61
Quadrature two-phase modulation is performed, and a burst signal is added by a burst adder 62. After being directly output from the C output terminal 63 or being subjected to DA conversion, the television or V
Output to an external device such as a TR.

The output signals Y ₀ and Y ₁ of the filter color separation block 55 are first converted by a subtractor 64 into Y ₁ −Y
₀ is obtained, and this signal is subjected to variable gain, base clipping, and low-pass filter processing by a VAPC process 65 to form a vertical aperture signal.

Next, it is added to Y ₀ by the adder 66, gamma-corrected by the gamma circuit 67, clipped at predetermined white and black levels by the white / black clip 68, and delayed by the delay circuit 69. .

The delay amount of the delay circuit 69 is 56, 57, 5
8, 59, 60, 61, 62 and 63, the total number of delay stages in the signal processing circuit is 64, 65, 66,
Since the number of delay stages is greater than the total number of delay stages of the luminance signal processing circuit formed by the circuits 67, 68, 69, 70, and 71, the delay amount is set to the difference. Its output is the synchronous adder 7
By 0, a synchronization signal is added, and the Y output terminal 21 is connected to an external device in the same manner as the above-described signal.

FIG. 7 is a detailed diagram showing an example of the filter color separation block 55 in FIG. In FIG. 7, 101
Is a delay line (1H DL) for one horizontal period, 1
02, 103, 104, 105, 106, 107, 12
4, 125, 126, 127, 128 and 129 are delay elements such as D-type flip-flops.

Also, 108, 109, 110, 111,
112, 113, 114, 130, 131, 132, 1
33,134,135,136 are each a coefficient unit having a predetermined coefficient K ₁ ~K _7. 115, 137 are adders for adding all the input signals, 116, 12
1, 138 is an adder, 117, 139 are 1/2 coefficient multipliers, 118, 119, 122, 123, 140, 141
Is a switch circuit, and 120 and 142 are subtractors.

In the filter color separation block 55 configured as described above, the input signal S _in
02 to 107, the output of S _in and the respective delay elements are K ₁ by coefficient units 108 to 114, respectively.
ＫK ₇ are multiplied by each other, added together by the adder 115 to form and output a luminance signal Y ₀ .

Further, the input signal S _in and the delay element 10
3 are added by an adder 116, and a coefficient unit 117
The switching circuits 18 and 19 alternately select the output of the delay element 102 and the switching signal S ₁ . The switching signal S ₁ is a signal that switches in synchronization with the horizontal scanning clock according to the arrangement of the color filters of the CCD 2.

[0110] The output of the switch circuit 118 and 119 are added by one, at the same time Y _L is obtained is subtracted by the subtractor 120. The output of the subtracter 120 is switched alternately according to the output and switching signal S ₂ of the subtracter 142 to be described later by the switch circuits 122 and 123, C _R
And _CB are formed and output.

The input signal S _in is connected to the delay line 1
01 is delayed by one horizontal period, and the delay elements 124 to 129, coefficient units 130 to 136, and
7, a luminance signal Y ₁ delayed by one horizontal period from Y ₀ is generated and output.

As described above, the outputs of the delay line 101 and the delay element 125 pass through the adder 138 and the coefficient unit 139, and alternately with the output of the delay element 124.
0, 141. Then, next, the subtractor 142
Are subtracted from each other by the switch circuit 12 as described above.
2, 123 are alternately selected with the output of the subtractor 120 to form C _{R and} C _B and output.

In FIG. 7, Y ₀ is the following transfer function H ₁
(Z). H ₁ (Z) = K ₁ + Z ^-1 · K ₂ + Z ^-2 · K ₃ + Z ^-3 · K
₄ + Z ^-4 · K ₅ + Z ^-5 · K ₆ + Z ^-6 · K ₇

In a normal video filter, K ₁ =
K ₇ , K ₂ = K ₆ , and K ₃ = K ₅ . At this time, the group delay time is 3τ (τ is the delay time per stage of the delay element). Y ₁ is also 3τ in the horizontal direction.
it is conceivable that. As for _{Y L, C R, C B} , although it includes a non-linear circuit (switching circuit), if considered in the horizontal direction only, the group delay time is considered 1.tau. Therefore, Y _L, C _R, is C _B Y _0, Y ₁ from 2
τ is output earlier, and the number of stages of the delay circuit 19 described above can be reduced.

FIG. 8 is a block diagram showing a third embodiment of the present invention. In FIG. 8, the same reference numerals are given to the same functional units as those in the above-mentioned drawings. In FIG. 8, 143 is a 1H delay line, 144 is an adder, and 145 is a coefficient unit having a coefficient of 1/2.

The input signal S ₁ is added to a signal delayed by 2H, which will be described later, by an adder 144 and halved by a coefficient unit 145. Then, as in the case of FIG.
02, the coefficient unit 108, and the adder 116. The output of the delay line 101 is input to the delay element 124, the coefficient unit 130, and the adder 138 at the same time as the case of FIG.

- 0117] In the delay line 143, further 1H delay an input signal, and outputs a total 2H delayed signals, this is added to the S _in the adder 144 as described above. Subsequent operations are the same as in FIG.

In the case of such a configuration, the input signal S _in
On the other hand, if the signal delayed by 1H is S _1H and the signal delayed by _2H is S _2H , the signals used to generate the color signals are S _in + S _2H / 2, S _1H , Since the centers of gravity are equal, the occurrence of color blur (false color signal) due to an error is small. In addition, since the center of gravity of the vertical contour signal of the luminance signal is similarly matched, distortion of the image in the vertical direction is small.

In the above-described embodiment, the recording and reproduction of an image is performed by the digital recorder circuit. However, the present invention is not limited to this, and any recording and reproduction apparatus that inputs a digital signal can implement the present invention. It is possible.

[0120]

As described above, according to the present invention, the arithmetic means for correcting the zoom magnification signal in accordance with the ratio between the first clock and the second clock is provided. Of the clock rate for the same can be performed simultaneously. According to another feature of the present invention, since the frequency conversion is performed in the electronic zoom means, the circuit in the electronic zoom means can be shared to constitute the clock rate conversion circuit. Becomes
The configuration of the entire apparatus can be simplified. According to another feature of the present invention, the conversion ratio between the clock rates of the first clock and the second clock and the zoom magnification can be independently changed. When used, only the conversion rate of the clock rate needs to be changed, and the circuit configuration for the change can be minimized.

According to the second aspect of the present invention, a digital image pickup signal processing circuit can be realized without increasing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of an imaging and recording device of the present invention.

FIG. 2 is a detailed diagram of an electronic zoom circuit in FIG.

FIG. 3 is another detailed diagram of the electronic zoom circuit in FIG. 1;

FIG. 4 is a configuration diagram showing a second embodiment of the present invention.

FIG. 5 is a detailed view of a main part of the electronic zoom circuit in FIG. 4;

FIG. 6 is a configuration diagram showing a third embodiment of the present invention.

FIG. 7 is a diagram illustrating details of a filter color separation block in FIG. 6;

8 is a diagram showing another detail of the filter color separation block in FIG.

[Explanation of symbols]

 Reference Signs List 1 lens 2 CCD 3 camera timing generator 4 sample hold circuit 5 AD converter 6 camera signal processing circuit 7 electronic zoom circuit 8 YC separation type external video signal input terminal 9 external video signal input terminal for composite video signal 10 YC separation circuit 13 AD converter 14 Color demodulation circuit 21 Digital record circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/222-5/257 H04N 5/76-5/956

Claims (4)

(57) [Claims] An imaging unit configured to image an object to form an image signal; a recording unit configured to record an image signal formed by the imaging unit; and an electronic unit configured to electronically convert an image formed by the imaging unit. Electronic zoom means for enlarging or reducing an image; zoom magnification signal input means for inputting a zoom magnification signal for changing the electronic zoom magnification in the electronic zoom means; and a first for driving the imaging means. A first clock generating means for generating a clock, and a second clock for generating a second clock for driving the recording means, wherein the second clock has a different frequency from the first clock.
And a calculating means for correcting the zoom magnification signal in accordance with a ratio of the first clock and the second clock. 2. The imaging and recording apparatus according to claim 1, wherein a conversion ratio between a clock rate of the first clock and the second clock and the zoom magnification can be independently changed. . 3. An input side of said electronic zoom means is connected to said first zoom means.
The imaging and recording apparatus according to claim 1, wherein the output of the electronic zoom means is driven by the second clock. 4. The electronic zoom device according to claim 1, further comprising a switching unit for switching between an image signal formed by said imaging unit and an external input signal input from outside. 3. The imaging recording device according to claim 1.