JP3280243B2 - Manufacturing method of BGA type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a BGA type semiconductor device.

[0002]

2. Description of the Related Art Higher integration and higher density of semiconductor devices are strongly demanded along with higher performance of electric and electronic parts. Has been changed from a structure having bonding pads on two sides to a structure having bonding pads on all four sides.

Further, as a countermeasure for increasing the number of pins, for example, U
In SP5148265, an insulating film on which a wiring pattern is formed is arranged on the surface (functional surface side) of a semiconductor chip via an elastomer layer, and a plurality of solder balls are arranged on the surface of the insulating film in a grid pattern. A semiconductor device called a “ball grid array” has been proposed.

[0004] In this BGA type semiconductor device, the connection portion between the bonding pad of the semiconductor chip and the wiring pattern is covered with an insulating coating material such as a silicon resin by a potting method in order to prevent unnecessary electrical contact with the outside. Have been.

[0005] Incidentally, since this BGA type semiconductor device is formed based on one insulating film in which a plurality of wiring patterns are formed in a grid pattern, a plurality of chips are mounted, and after completion of a covering step, individual products are formed. A method of performing a dividing operation for performing the above operation is adopted. In such a division,
Conventionally, the cutting operation has been performed using a rotary blade used for cutting a silicon wafer.

[0006]

However, according to this dividing method, not only the external precision of each separated semiconductor device is not good, but also an expensive dividing device is required, so that the production cost is enormous. Become. Furthermore, in this dividing step, the coating material for coating may also need to be cut at the same time, and a fine powder of the coating material may be scattered during the dividing operation by the rotary blade, so that a cleaning step is required after the division. Was. Furthermore, since the coating material used here has elasticity, there is a problem that fine powder is not sufficiently washed away even by washing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device which is low in cost, has high mass productivity, and has a good appearance.

[0008]

Accordingly, the first B of the present invention is described.
The feature of the manufacturing method of the GA type semiconductor device is that a semiconductor chip having a plurality of bonding pads on a peripheral edge and a wiring pattern are provided and connected to the wiring pattern to protrude and electrically connect to the outside. And an insulating film comprising solder balls of the type described above, and the insulating film is adhered to the functional surface side of each of the semiconductor chips via an insulating member and formed on the peripheral edge of the semiconductor chip. In the method for manufacturing a BGA type semiconductor device in which the wiring patterns are connected to the bonding pads, a plurality of the wiring patterns are arranged at predetermined intervals, and an insulating film is provided on the functional surface side of each semiconductor chip. And bonding the wiring pattern to a plurality of bonding pads formed on the periphery of the semiconductor chip. A continuous bonding step, a covering step of covering a connection portion between the wiring pattern and the bonding pad of the semiconductor chip with an insulating coating material, and a dividing step of individually dividing the semiconductor device by a punching method. Features.

Preferably, the dividing step is performed by punching using a mold having a circular projection having a right triangular cross section around a hole of a die of the press mold. .

Preferably, in the dividing step,
The coating material is cut by punching using a press die together with the insulating film.

According to the method of the present invention, after the coating film is formed, the cutting is performed by the punching method, so that a semiconductor device which is inexpensive and has a good appearance can be obtained. In addition, mass productivity is significantly improved.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
This will be described in detail with reference to the drawings. As shown in the conceptual diagram of FIG. 1, the method of manufacturing a BGA type semiconductor device according to the present invention employs a punching method using a die in which a ring-shaped projection 31 having a triangular cross section is provided around a hole H1 of a die 30 of a press die. The insulating film 11 on which the semiconductor chip 10 is mounted
Is divided along with the coating material 13.

That is, after a mounting body formed by connecting an insulating film 12 having a wiring pattern on the surface of the semiconductor chip 10 is coated with a coating material 13 at a connection portion between a bonding pad of the semiconductor chip 10 and the wiring pattern, This is mounted on a die 30 having an annular projection 31 having a triangular cross section, and the insulating film 11 is cut together with the coating material 13 using a punch 32 to divide the semiconductor film into individual semiconductor devices. Here, reference numeral 33 denotes a stripper.

A large number of wiring patterns are continuously formed on the insulating film. After mounting the semiconductor chip 10 thereon, the bonding pattern between the bonding pads 10B of the semiconductor chip 10 and the wiring patterns 16S shown in FIG. A semiconductor device as shown in FIG. 3 is formed by forming a coating layer 13 on a connection portion and thereafter dividing the coating layer by a punching device shown in FIG.

[0015]

Next, this method will be described in detail with reference to process drawings. First, as shown in FIG. 4, a copper foil 15 is adhered to the surface of an insulating film 11 made of a polyimide tape, and a photoresist (not shown) is further applied to the surface and patterned by photolithography. Is formed.

Thereafter, a photoresist is further applied and photolithography is performed to form a resist pattern R as shown in FIG. In the following drawings, one half of one unit is shown, and a large number of such units are arranged at predetermined intervals.

Thereafter, as shown in FIG. 6, a gold plating layer 16 is formed on the surface of the copper foil 15 exposed from the resist pattern R by electroless gold plating.

Then, a photoresist is applied from the back side, photolithography is performed, and the insulating film 11 is etched using this as a mask to form a connection piece (beam lead) 16S at the tip of the wiring pattern as shown in FIG. A window W and a via V are formed in an electrical connection region between the peripheral edge region and the solder ball 12.

As shown in FIG. 8, solder balls 12 are formed in the vias V except for the connection piece forming portions so as to be connected to the pattern of the copper foil 15 and protrude from the surface.

Then, as shown in FIG. 9, copper etching is performed to remove copper exposed in the window by etching.
As a result, the area of the window W has only the gold pattern as the connection piece 16S, and is in a flexible state. The central portion has a two-layer structure of a copper foil pattern 15 and a gold plating layer 16 and is connected to the connection pieces 16S, respectively, and functions as a wiring pattern.

Further, as shown in FIG. 10, an insulating elastomer (silicon elastomer) 17 is applied to the wiring pattern forming surface side of the insulating film by a printing method.
Bake and cure.

Thereafter, an adhesive is applied onto the insulating elastomer layer 17 and is positioned on the diced semiconductor chip 10 as shown in FIG. The conductive film 11 is fixed.

Thereafter, as shown in FIG. 12, by using a bonding tool BT, a connection piece is thermocompression-bonded to a bonding pad on a peripheral portion of the semiconductor chip 10 to electrically connect the wiring pattern to the semiconductor chip. Make a connection.
At this time, since the gold connection piece 16S is thin, it is cut at the same time as thermocompression bonding.

As shown in FIG. 13, the photosensitive film 3 covers the window W of the insulating film 11.
Attach 0. Then, a fine hole o is formed in this.

Thereafter, as shown in FIGS. 14 (a) and 14 (b) (FIG. 14 (a) is a sectional view taken along a line aa in FIG. 14 (b)), the solder ball forming region A lower mold 20L having a plurality of recesses 21 is prepared, and a plurality of openings H having an opening area and a height equivalent to that of the semiconductor chip are provided corresponding to the position of the semiconductor chip. Is prepared. Then, the frame 22 is arranged so that the semiconductor chips are respectively arranged in the openings.
Then, the insulating film connected to the semiconductor chip is fixed, placed on the lower mold 20L, and further, the upper mold 20U is installed.

Then, an insulating coating material M is filled between the opening and the semiconductor chip. 25 is a filling hole of the coating material. In this state, by applying pressure as shown in FIG. 15, the connection portion between the wiring pattern of the semiconductor chip and the bonding pad is covered with a coating material. At this time, while vacuum-suctioning from the lower mold 20L side through the fine holes o formed in the film,
By filling the coating material, the coating material is filled well.

Finally, as shown in FIG. 16, after the coating is completed and the mold is removed, the photosensitive film is removed or brought into close contact by heat treatment, and then the punching device shown in FIG. 1 is used. Then, the coating material is cut together with the insulating film 11 and cut into individual pieces.
As shown in (1), a semiconductor device covered with a coating material and protected is completed. 25 is a filling hole of the coating material.

According to the method of the embodiment of the present invention, since the insulating film 11 is cut by using a punching device, a good appearance and high dimensional accuracy can be obtained.

In the above embodiment, since the coating material is molded using a mold, a dense and high-quality coating is performed, and it is not necessary to cut the coating material. The coating material can be easily separated at the same time as the insulating film is separated by using the punching device of the present invention even when the coating material protrudes without using the coating material or when the coating material protrudes using the mold. Manufacturing costs are reduced, and
Since there is no scattering of the fine powder of the coating material, there is no problem that the reliability is reduced due to the adhesion of impurities.

In the above embodiment, the insulating film (TAB substrate) on which the solder balls are formed is bonded to the semiconductor chip. However, after the bonding and coating are completed, the solder balls are formed. Is also good. As a second embodiment of the present invention, this embodiment will be described with reference to the process sectional views of FIGS.

As shown in FIGS. 18 to 21, up to the step of forming a window W and a via V in an electrical connection area between the solder ball 12 and a peripheral area where a connection piece (beam lead) is formed. Are formed in the same manner as the steps shown in FIGS. 4 to 7 of the first embodiment.

Then, as shown in FIG.
The copper foil pattern 15 exposed inside is removed by etching. At this time, the via V is covered and protected with a resist (not shown) or the like.

Thereafter, as shown in FIG. 23, an insulating elastomer (silicone elastomer) 17 is applied on the wiring pattern forming surface side of the insulating film by a printing method.
Bake and cure.

After that, an adhesive is applied on the insulating elastomer layer 17 and then positioned on the diced semiconductor chip 10 as shown in FIG. Insulating film 11
Is fixed.

Thereafter, as shown in FIG. 25, by using a bonding tool BT, a connection piece is thermocompression-bonded to a bonding pad on a peripheral portion of the semiconductor chip 10 to electrically connect the wiring pattern to the semiconductor chip. Make a connection.
At this time, since the gold connection piece 16S is thin, it is cut at the same time as thermocompression bonding. Then, as shown in FIG. 26, a photosensitive film 30 is attached on the insulating film 11 thereafter.
Thereafter, the frame 22 is attached to the insulating film 11 on which the semiconductor chip is mounted in the same manner as in the first embodiment, and is set in a mold as shown in FIG. Coating is performed similarly. Here, since the solder balls have not been formed yet, the concave portion of the lower mold is unnecessary. The other steps may be performed in exactly the same manner as in the first embodiment.

Molding is performed as described above, and the connection area between the connection piece and the bonding pad is formed with the coating material 13.
Cover with.

Thereafter, as shown in FIG. 28, photolithography is performed to expose the photosensitive film, and as shown in FIG. 29, a hole h is formed in the solder ball forming region. Then, as shown in FIG. 30, flux is printed on the copper foil 15 exposed in the hole h, and Pb 10%
Solder ball 12 of 0.7 mm diameter made of 90% solder
Is supplied, and the surface is fixed to the copper pattern 15 through a heating process at 320 ° C. for 10 seconds (peak temperature maintaining time). And if necessary, isopropyl alcohol (IPA)
And ultrasonic cleaning to remove excess flux. Finally, the photosensitive film is removed or adhered by heat treatment, and if necessary, the surface of the solder ball is plated with a noble metal such as palladium, and thereafter, the same as that used in the first embodiment. The insulating film is cut together with the coating material using a punching device, and a BGA type semiconductor device in which the connection between the wiring pattern and the semiconductor chip is well covered and protected as shown in FIG. 31 is completed. Here, the solder balls 12 are formed on the entire surface so as to form a lattice shape, and the back surface of the semiconductor chip 10 is in a bare state. Thus, a low-cost and highly reliable semiconductor device is formed. In this method, since a photosensitive film is adhered, the releasability from a mold is improved.

The pitch and diameter of the via holes are as follows:
For example, if the lattice pitch is 1 mm, the hole diameter can be changed to 0.55 mm, and if the lattice pitch is 1.5 mm, the hole diameter can be changed to 0.75 mm.

Furthermore, the composition of the solder ball can be appropriately selected. For example, when eutectic solder of Pb 37% Sn 63% is used, the heating temperature in the fixing step may be about 230 ° C.

[0040]

As described above, according to the present invention, since the insulating film is divided by using the punching device, it is possible to obtain a semiconductor device having high precision and good appearance.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing the present invention.

FIG. 2 is a manufacturing process diagram of the semiconductor device of the present invention.

FIG. 3 is a manufacturing process diagram of the semiconductor device of the present invention.

FIG. 4 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a manufacturing process diagram of the semiconductor device according to the first embodiment of the present invention;

FIG. 9 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 10 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 12 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 13 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 14 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 15 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 16 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 17 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 18 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 19 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 20 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 21 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 22 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 23 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 24 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 25 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 26 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 27 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 28 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 29 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 30 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 31 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor chip 11 Insulating film 12 Solder ball 13 Coating material 15 Copper foil 16 Gold plating layer 16S Connection piece 20U Upper die 20L Lower die 22 Frame H Opening 30 Die 31 Annular protrusion 32 Punch 33 Stripper

Continuation of the front page (56) References JP-A-5-190747 (JP, A) JP-A-6-275670 (JP, A) JP-A-7-273246 (JP, A) JP-A-8-31868 (JP) JP-A-8-31869 (JP, A) JP-A-8-83818 (JP, A) JP-A-9-246416 (JP, A) JP-A-10-22411 (JP, A) 10-116845 (JP, A) JP-A-10-116528 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/60 H01L 23/12

Claims (3)

(57) [Claims] A semiconductor chip having a plurality of bonding pads on a peripheral edge thereof; and a plurality of solder balls connected to the wiring pattern and protruding and electrically connected to the outside. And an insulating film consisting of
On the functional surface side of each of the semiconductor chips, the insulating film is attached via an insulating member, and the wiring pattern is connected to a bonding pad formed on a peripheral portion of the semiconductor chip. In the manufacturing method, an insulating film formed by arranging a plurality of the wiring patterns at predetermined intervals is attached to a functional surface side of each of the semiconductor chips via an insulating member, and a peripheral portion of the semiconductor chip is provided. A bonding step of connecting the wiring pattern to a plurality of bonding pads formed on the semiconductor chip; a coating step of coating a connection portion between the wiring pattern and the bonding pad of the semiconductor chip with an insulating coating material; BGA, comprising a cutting step of cutting individually by a punching method using a mold. The method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein the dividing step is performed by punching using a mold provided with an annular protrusion having a right triangular cross section around a hole of a die of the press mold. Item 2. The method for manufacturing a BGA type semiconductor device according to Item 1. 3. The method of manufacturing a BGA type semiconductor device according to claim 1, wherein said dividing step is a step of dividing both the coating material and the insulating film.