JP3272396B2 - Plasma display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) of a surface discharge type having a three-electrode structure for displaying a matrix of various colors using phosphors and a drive control system thereof.

2. Description of the Related Art Plasma display devices can display images at a higher speed than liquid crystal display devices and can easily enlarge a display screen. Therefore, the use of the plasma display devices in fields such as OA equipment and public information display has begun to spread. . Further, for example, progress is expected in the field of high definition television.

[0003] With the expansion of such uses, there has been an increasing demand for plasma display devices, particularly for higher brightness of color display.

[0004]

2. Description of the Related Art A matrix display type PDP displays an arbitrary character or figure by selectively emitting light in unit light emitting areas arranged vertically and horizontally.

[0005] Among these types of PDPs, surface-discharge type PDPs having a three-electrode structure suitable for color display using phosphors are, as schematically shown in FIG. A plurality of electrode pairs consisting of X and Y;
It has a plurality of address electrodes A orthogonal to each electrode pair.
Each electrode pair corresponds to one line (row) of the display, and each address electrode A corresponds to one column of the display.

In general, one display electrode X is electrically shared among a plurality of lines, and the other display electrode Y is electrically independent for each line. A surface discharge cell C is defined for each unit light emitting area EU by the display electrodes X and Y.
The selection (address) of lighting (discharging) or non-lighting of each surface discharge cell C is performed by the address electrodes A.

FIG. 10 shows a conventional surface discharge type PDP 1j.
FIG. 11 is an exploded perspective view showing a cross-sectional structure of a portion corresponding to one unit light emitting region EU, and FIG. 11 is a voltage waveform diagram showing a driving method suitable for a conventional PDP 1j. In FIG. 10, the range of the unit light emitting region EU on the inner surface of the glass substrate 11 (the surface on which the display electrodes X and Y are formed) is indicated by a two-dot chain line.

In the PDP 1j, display electrodes X and Y are arranged on the inner surface of the glass substrate 11 on the display surface H side of the glass substrates 11 and 21 opposed to each other with the discharge space 30 interposed therebetween.
Each of these display electrodes X and Y is composed of a wide band-like transparent conductive film (such as a Nesa film) 41 and a narrow band-like metal film (such as Cr—Cu—Cr) 42 that supplements the conductivity. Light shielding on the display surface H is minimized.

A dielectric layer 17 for AC driving is provided so as to cover the display electrodes X and Y. On the dielectric layer 17, a grid-like shape for dividing the discharge space 30 into unit light emitting areas EU is provided. Partition wall 19W is provided. The surface of the dielectric layer 17 is covered with a protection film made of MgO (not shown) at a stage after the partition wall 19W is provided.

On the other hand, on the inner surface of the glass substrate 21 on the back side, the discharge space 3 along with the address electrodes A and the partition walls 19W are provided.
A band-shaped partition wall 29 which defines 0 and defines a gap size thereof
And a phosphor 28 of a predetermined emission color.

The address electrode A is arranged so as to approach one end of the unit light emitting region EU, that is, adjacent to one of the partition walls 29 on both sides of the unit light emitting region EU.
8 is arranged on the surface of the glass substrate 21 between the address electrode A and the other partition 29.

When displaying the PDP 1j having the above-described structure, the address method is a type of so-called erase address method in which writing (forming the accumulation state of wall charges) and selective erasing are sequentially performed in line units. A method utilizing self-erasing discharge for erasing is used.

That is, as shown in FIG. 11, in the initial address cycle CA of the line display period T corresponding to the display of one line, the peak value V is first applied to the display electrode X.
A positive write pulse PW of w is applied, and a negative sustain pulse PS of peak value Vs is simultaneously applied to the display electrode Y corresponding to the line to be displayed. In the figure, the hatched lines attached to the sustaining pulse PS indicate that the pulse is selectively applied for each line.

As a result, since the relative potential difference between the display electrodes X and Y, that is, the cell voltage applied to the surface discharge cells C exceeds the discharge starting voltage, all the surface discharge cells C corresponding to one line have a surface potential. Discharge occurs. When surface charges cause wall charges having a polarity opposite to the applied voltage to accumulate in the dielectric layer 17 and the cell voltage decreases to a predetermined value, the surface discharge stops. In this process, the surface discharge cells C are in the address state.

Subsequently, a sustaining pulse PS is alternately applied to the display electrodes X and Y. Then, since the voltage Vs of the sustaining pulse PS is superimposed on the wall charge and the cell voltage exceeds the firing voltage, a surface discharge occurs each time the sustaining pulse PS is applied.

After stabilizing the written state by causing a plurality of discharges as described above, at the end of the address cycle CA, one line is erased in order to erase (selectively erase) wall charges unnecessary for display. The peak value V is applied to the address electrode A corresponding to the unit light emitting area EU to be turned off in the
A selection discharge pulse PA of positive polarity a is applied, and at the same time, a sustaining pulse PS is applied to the display electrode Y. In the figure, a hatched line attached to the selective discharge pulse PA indicates that the selective discharge pulse PA is selectively applied to each unit light emitting area EU in one line.

At the rising edge of the selective discharge pulse PA, a counter discharge in the gap direction of the discharge space 30 occurs at the intersection of the address electrode A and the display electrode Y. This discharge causes excessive wall charges to accumulate in the surface discharge cells C, and when the selection discharge pulse PA falls and the sustaining pulse PS rises, a discharge (self-erasing discharge) using only the wall charges occurs. . The self-erasing discharge has a short duration because no discharge current is supplied from the electrodes. for that reason,
Wall charges disappear in the form of neutralization.

In the subsequent display cycle CH, a sustaining pulse PS is alternately applied to the display electrodes X and Y.
As a result, at each falling edge of the sustaining pulse PS, only the surface discharge cells C in which the wall charge has not disappeared by the self-erasing discharge are intermittently turned on, and the phosphor 28 is excited by the ultraviolet light generated at this time. To emit light. Display cycle C
In H, the display brightness is adjusted by appropriately selecting the cycle of the sustaining pulse PS.

The above operation is repeated every line display period T, and display is performed for each line in order. Note that writing is performed collectively on all lines, for example, and only selective erasure of wall charges is performed sequentially for each line, thereby shortening the writing period in the display period (field) of one screen to speed up display. Can also be planned.

[0020]

Heretofore, there has been a problem that practically sufficient luminance cannot be obtained in an attempt to increase the definition of a display (ie, to make the unit light emitting region EU finer).

That is, it is necessary to select the width of the address electrode A so that the area facing the display electrode Y is equal to or larger than a certain value in order to secure the address. However,
In the conventional PDP 1j, the phosphor 28 is arranged so as to expose the address electrode A to the discharge space 30 as described above. Therefore, the higher the definition, the larger the ratio of the address electrode A in the unit light emitting area EU. Become. As a result, the substantial light emission area (the formation area of the phosphor 28) is reduced,
The predetermined luminance cannot be secured.

Therefore, it is conceivable to provide the phosphor 28 so as to cover the inner surface of the glass substrate 21 including the surface of the address electrode A. However, in this case, since the phosphor 28 (insulator) is interposed between the address electrode A and the discharge space 30, the address electrode A and the display are caused by the wall charges accumulated in the phosphor 28. The discharge between the electrode Y and the self-erasing discharge is impaired, resulting in excessive lighting or lighting mistake.

The present invention has been made in view of the above problems, and has as its object to realize high-definition and bright display.

According to the first aspect of the present invention, the discharge space 3
A plurality of pairs of display electrodes X and Y parallel to each other and a dielectric layer 17 covering them are provided on the inner surface of one substrate 11 of the display electrodes X, Y and the address electrodes a and the surface discharge type plasma display panel of a matrix display type consisting have <br/> phosphor 2 8 provided so as to covering these object intersecting And a line corresponding to the display electrode pair
After writing to all the surface discharge cells of the inner, the Rye
A discharge is generated between one display electrode Y in the display electrode pair corresponding to the
Make application of the erase pulse PD to erase, in parallel with this
Address electrodes corresponding to the surface discharge cells to be left
Against A, an erase address of one line of an electric field control pulse PC by indicia pressurized to Rukoto for canceling an electric field due to the erase pulse PD occurring surface discharge cell to leave charge
And a drive control system of an erase address system configured to perform the operation.

The apparatus according to the second aspect of the present invention provides a plasma display panel 1 and all surfaces corresponding to display electrode pairs.
Collectively define the state of accumulation of predetermined wall charges for discharge cells.
After applying the resulting voltage, pulses PS and PA for generating a selective discharge for writing are applied to one display electrode Y of the display electrode pair and each of the address electrodes A , respectively.
And a drive control system 3 of a write address system configured to sequentially perform a write address of one line .

[0026] In apparatus according to the invention of claim 3, the drive control system 3 of the write address method, for all the surface discharge cells corresponding to the display electrode pairs, by producing collectively surface discharge, the fluorescent After accumulating positive charges on the charge accumulation surface of the body and accumulating negative charges on the dielectric layer, the relative potential of the selected display electrode of the display electrode pair with respect to the other display electrode is changed. So that it has a negative potential
It applies a pulse, to the address electrodes, by the relative potential between those the one display electrodes to apply a pulse for writing so that the positive potential, is selected
It is configured to perform the address for each line .
The plasma display device according to claim 4,
The drive control system of the write address system has an address for each line.
Prior to the address operation, all of the display electrode pairs
At least one of the surface discharge cells is discharged
The potential of the display electrode is relatively positive with respect to the address electrode.
A pulse having the polarity shown below was applied between the display electrode pair.
After that, it occurs in all surface discharge cells corresponding to the display electrode pairs.
It is configured to apply a voltage for erasing the charge caused by the discharged discharge . 6. The driving method according to claim 5 , wherein the writing address method is used.
Control system, after applying a voltage for the erasure, for one of the display electrodes, so the relative potential between the other display electrode becomes a negative potential, selectively path to the display electrode It applies a pulse, to the address electrodes, to apply a pulse such that the relative potential is a positive potential between the address electrode and the counter to perform address discharge display electrodes
You. 7. The plasma display apparatus according to claim 6, wherein the matrix display type surface discharge type plasma display panel has one substrate having a plurality of parallel display electrode pairs and a dielectric layer disposed on a display surface side, and The other substrate having a plurality of address electrodes and a phosphor is disposed on the back side, and further has a strip-shaped partition wall parallel to the address electrode at a position corresponding to each adjacent address electrode on the inner surface of the other substrate on the back side. The phosphor is provided between adjacent partitions including the side surfaces of the strip-shaped partition.

[0027]

In the unit light emitting area EU, almost the entire inner surface of the glass substrate 21 including the surface on which the address electrode A is formed becomes a light emitting surface of the phosphor 28, thereby enabling a high-luminance display.

After writing in line units, an erasing pulse PD having a very small width is applied to the display electrode Y, whereby a surface discharge occurs between the display electrodes X and Y, and the wall charges disappear in line units. However, at this time, the surface discharge is partially suppressed by selectively applying the electric field control pulse PC to the address electrode A according to the display content, and the surface discharge cell C to be lit is controlled.
Is kept in the write state.

In the erase address system for performing such selective erasure, no discharge occurs between the address electrode A and the display electrodes X and Y.
Does not accumulate in the phosphor 28 interposed between the wall charges, which is an obstacle to the address.

On the other hand, in the case of the so-called write address system, by accumulating charges on the address electrode A, addressing by the selective discharge pulse PA having a low peak value Va becomes possible. Then, prior to the address, the address electrode A
By accumulating the positive charges on the upper side, the potential relationship between the electrodes in the display cycle CH can be made advantageous in suppressing ion bombardment on the phosphor 28.

[0031]

FIG. 1 is a block diagram schematically showing a configuration of a plasma display device 100 according to a first embodiment of the present invention, and FIG. 2 is an exploded perspective view showing a cross-sectional structure of a main part of the PDP 1 of FIG. . In FIG. 2, components having the same functions as those in FIG. 10 are denoted by the same reference numerals regardless of the difference in shape, and the description thereof will be omitted or simplified.

First, in FIG. 2, the PDP 1 includes a pair of display electrodes X and Y and an address electrode A each of which has a unit light emitting area EU.
Is a surface discharge type PDP having a three-electrode structure.
Each of the display electrodes X and Y is composed of a strip-shaped transparent conductive film 41 and a strip-shaped metal film 42, and the glass substrate 1 on the display surface H side.
1 on the inner surface.

On the dielectric layer 17 covering the display electrodes X and Y, a strip-shaped partition wall 19 made of low-melting glass extending in a direction perpendicular to the display electrodes X and Y is provided. It is partitioned for each unit light emitting area EU in the extending direction of the display electrodes X and Y.

In the PDP 1, the sum of the widths of the display electrodes X and Y and the discharge gap (the width of the electrode pair) is determined by the arrangement of the electrode pairs in order to prevent interference of discharge between discharge lines (coupling of discharges). The value is selected to be 0.7 times or less of the pitch (corresponding to the length of the unit light emitting region EU in the direction orthogonal to the display electrodes X and Y, and the value is, for example, about 220 μm).

On the other hand, a strip-shaped partition 29 having substantially the same height as the above-described partition 19 and extending in the same direction is provided on the rear glass substrate 21. The size of the gap in the discharge space 30 is defined by the partition wall 19.

An address electrode A having a predetermined width is arranged between the partition walls 29 by, for example, pattern printing and baking of a silver paste. The phosphor 28 is provided so as to cover the inner surface of the glass substrate 21 except for the portion of the partition wall 29 which is in contact with the display surface H side and the vicinity thereof. That is, in the PDP 1, the phosphor 28 is provided on almost the entire wall surface of the discharge space 30 on the glass substrate 21 side in the unit light emitting region EU, including the side surface of the partition wall 29 and the surface of the address electrode A. .

In the PDP 1 having the above-described structure, the light emitting area is increased by an amount corresponding to the partition wall 29 and the address electrode A as compared with the conventional PDP 1j, so that high-luminance display is possible. Further, since the side surface of the partition wall 29 also serves as a light emitting surface, the viewing angle of display is large.

Next, in FIG. 1, the plasma display device 100 comprises a PDP 1 and a drive control system 2 for driving the PDP 1, and the PDP 1 and the drive control system 2
Are electrically connected to each other via a flexible printed wiring board (not shown).

The drive control system 2 includes an X-electrode drive circuit 141 and a Y-electrode drive circuit 14 corresponding to the display electrodes X and Y and the address electrode A, respectively, centering on the scan control section 110.
2, an A electrode drive circuit 143, an A / D converter 120, a frame memory 130, and the like.

Each of the drive circuits 141 to 143 is composed of a high-voltage switching element for discharging and a logic circuit for ON / OFF operation of the switching element. Driving voltage (discharge sustain pulse PS, write pulse PW, erase pulse PD,
And an electric field control pulse PC).

The AD converter 120 quantizes an analog input signal externally supplied as display information and converts it into image data which is a digital signal. Frame memory 13
0 stores image data for one frame output from the AD converter 120.

The scan control unit 110 controls each drive circuit 141 based on one frame of image data stored in the frame memory 130 by an erasure address method described later.
To 143.

Therefore, the scan control unit 110 includes a sustaining pulse generating circuit 111 for generating switching control signals corresponding to the respective pulses PS, PW, PD, and PC, a writing pulse generating circuit 112, and an erasing pulse generating circuit 11
3, and an electric field control pulse generation circuit 114 are provided.

The plasma display device 1 having the above configuration
In the case of 00, matrix display is performed by an erase address method of performing selective erase without causing selective discharge. FIG. 3 is a voltage waveform diagram showing a driving method according to the plasma display device 100.

In the plasma display apparatus 100, in the initial address cycle CA of the line display period T, first, as in the conventional case, the application of the discharge sustain pulse PS to the display electrode Y and the writing pulse PW Is applied. In the figure, the hatched lines attached to the sustaining pulse PS indicate that the pulse is selectively applied for each line. As a result, all the surface discharge cells C corresponding to one line enter the write state.

Subsequently, after the discharge sustaining pulse PS is alternately applied to the display electrodes X and Y to stabilize the writing state, at the end of the address cycle CA, the display electrodes Y and Y are applied.
, An erase pulse PD is applied to generate a surface discharge.

The erase pulse PD has a very small pulse width (1
２2 μs). For this reason, the wall charges disappear in line units due to the surface discharge by the erase pulse PD. However, in synchronization with the erasing pulse PD, a positive electric field control pulse PC having a peak value Vc is applied to the address electrode A corresponding to the unit light emitting region EU in the line to emit light.
In the figure, the hatched lines attached to the electric field control pulse PC indicate that the voltage is selectively applied to each unit light emitting region EU in one line.

In the unit light emitting region EU to which the electric field control pulse PC is applied, the electric field due to the erasing pulse PD is canceled out, whereby the surface discharge related to erasing is suppressed, and the wall charges necessary for display remain. That is, the surface discharge cell C to be lit
Is performed by selective erasure in a form that maintains the write state of

In such an address, since no discharge occurs between the address electrode A and the display electrodes X and Y, even if the fluorescent material 28 which is an insulator exists on the address electrode A as described above. On the other hand, the phosphor 28 does not accumulate wall charges, which are obstacles to the address. Therefore, correct display without erroneous lighting can be performed.

In the display cycle CH following the address cycle CA, the sustaining pulse PS is alternately applied to the display electrodes X and Y to cause the phosphor 28 to emit light. Then, the above operation is repeated every line display period T to display one screen.

FIG. 5 is a block diagram schematically showing a configuration of a plasma display device 200 according to a second embodiment of the present invention, FIG. 6 is a voltage waveform diagram showing a driving method of the plasma display device 200, and FIG. 7) to 7 (h) are cross-sectional views schematically showing charge accumulation states corresponding to the respective timings a to h in FIG. In FIG. 5, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The plasma display device 200 is the same as that shown in FIG.
And a drive control system 3 for driving the PDP 1 having the structure described above. The drive control system 3 mainly includes a scan control unit 210. The scan control unit 210 includes a sustaining pulse generating circuit 211 and a selective discharging pulse generating circuit 214.

In the plasma display device 200, matrix display is performed by a write address method.
That is, as shown in FIG. 6, at the time of line display, the discharge sustain pulse PS is selectively applied to the display electrode Y, and the address electrode corresponding to the unit light emitting region EU which emits light in the line according to the display content. A selective discharge pulse PA is selectively applied to A. Thereby, a counter discharge (selective discharge) occurs between the address electrode A and the display electrode Y.
Occurs, and the surface discharge cell C enters a predetermined address state. At this point, the address ends.

However, in this embodiment, prior to the address, a charge accumulation state for relaxing ion bombardment on the phosphor 28 is formed in the following procedure. First, the discharge sustaining voltage Vs of positive polarity is applied to the display electrodes X and Y at all times. That is, the pulse base potential of the display electrodes X and Y is set to a positive potential.

At the beginning of the address cycle CA, a write pulse PW whose potential becomes a predetermined negative potential (-Vw) is applied to the display electrode X to generate a surface discharge in line units.

As a result, as shown in FIG. 7A, a portion of the dielectric layer 17 on the display electrode X (hereinafter, referred to as “upper portion of the display electrode X”) has a polarity opposite to that of the applied voltage. Positive charges (discharge gas ions) as charges accumulate, and negative charges (electrons) accumulate in a portion of the dielectric layer 17 on the display electrode Y (hereinafter, this is referred to as “above the display electrode Y”). I do.
Further, due to the relative potential relationship between the address electrode A and the display electrodes X and Y, negative charges accumulate in the portion of the phosphor 28 covering the address electrode A facing the display electrode X, and Positive charges accumulate in the opposing portion of.

Next, the display electrode X is returned to the pulse base potential, and the display electrode Y is set to the ground potential (0 volt), for example.
And That is, the sustaining pulse P is applied to the display electrode Y.
S is applied. By the surface discharge at this time, as shown in FIG. 7B, the polarities of the charges on the display electrodes X and Y are switched. Further, the electrode on the address electrode A opposite to the display electrode X is replaced with a positive charge.

Subsequently, the sustaining pulse PS is applied to the display electrode X.
Is applied, the display electrode Y is returned to the pulse base potential, and the polarities of the charges on the display electrodes X and Y are switched again (FIG. 7C).

Then, the sustaining pulse PS is applied to the display electrode X.
Is applied (at a ground potential), the display electrode Y
The sustaining pulse PS is also applied to the display electrode X and the display electrode Y in order to return the display electrode X and the display electrode Y to the pulse base potential sequentially by shifting the timing by a minute time t1 of about 1 μs. As a result, surface discharge occurs when the display electrode X is returned to the pulse base potential. However, after a short time t1, the display electrodes X and Y have the same potential, so that the surface discharge is immediately stopped and the display electrodes X and Y are stopped. Once the charge on the top of the device disappears.

However, thereafter, the pulse base potential is a positive potential, and the display electrodes X and Y and the address electrodes A
7D, a negative charge is uniformly accumulated on the display electrode X and the display electrode Y, and a positive charge is uniformly accumulated on the address electrode A, as shown in FIG. Charges accumulate.

After the charge accumulation state has been formed for all the surface discharge cells C corresponding to one line in this way, at the end of the address cycle CA, selection is made between the display electrode Y and the address electrode A for addressing. Causes discharge.
Due to the facing discharge at this time, as shown in FIG.
Positive charges are accumulated on the upper part of the display electrode Y, and negative charges are accumulated on the upper part of the display electrode X and the address electrode A which have a positive potential relative to the display electrode Y.

In the subsequent display cycle CH, the sustaining pulse PS is alternately applied to the display electrodes X and Y to cause the phosphor 28 to emit light. At this time, a surface discharge occurs every time one of the display electrodes X and Y falls to a negative potential with respect to the pulse base potential. At the time of the surface discharge, the capacitive coupling between the display electrodes X and Y occurs. The address electrode A in the state has a relatively positive potential with respect to the display electrodes X and Y that have fallen to the negative potential. For this reason, the movement of the positive charges (ions) to the address electrode A side is suppressed, and the ion bombardment on the phosphor 28 is reduced.

In the display cycle CH, the upper part of the display electrodes X and Y and the address electrode A is shown in FIGS.
As shown in (h), the polarities of the charges are switched. In the write address method, the address is terminated by the discharge at the rising edge of the selection discharge pulse PA. Therefore, unlike the case of using the erase address method in which the address is terminated by the self-erasing discharge immediately after the selection discharge pulse PA, the address on the address electrode A is different. There is no adverse effect due to accumulation of wall charges on the memory cells, and the address becomes stable even when the peak value Va of the selective discharge pulse PA is small due to the wall charges.

According to the above-described embodiment, the PDP 1 has the phosphors 28 on the side surfaces of the partition walls 29 as well as on the surface of the glass substrate 21, so that it is possible to increase the display brightness and improve the viewing angle.

That is, as shown in FIG.
PDP in which is disposed on a glass substrate 21 on the back side
In 1, when the phosphor 28 is also provided on the side surface of the partition wall 29 (shown by a solid line in the figure), when the phosphor 28 is provided only on the surface of the glass substrate 21 (shown by a broken line in the figure) )
As compared with, the luminance in front of the display surface H (viewing angle 0 °) is increased about 1.35 times. In addition, a luminance equal to or higher than that of the front can be obtained over a wide range (viewing angle is in a range of −60 ° to + 60 °).

Focusing particularly on the viewing angle dependency of the luminance, as shown in FIG. 9, the reflection type PDP 1 in which the phosphor 28 is also provided on the side surface of the partition wall 29, It is superior to a transmissive PDP arranged on the substrate 11.

In the above-described embodiment, a plurality of unit light emitting areas EU are associated with one pixel of the matrix display, and the phosphors 28 having different emission colors are assigned to the unit light emitting areas EU.
Is provided, multicolor or full-color display can be performed. Further, it is also possible to divide the line display period T and appropriately set the number of surface discharges in each divided period to perform gradation display.

In FIG. 3, writing is performed collectively on a plurality of lines, and thereafter, selective erasing (selective holding of a writing state by an erasing pulse PD and an electric field control pulse PC) is performed for each line, thereby achieving high-speed display. Can be achieved. In FIG. 6 as well, the above-described charge accumulation state is formed collectively for a plurality of lines, and thereafter, addressing is performed for each line in order, so that display can be speeded up.

In the above-described embodiment, a transmissive PDP may be used instead of the reflective PDP 1 depending on the application. The peak value, pulse width, and application timing of each pulse can be changed as appropriate. For example, in FIG. 6, the pulse base potential may be set to the ground potential, and a negative voltage may be applied to the display electrodes X and Y as the sustaining pulse PS.

[0070]

According to the present invention, a high-definition and bright display can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of a plasma display device according to a first embodiment of the present invention.

FIG. 2 is an exploded perspective view showing a cross-sectional structure of a main part of the PDP of FIG.

FIG. 3 is a voltage waveform diagram showing a driving method according to the plasma display device of FIG. 1;

FIG. 4 is a plan view schematically showing an electrode configuration of a surface discharge type PDP.

FIG. 5 is a block diagram schematically showing a configuration of a plasma display device according to a second embodiment of the present invention.

6 is a voltage waveform diagram showing a driving method according to the plasma display device of FIG.

7 is a cross-sectional view schematically showing a charge accumulation state corresponding to each timing in FIG.

FIG. 8 is a graph showing a relationship between a viewing angle and a surface average luminance.

FIG. 9 is a graph showing a relationship between a viewing angle and relative luminance.

FIG. 10 is an exploded perspective view showing a sectional structure of a portion corresponding to one unit light emitting region of a conventional surface discharge type PDP.

FIG. 11 is a voltage waveform diagram showing a driving method suitable for a conventional PDP.

[Explanation of symbols]

 100, 200 Plasma display device 1 PDP (surface discharge type plasma display panel) 2, 3 Drive control system 30 Discharge space 11, 21 Glass substrate (substrate) X, Y Display electrode 17 Dielectric layer A Address electrode 28 Phosphor PW writing Pulse PS Sustain sustain pulse PD Erase pulse PC Electric field control pulse PA Selective discharge pulse

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinji Metal fittings 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) H01J 11/00 H01J 11/02

Claims (6)

(57) [Claims] To 1. A on the inner surface of one substrate of the substrate pair sandwiching a discharge space, it has a dielectric layer to the covering multiple electrode pairs and those consisting of parallel display electrodes together, on the inner surface of the other substrate to a plurality of address electrodes and a plasma display panel of a surface discharge type matrix display system comprising a provided a phosphor so as to cover them crossing the display electrodes, corresponding to the display electrode pair lines after writing to all the surface discharge cells of the inner display electrodes corresponding to the line
For one display electrode in a pair , the other display electrode
And causing discharge performed indicia <br/> pressurized erase pulse for erasing the charge between, and parallel with this, the surface discharge cells to leave the charge
For the address electrodes corresponding to
Consumption of one line by applying an electric field control pulse for canceling an electric field due to the erase pulses occurring photocells
A plasma display apparatus characterized by comprising a drive control system of the configured erasure addressing method to perform addressed. To 2. A on the inner surface of one substrate of the substrate pair sandwiching a discharge space, it has a dielectric layer to the covering multiple electrode pairs and those consisting of parallel display electrodes together, on the inner surface of the other substrate a plurality of address electrodes crossing the display electrodes and those
A plasma display panel of a surface discharge type matrix display system comprising a phosphor which is arranged to accumulate charge between the address electrode and the discharge space, all surface discharge corresponding to the display electrode pairs About cell
Collectively apply a voltage to form a predetermined accumulation state of wall charges.
Then, a selective discharge for writing is generated in one of the display electrodes of the display electrode pair and each of the address electrodes.
Write one line by applying each pulse
A plasma display device comprising: a drive control system of a write address system configured to sequentially perform an address. 3. An inner surface of one of a pair of substrates sandwiching a discharge space.
Above, and a plurality of electrode pairs ing of parallel display electrodes together
Having a dielectric layer covering them, on the inner surface of the other substrate
A plurality of address electrodes and a plurality of address electrodes intersecting with the display electrodes.
Matrix display method having a charge storage surface made of a light body
Type surface discharge type plasma display panel and writing
A drive control system of an address system , wherein the drive control system of the write address system collectively generates a surface discharge for all the surface discharge cells corresponding to the display electrode pairs , thereby accumulating the charge of the phosphor. After accumulating positive charges on the surface and accumulating negative charges on the dielectric layer, the relative potential of the selected display electrode of the display electrode pair to the other display electrode becomes negative. Like
In conjunction with application of a pulse, to the address electrodes, by the relative potential between those the one display electrodes to apply a pulse for writing so that the positive potential, is selected
A plasma display device configured to perform addressing for each line . 4. An inner surface of one of a pair of substrates sandwiching a discharge space.
Above, a plurality of electrode pairs consisting of display electrodes parallel to each other and
Having a dielectric layer covering them, on the inner surface of the other substrate
A plurality of address electrodes intersecting with the display electrodes;
A phosphor interposed between the address electrode and the discharge space;
Surface discharge type plasma display with matrix display
Spray panel and drive control system of write address method
And the drive control system of the write address system is provided for each line.
Prior to the address operation, all addresses corresponding to the display electrode pairs
All the surface discharge cells must be discharged at once.
Potential of one display electrode is relative to the address electrode.
A positive polarity pulse is applied between the display electrode pair.
After that, all the surface discharge cells corresponding to the display electrode pairs are fired.
Apply a voltage to erase the charge caused by the generated discharge
A plasma display apparatus characterized by comprising configured to that. 5. The plasma display device according to claim 4, wherein the drive control system of the write address system performs the erase operation .
After the application of the voltage, the relative potential between one display electrode and the other display electrode becomes a negative potential,
With selectively applying pulses to the display electrodes, to said address electrodes, a pulse such that the relative potential between the corresponding address electrodes opposite to perform address discharge display electrodes has a positive potential a plasma display apparatus characterized by including a you apply configuration further. 6. The plasma display device according to claim 1, wherein the matrix display type surface discharge type plasma display panel has a plurality of parallel display electrode pairs and a dielectric layer. One substrate is arranged on the display surface side, and the other substrate having a plurality of address electrodes and phosphors is arranged on the back side, and further corresponds to between the adjacent address electrodes on the inner surface of the other substrate on the back side. A plasma display device having a strip partition parallel to the address electrode at a position, and wherein the phosphor is provided between adjacent partitions including side surfaces of the strip partition.