JP3259627B2 - Scanning line converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a scanning line conversion device in electronic equipment mainly for a liquid crystal display.

[0002]

2. Description of the Related Art Conventionally, a scanning line converter has been used to display an image on a display element such as a liquid crystal panel having a number of pixels different from the number of pixels of an input signal. An example of the operation for performing the scanning line conversion is an example of a digital video processing operation shown in “Application of Digital Signal Processing (page 271)” (edited by the Institute of Electronics, Communication and Communication Engineers). Hereinafter, a conventional scanning line conversion device will be described with reference to the drawings.

FIG. 8 is a system diagram of a conventional scanning line converter in the case of reduction, and FIG. 9 is a diagram showing an interpolation reduction operation. In FIG. 8, 20 is a reference counter, 21 is a comparator, 22 is a register, 23 is an adder, 24 is an interpolation circuit, 25 is a memory,
26 is an address generation circuit. FIG. 9 shows the operation principle when the reduction ratio is 0.6. In FIG. 9, short vertical lines of the input signal represent sample values of the original image signal, and black dots are values that need to be newly created by interpolation. First, the reciprocal of the reduction ratio SH = (standard screen size) / (size to be reduced) is input from, for example, a microcomputer. In this example, SH = 1 / 0.6 = 1.67, which means that a new sample value is created every 1.67 times the original sample interval. This SH is applied to a ΣSH circuit 27 including a register 22 and an adder 23. The SH circuit 27 performs integration in the SH step every time a coincidence pulse appears in the output of the comparator 21.

[0004] The integrated output, ie, the SH circuit 27
Is compared with the output of reference counter 20, and when the values are equal, the comparator generates a coincidence pulse.
This coincidence pulse indicates the position of the sample point to be interpolated. On the other hand, the decimal part of ΣSH is used as an interpolation coefficient at that time. The sample value obtained as a result of the interpolation is written to a predetermined position on the main memory according to the write address generated by the counter from the coincidence pulse.

[0005] In this manner, by writing new pixel data into the memory every time a coincidence pulse is generated, a reduced image can be formed on the memory. By performing the -A conversion, a reduced analog image signal can be obtained. In the above example, the example of horizontal reduction has been described, but the same applies to the case of vertical reduction, and the clock is a pulse synchronized with the horizontal synchronization signal.

In order to convert the number of samples in this manner, it is necessary to calculate sample points and interpolation coefficients for interpolation based on a reference clock (or horizontal synchronization pulse), and to form a data string by a memory. .

Further, for example, VGA (Video Gr)
aphs Array) standard (standard) to XGA (X
tended Video Graphics Arr
ay) Considering the case of converting to the standard (standard) and displaying it on a liquid crystal panel compatible with the XGA standard, the number of horizontal dots is 800 and the number of horizontal effective dots is 640 in the case of the VGA standard. Since the number of horizontal effective dots of the XGA standard is 1024, the number of horizontal samples is 1.6 times (1024/64).
By setting 0), a signal of the VGA standard can be displayed on a liquid crystal panel compatible with the XGA standard.

On the other hand, VESA (Video Select)
ronics Standards Associate
On), there is also a signal of 832 horizontal dots and 640 horizontal effective dots. When this signal is displayed on, for example, an XGA standard compliant liquid crystal panel, the conversion of the number of horizontal effective dots is simply performed, that is, 1.6 times (= 1024/640), and the number of horizontal dots is 1331.2 (= 832 × 1). .6), and the display becomes odd on a liquid crystal panel with a fractional part. Further, since the number of horizontal dots is larger than the standard XGA of 1280, a part of the image may not be able to be displayed because the specifications of the liquid crystal panel are not satisfied. For this reason, a method is used in which only the effective screen of the converted signal is once written to the memory, and only the effective area is read from the memory with a clock that allows the reading side to see the specifications of the liquid crystal panel. At this time, a method is generally known in which the clock on the memory write side is synchronized with the input signal, while the clock on the read side is generated asynchronously with the input signal.

[0009]

As described above, when performing the scanning line conversion flexibly corresponding to the liquid crystal panel, if the number of scanning lines is converted in accordance with the number of horizontal effective dots, the converted number of scanning lines is reduced. There was a problem that it did not fall within the limitations of the display panel.

When the frame frequency is converted using a memory, the input signal and the signal to be displayed on the liquid crystal panel are completely asynchronous, so that a frame jump occurs in the effective screen area, resulting in a non-continuous operation. There was a problem that is displayed in.

[0011]

In order to solve the above-mentioned problems, a scanning line conversion apparatus according to the present invention comprises a synchronization separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal from an input signal, and an output from the synchronization separation circuit. A first PLL circuit that generates a first clock in synchronization with a horizontal synchronization signal, a second PLL circuit that generates a second clock in synchronization with the horizontal synchronization signal, and a scanning line of an input signal. A scanning line conversion circuit for converting the data, and generating an interpolation timing and an interpolation coefficient for performing horizontal and vertical interpolation in the scanning line conversion circuit, and a horizontal line having a plurality of horizontal frequencies after the scanning line conversion. It is characterized by including a timing generation circuit for generating a synchronization signal, and a memory for converting a frame frequency of an output of the scanning line conversion circuit.

The present invention has been made in view of the above problems, and provides a scanning line conversion apparatus capable of displaying a picture without disturbing the screen even if the scanning line conversion is performed according to the number of dots in the horizontal direction.

Further, the present invention provides a scanning line conversion apparatus in which an input signal and a signal to be displayed on a liquid crystal panel are completely asynchronous, so that a frame is skipped in an effective screen area and is not displayed discontinuously. Is what you do.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A scanning line converter according to a first aspect of the present invention provides a timing of a horizontal synchronizing signal in an effective screen area and a horizontal scanning period in a blanking period when converting the number of scanning lines of an input signal. It is characterized in that the timing of the synchronization signal is made different, and has an effect that scanning line conversion that can be displayed on a liquid crystal panel without frame frequency conversion can be performed.

According to a second aspect of the present invention, there is provided a scanning line converting apparatus for synchronizing a horizontal synchronizing signal and a vertical synchronizing signal from an input signal, and synchronizing with a horizontal synchronizing signal which is an output from the synchronizing signal. A first PLL circuit for generating a first clock, a second PLL circuit for generating a second clock in synchronization with the horizontal synchronization signal, and a scan for converting a scan line of the input signal. A line conversion circuit, and generating an interpolation timing and an interpolation coefficient for performing horizontal and vertical interpolation in the scanning line conversion circuit,
It has a timing generation circuit that generates a horizontal synchronization signal with multiple horizontal frequencies after scanning line conversion, and can perform scanning line conversion that can be displayed on a liquid crystal panel without frame frequency conversion. Having.

In a scanning line conversion apparatus according to a third aspect of the present invention, when converting the number of scanning lines of an input signal, the total number of clocks per frame before the scanning line conversion is set to m, and the number of clocks after the scanning line conversion is changed. The total number of clocks per frame is defined as n, and the frame frequency is converted using a clock frequency such that an integer multiple of the clock number n before the scan line conversion is an integer multiple of the clock number m after the scan line conversion. This has the effect that scanning line conversion can be performed without skipping frames and displaying non-continuously.

According to a fourth aspect of the present invention, there is provided a scanning line conversion apparatus comprising: a synchronization separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal from an input signal; and a horizontal synchronization signal output from the synchronization separation circuit. A first PLL circuit that generates a first clock in synchronization with the first clock, a second PLL circuit that generates a second clock in synchronization with the horizontal synchronization signal,
A scanning line conversion circuit for converting a scanning line of the input signal, and an interpolation timing and interpolation coefficient for performing horizontal and vertical interpolation in the scanning line conversion circuit; And a memory for converting the frame frequency of the output of the scanning line conversion circuit, and a frame is skipped, which is displayed non-continuously. This has the effect that scanning line conversion can be performed without the need for such a conversion.

An embodiment of the present invention will be described below with reference to FIGS. (Embodiment 1) FIG. 1 shows a scanning line converter according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a synchronization separation circuit, 2 denotes a first PLL circuit for generating a first clock in synchronization with an input horizontal synchronization signal, and 3 denotes a second PLL circuit in synchronization with an input horizontal synchronization signal. , A scanning line conversion circuit for converting the number of scanning lines of the input signal, and 5 an interpolation coefficient and interpolation for performing a sample interpolation in the scanning line conversion circuit 4. A timing generation circuit that generates timing and generates a synchronization signal for driving a display device such as a liquid crystal panel.

FIG. 2 is an internal configuration diagram showing an example of the inside of the timing generation circuit. In FIG. 2, 6 is clock 1
(CK1) is a first counter that divides the frequency by an arbitrary frequency division ratio to generate an HD signal; 7 is a horizontal interpolation circuit that generates an interpolation coefficient and timing used in horizontal interpolation using clock 1 (CK1); Is a second counter for generating an HD2 signal by dividing the clock 2 (CK2) by an arbitrary dividing ratio;
Reference numeral 9 denotes a vertical interpolation circuit that generates an interpolation coefficient and timing used in vertical interpolation using a clock 2 (CK2). 10 denotes a first H that counts the clock 2 (CK2) and generates a first horizontal synchronization signal a. Counter, 11 is clock 2
To generate a second horizontal synchronizing signal b.
H counter 12 has an output signal a of H counter 10 and H
A selector 13 for selecting the output signal b of the counter 11 and a V counter 13 for controlling the selector 12 by counting the horizontal synchronizing signal c output from the selector 12. FIG. 3 is a diagram showing the relationship between the synchronization signal and the number of samples and the number of lines.

Next, an operation example of the scanning line conversion apparatus of the present invention will be described. An input signal is input to the sync separation circuit 1, and a horizontal sync signal (Hsync) and a vertical sync signal (Vsync) are input.
Is output separately. The PLL circuit 2 reproduces the clock 1 (CK1) based on Hsync. In the PLL circuit 2, the frequency of the clock 1 is determined by setting the frequency division ratio by the first counter 6 in the timing generation circuit 5. For example, if the frequency division ratio is 800 in the case of the VGA standard, the dot clock on the signal transmission side can be reproduced. Similarly, the PLL circuit 3 generates the clock 2 set by the second counter 8. For example, when converting a signal of the VGA standard, which is an input signal, the frequency division ratio of the counter 2 is set to 1280 as in the case of the XGA standard.

In the horizontal interpolation circuit 7 and the vertical interpolation circuit 9, VG
An interpolation coefficient and timing for converting from the A standard to the XGA standard are generated, and the scanning line conversion circuit 4 converts the number of scanning lines according to the generated interpolation coefficient and timing. At this time, the input signal is converted as shown in FIG. 3 (2) showing the relationship between the number of samples and the number of lines of clock 2 in FIG. 3 (1) showing the relationship between the number of samples and the number of lines of clock 1. . That is, since the number of horizontal dots is converted from 800 dots to 1280 dots (1.6 times), the number of lines in the vertical direction is also 1.6 times 5 times.
It is converted from 25 lines to 840 lines. By the way, since the standard XGA signal has 806 vertical lines, there is no allowance in the timing specification of, for example, a liquid crystal panel for displaying an image, and there is a signal which cannot be displayed with a signal of 840 lines.

The output signal a of the H counter 10 is
80, the output signal b of the H counter 11 is set to 2304, the number of lines is counted by the V counter 13, and the output signals a and b are switched at the boundary of 768 lines. Therefore, the timing of the horizontal synchronization of the effective line is not changed, and the timing of the horizontal synchronization in the vertical blanking period is set to, for example, FIG.
As shown in (3), the synchronization signal is switched so that the number of horizontal synchronization dots is 2304 for 40 lines (808-768) in the vertical blanking period. In this way, the number of vertical lines becomes 808, and X
Since it is similar to the 806 lines of the GA standard, it can be projected on a liquid crystal panel. That is, the image can be displayed on the display device without changing the frame frequency and without using the memory. In the present embodiment, H
Although an example in which two counters are used has been described, by using more than two counters, it is possible to switch the timing of horizontal synchronization in various ways and perform the indication.

According to this configuration, by providing a plurality of horizontal synchronization signals in one frame, an image can be displayed on a display device having a small timing margin without converting the frame frequency.

(Embodiment 2) Next, another embodiment of the present invention will be described with reference to FIG. 4, FIG. 5, FIG. 6, and FIG. Note that the same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted. In FIG.
14 is a memory. FIG. 5 is a diagram showing the internal configuration of the timing generation circuit in FIG. 4. In FIG. 5, reference numeral 15 denotes a third H counter, 16 denotes a fourth H counter, and 17 denotes a fourth H counter.
Is a second selector and 18 is a second V counter. 6 and 7 are diagrams showing the conversion of the frame frequency.

In this embodiment, when the timing specification of the display device is not satisfied, it is general to use a memory to convert the frame frequency. In this case, as shown in FIG. If the write clock and the read clock are performed completely asynchronously, a frame before conversion is skipped in the screen. That is, in FIG. 6A, if the frequency of the calling clock is slightly higher than the write clock, the read address passes the write address during writing as in # 1 (first frame). the first#
Although 1 is being read, the signal of the frame immediately before that frame is called out. For this reason, there is no problem in the case of a still image, but in the case of a moving image, a frame is skipped in an effective screen, which appears as an obstruction.

For this reason, as shown in FIG. 6 (2), the clock relationship between the frame before conversion and the frame after conversion is set to a clock frequency that completes with an integer ratio, and the horizontal synchronization frequency and vertical synchronization frequency after conversion. By doing so, jumping in the screen can be prevented. FIG.
In the example of (2), the frame frequency is converted from 3 frames to 4 frames.
This is an example of converting to a frame. That is, the total number of clocks in one frame before conversion is m. For example, if there are 2,000 horizontal dots and 830 vertical lines, m = 2000 * 830 = 1660000 [clock]. Here, the timing specification of the liquid crystal panel is such that the maximum number of horizontal dots is 1700 dots and the maximum number of vertical lines is 8
If there are 32 lines, the maximum allowable number of clocks per frame of the liquid crystal panel is 1700 * 832 = 1414400 [clocks], and no matter how many horizontal synchronization signals are provided in one frame as shown in the first embodiment. The specifications of the liquid crystal panel cannot be satisfied. Therefore, only the effective screen area of the signal before conversion is written into the memory, and only the effective screen area is read out for calling, and the frame frequency is converted. The total number of clocks in one frame after conversion is n.
At this time, n is selected such that the ratio of n and m is an integer.
For example, three frames before conversion and four frames after conversion have the same time. That is, since 3 * m = 4 * n, n = 3/4 * m = 1245000 [clock]. At this time, the maximum allowable clock number of the liquid crystal panel is satisfied. Thereafter, the number of horizontal dots and the number of vertical lines after the conversion are determined. In this case, as described in the first embodiment, the number of horizontal dots and the number of vertical lines can be easily determined by providing a plurality of horizontal synchronization signals in one frame. For example, the number of horizontal dots 1558 is 797 lines, and two lines thereafter are 1637 dots. We are satisfied with the specifications of the LCD panel.

In the reading of the memory, only the effective screen area is read according to the number of dots determined as described above. FIG. 7 shows the relationship between horizontal dots and horizontal lines before and after conversion and the relationship between memory control.

In this case, although the frame frequency conversion is performed,
By making the write clock and the read clock the same, the jump between the write address and the read address does not occur. By doing so, there is no interference caused by skipping frames in the effective screen. Further, the clocks for writing and reading the memory can be made the same, which is less than when the clock recovery circuit is asynchronous.

The total number m of clocks before conversion is determined by the H counters 10 and 11 and the V counter 13, and the total number n of clocks after conversion is determined by the H counters 15 and 16 and the V counter 18.

[0030]

As described above, according to the scanning line conversion apparatus of the first invention, the number of horizontal effective dots before conversion is switched by switching the horizontal synchronization signal having a plurality of horizontal frequencies within the same frame. The number of lines is not converted according to the ratio of the number of horizontal effective dots after the conversion, that is, the conversion rate in the horizontal direction and the conversion rate in the vertical direction can be different, and as a result, an image is missing in the display screen. The scanning line can be converted without any need.

According to the second aspect of the present invention, it is possible to perform a scanning line conversion in which a frame is skipped and is not displayed discontinuously.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a scanning line conversion device according to a first embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a timing generation circuit according to the present invention.

FIG. 3 is a diagram showing a relationship between a synchronization signal and the number of samples and the number of lines according to the present invention;

FIG. 4 is a circuit diagram of a scanning line conversion device according to a second embodiment of the present invention.

FIG. 5 is a timing generation circuit diagram of a scanning line conversion device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing conversion of a frame frequency according to the present invention.

FIG. 7 is a diagram showing conversion of a frame frequency according to the present invention.

FIG. 8 is a diagram showing a configuration of a conventional scanning line conversion device.

FIG. 9 is a diagram illustrating an operation in a conventional scanning line conversion circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization separation circuit 2 PLL1 3 PLL2 4 Scanning line conversion circuit 5 Timing generation circuit 6 Counter 1 7 Horizontal interpolation circuit 8 Counter 2 9 Vertical interpolation circuit 10 H counter 1 11 H counter 2 12 selector 13 V counter 14 Memory

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshikuni Shindo 1-1, Matsushita-cho, Ibaraki-shi, Osaka Matsushita Avicy Technology Co., Ltd. (56) References JP-A-8-129356 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/46 H04N 5/66 H04N 7/01

Claims (1)

(57) [Claims] 1. A horizontal synchronizing signal and a vertical synchronizing signal from an input signal.
And a synchronization separation circuit for separating the synchronization signal.
The first clock is synchronized with the horizontal synchronizing signal
A first PLL circuit for generating the horizontal synchronizing signal,
Second PLL circuit for generating second clock in synchronization
Scanning line conversion for converting the number of scanning lines of the input signal.
Conversion circuit, the first clock and the previous second clock
To perform horizontal and vertical interpolation.
Timing for generating a signal and outputting the signal to the scanning line conversion circuit
A timing generation circuit, wherein the timing generation circuit is effective.
Horizontal sync signal timing and blanking in screen area
Output a signal that changes the timing in the period.
Characteristic scanning line converter.