JP3251670B2 - PCM audio data processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCM audio data processing system, and more particularly to a PCM audio data processing system in which PCM audio data is transferred by DMA transfer.

[0002] In a so-called multimedia personal computer or other audio processing apparatus, audio is recorded, processed, edited, and a voice message is notified to a user when necessary.

As a method of processing audio data in such an apparatus, a PCM (pulse code modulation) recording / reproducing method is used, and as a PCM audio data transfer method, a DMA (direct memory access) method is used. Used.

[0004]

2. Description of the Related Art In the case of a recording operation, recording data is transferred from an ADC (analog-digital converter) to a memory buffer (main memory) of a host, and in the case of reproduction, reproduction information is transferred from the memory buffer of the host to a DAC (digital-analog converter). Transfer to At this time, DMA transfer is used to allow the host system to perform other tasks in parallel. The number of transfer bytes that can be transferred at one time is DMA
The transfer destination of the recorded data is indicated by the transfer byte counter of the C (DMA controller), and the storage source address of the reproduced data is indicated by the byte address of the DMA controller. The number of transfer bytes is limited by the number of bits of the transfer byte counter, and the transfer ends when the byte counter becomes 0. At the end of the transfer, a data update operation occurs.

For such an update operation, for example, in the case of a reproduction operation, the following audio data is prepared in advance in the memory buffer of the host before the end of the transfer, and immediately after the transfer end notification is received, Required to specify data. On the other hand, the sampling frequency of PCM is 11 KHz
If the sampling frequency is in the range of ~ 44 KHz, the sampling period is 90
２２22 μs. Therefore, it is necessary to complete the update operation of the next information at the latest within 22 μs after the notification of the transfer end, but this is almost impossible with a general host system.

Therefore, as shown in FIG. 5, the DMA controller 8 usually has an auto-initialize function for automatically processing this update operation. When starting the DMA transfer, the DMA controller 8 transfers the base address BA and the base count BC stored in its internal register to a predetermined counter. As a result, the base address BA becomes the current address CA, and the base count B
C is the current count CC.

Next, for example, in the case of a reproducing operation, the DMA controller 8 DMA-transfers the PCM audio data in the main memory 7 to the buffer memory 5 on the DAC side. At this time, in the main memory 7, data transfer is performed sequentially starting from the current address CA. Each time 1-byte data is DMA-transferred from the main memory 7, the current count CC is reduced by -1 and it is determined whether or not CC = 0. If CC ≠ 0, DMA transfer is repeated and C
If C = 0, the transfer ends.

[0008] With the end of the transfer as a trigger, the DMA controller 8 transfers the base address BA and the base count BC to predetermined counters again and sets them as the current address CA and the current count CC, respectively.

[0009]

In the above-mentioned auto-initialization function of the DMA controller 8, the base address BA and the current address CA, and the base count BC and the current count CC cannot be updated separately. That is, while the current address CA and the current count CC are used for data transfer,
The base address BA and the base count BC cannot be updated.

Therefore, the same base address BA and the same base count BC are always stored as the current address CA and the current count CC with the transfer end as a trigger. Further, in this case, the following PCM audio data cannot be written in the area of the main memory 7 during the DMA transfer. For this reason, it is not possible to continuously reproduce or record audio data larger than the size of the main memory 7 (the size of the area that can be obtained for writing PCM audio data in the main memory 7) or the size of the buffer memory 5. Did not. In other words, when trying to reproduce or record audio data of such a size, the audio is always interrupted.

On the other hand, the current address CA and the current count CC can be updated by updating the base address BA and the base count BC after the completion of the transfer. In this case, the following PCM audio data can be expanded to another address of the main memory 7,
It takes several tens μs from the end of the previous transfer to the resumption of the transfer (2
Longer than 2 μs). For this reason, as described above, it has been impossible to continuously reproduce or record audio data having a predetermined volume or more.

Some of the latest DMA controllers have improved auto-initialization functions so that the base address BA and the current address CA and the base count BC and the current count CC can be updated separately. That is, even when the current address CA and the current count CC are being used for data transfer, the base address BA and the base count BC can be updated. Therefore, the following PCM audio data is developed at another address of the main memory 7 and can be continuously DMA-transferred (can be continuously reproduced or recorded as audio).
However, models equipped with such a DMA controller require complicated hardware and are generally expensive (expensive). Further, since the DMA controller is usually mounted on a main body board of a personal computer or the like, it is not possible to replace only the DMA controller, and the D for the auto-initialization function described above.
In a personal computer or the like provided with the MA controller 8, the above-mentioned problem still remains.

This problem does not exist at the time of selling such a personal computer, but the size of audio data, which was initially considered to be sufficient, has become insufficient due to the development of multimedia communication and the like. It has occurred.

Another object of the present invention is to provide a PCM audio data processing system capable of recording / reproducing continuous audio.

[0015]

FIG. 1 is a block diagram showing the principle of the present invention, and shows a data processing apparatus according to the present invention. In FIG. 1, a main memory 7 and an external storage device 9 store PCM audio data. The buffer memory 25 temporarily stores PCM audio data for audio input / output. DM
The A controller 8 has a main memory 7 and a buffer memory 2
Data transfer control means for transferring PCM voice data to and from PCM voice data.

The interrupt signal generating means 36 generates an interrupt signal every 1 / n of the transfer data amount set in the DMA controller 8. The data transfer means 11 transfers PCM audio data between the main memory 7 and the external storage device 9 according to the interrupt signal.

The interrupt signal generating means 36 generates an interrupt signal every time the transfer amount of PCM audio data between the main memory 7 and the buffer memory 25 reaches 1 / n of the transfer data amount. Reference numeral 11 transfers the PCM audio data to and from the external storage device 9 in the area of the main memory 7 where the transfer of the PCM audio data to and from the buffer memory 25 has been completed in response to the interrupt signal.

[0018]

FIG. 1 shows a continuous sound reproduction process when n = 2. It should be noted that in FIG.
However, the number is actually one, and two identical ones are shown for convenience of explanation.

In the DMA controller 8, the transfer amount of the PCM voice data is set as a base count BC. Therefore, the interrupt signal generation means 36 calculates 1 /
An interrupt signal is generated every 2 (1 / 2BC).

The DMA controller 8 has a main memory 7
Transfer (DMA transfer) of the PCM audio data from the buffer memory 25 to the buffer memory 25 is started from the current address CA obtained by transferring the base address BA (shown in the figure).

This DMA transfer is performed in half of the main memory 7.
That is, when the processing is performed up to 1 / 2BC (end in the figure), the interrupt signal generating means 36 detects this and generates an interrupt signal to notify the data transfer means 11.

In response, the data transfer means 11 writes PCM audio data from the external storage device 9 to the area X of the main memory 7 where the DMA transfer has been completed (shown in the figure).

At this time, the DMA controller 8
Performs a DMA transfer to the buffer memory 25 for the remaining area Y in the main memory 7. When the DMA transfer for this area Y ends (end in the figure), an interrupt signal is generated again. Thereby, writing of data from the external storage device 9 for the area Y by the data transfer means 11 (shown in the figure) and DMA transfer of the area X by the DMA controller 8 to the buffer memory 25 (FIG. ) Are performed simultaneously. Here, the data to be DMA-transferred is data written in the processing shown in FIG.

By repeating the above, continuous audio data can be transferred to the DM while using the same area of the main memory 7 (without updating the base address BA etc. separately).
A-transfer and continuous playback or recording as voice.

The DMA controller 8 uses a conventional DMA controller, while the interrupt signal generating means 36 (which can be constituted by a simple counter) and the data transfer means 11 (which can be realized by a simple modification of an existing program). By simply adding, continuous sound reproduction and recording can be performed.

[0026]

FIG. 2 is a block diagram of an embodiment, showing the configuration of a data processing device or a personal computer device of the present invention.

This data processing device has the following configuration for processing audio data. At the time of voice recording, the analog voice input obtained through a microphone (not shown)
A DC (analog / digital converter) 1 converts the signal into a digital signal (PCM audio data) and stores it in a buffer memory 2. The buffer memory 2 is a timing fine adjustment buffer with the ADC 1. The data in the buffer memory 2 is
The data is transferred to the main memory 7 via the data bus of the CPU (Central Processing Unit) 10.

At the time of audio reproduction, data on the main memory 7 is transferred to the buffer memory 5 via the data bus. Data in buffer memory 5 (PCM audio data)
(Digital / Analog Converter) 4 converts this into an analog signal and outputs it as an analog audio output via a speaker (not shown) or the like. Buffer memory 5 is D
This is a timing fine adjustment buffer for AC4.

The buffer memories 2 and 5 in FIG. 2 are shown as a buffer memory 25 in FIG. Data transfer (DMA transfer) between the buffer memories 2 and 5 and the main memory 7 is performed by the DMA controller 8.

A part of the area of the main memory 7 is used as an area (buffer) for DMA transfer between the main memory 7 and the buffer memories 2 and 5. The size of this area is the same as the number of transfer bytes described later, as shown in the figure.

When an interrupt signal is generated every 1 / n, the buffer area is divided into n parts.
In this embodiment, n = 2, and a region to be a buffer is divided into two regions of X and Y and used.

The PCM audio data on the main memory 7 is
At the time of recording, the data is transferred to the external storage device 9 via the data bus, and at the time of reproduction, the data is transferred from the external storage device 9 via the data bus. This data transfer is performed by the data transfer means 11.

The external storage device 9 comprises, for example, a magnetic disk (hard disk) device and stores various data, for example, PCM audio data. The data transfer means 11 comprises a processing program for transferring data between the main memory 7 and the external storage device 9 and is started up in advance and used for
A predetermined process (data transfer) is performed after each interrupt signal is generated. This processing program can be prepared, for example, in the form of a card to be inserted into a personal computer. Therefore, there is no need to change hardware, and the present invention can be easily applied to existing personal computers. The data transfer means 11 may be a separate channel of the plurality of DMA controllers 8 to be described later or a continuous movement command of the CPU 10.

A plurality of DMA controllers 8 are provided for sub-channels "0" to "2". For example, the sub-channel “0” corresponds to the main memory 7 and the memory buffers 2 and 5
DMA transfer between the main memory 7 and the external storage device 9 is performed on the sub-channel "1".
MA transfer).

The DMA controller 8 is used to record a voice,
The data in the buffer memory 2 is DMA-transferred to the main memory, and the data in the main memory 7 is DMA-transferred to the buffer memory 2 when audio is reproduced. This DMA transfer is repeated a plurality of times in byte units.

Each of the DMA controllers 8 has an internal register for storing a base address BA, a current address CA, a base count BC, and a current count CC (hereinafter referred to as a BA register or the like as necessary). Auto-initialize using

That is, at the start of the DMA transfer, the DMA controller 8 transfers the base address BA and the base count BC stored in the BA and BC registers to the CA and CC counters, respectively. Thus, the base address BA is set to the current address CA, and the base count BC is set to the current count CC. Further, triggered by the end of the transfer, the DMA controller 8 transfers the base address BA and the base count BC to the CA and CC counters, respectively, and sets them as the current address CA and the current count CC, respectively.

In the above-described auto-initialization function, the base address BA and the current address CA, and the base count BC and the current count CC cannot be updated separately. That is, while the current address CA and the current count CC are used for data transfer, the base address BA and the base count BC cannot be updated. Therefore, the same base address BA and the same base count BC are always stored as the current address CA and the current count CC with the transfer end as a trigger.

Base address BA and base count B
C is set in advance by a predetermined processing program.
The base address BA is stored in the main memory 7 when recording audio.
Of the main memory 7 during audio reproduction. Base count BC
Indicates the number of bytes to be transferred by the DMA transfer.

The current address CA is obtained by setting the base address BA in the CA register, and is added (incremented) by +1 every time one byte (one time) of the DMA transfer of the PCM audio data. The current count is obtained by setting the base count BC in the CC register, and is decremented (decremented) by -1 for each DMA transfer of one byte (one time) of PCM voice data.

To supplement the auto-initialize function,
1 / n counters 3 and 6 are provided between the DMA controller 8 and the buffer memories 2 and 5, respectively. The 1 / n counters 3 and 6 in FIG. 2 constitute the interrupt signal generating means 36 in FIG.

The 1 / n counters 3 and 6 count the number of transfer bytes (the number of transfers) of the DMA transfer performed by the DMA controller 8, generate an interrupt signal when the count value reaches a predetermined value, and notify the CPU 10 of the interrupt. .

The 1 / n counters 3 and 6 can be prepared in a form mounted on an additional board of a personal computer.
If the value of n and the value of the base count BC are determined, the 1 / n counters 3 and 6 can be configured as simple hardware. Therefore, it can be easily applied to an existing personal computer by adding simple hardware.

In this embodiment, n = 2, and 1/2 counters are used as 1 / n counters 3 and 6. That is, 1
The / n counters 3 and 6 count the number of bytes transferred by DMA and generate an interrupt signal when the value becomes 1 / 2BC (= 1 / 2CC). Since the sizes of the regions X and Y also correspond to 1 / 2BC, this interrupt signal
Or, it is generated every time the DMA transfer for Y is completed.

It is needless to say that the value of n is not limited to "2", but can be set to an appropriate value of 3 or more, so that DMA transfer and read / write of the buffer memory can be controlled more finely.

FIG. 3 shows a data transfer sequence at the time of audio reproduction when n = 2. The external storage device (hard disk) 9 stores continuous PCM audio data A to H. This data is assumed to be 88 Kbytes, which is equivalent to 2 seconds when the output frequency is 44 KHz.

It is assumed that a total area of 22 Kbytes is secured in the main memory 7 as an area for DMA transfer. The start address of this area is set in the BA register of the DMA controller 8, and the size (22 Kbytes) of this area is set in the BC register. Since n = 2, the (for reproduction) 1 / n counter 6 is a 1/2 counter, counts the transfer of 11 Kbytes, and generates an interrupt signal every 11 Kbytes.

A predetermined processing program is stored in the external storage device 9.
The above data A and B are stored in the area X of the main memory 7, respectively.
After that, the DMA controller 8 is activated. Thereby, the reproduction of the sound is started.

First, in the DMA controller 8, the base address BA and the base count BC are used as the current address CA and the current count CC. Then, the data A and B in the areas X and Y are sequentially DMA-transferred to the buffer memory 5 and output from the DAC 4 as sound.

At the intermediate point of the DMA transfer, that is, at the end of the DMA transfer of the data A in the area X, the 1 / n counter 6 detects that the DMA transfer has been performed for 11 Kbytes, and generates an interrupt signal. Note that this point in time is 250 ms later as shown in the figure.

This interrupt signal means that the transfer of the data in the area X has been completed, and indicates that the next data can be transferred to the area X. By knowing the availability of the area X, the period until the transfer of the data of the next area X can be used as the time for preparing the next data in advance.

The data transfer means 1 is generated by this interrupt signal.
The 1 / n interrupt processing routine (program), which is 1, is started, and the data C on the external storage device 9 is transferred to the area X. This transfer can be completed during the DMA transfer of data B, as shown.

Next, when the DMA transfer of the data B in the area Y is completed, the DMA controller 8 again uses the auto-initialization function to execute the current address CA.
And the current count CC are set. On the other hand, at this point, since the DMA transfer has been performed again for only 11 Kbytes, the 1 / n counter 6 generates an interrupt signal.

Therefore, DMA transfer of data C in area X is performed, while data D is transferred to empty area Y. The transfer of data D can be completed during the DMA transfer of data C.

Thereafter, the sound can be continuously reproduced by repeating the same processing. FIG. 4 shows a data transfer sequence at the time of voice recording when n = 2. Each condition in this sequence is assumed to be the same as the sequence in FIG.

ADC1 to P according to analog audio input
The CM audio data is output and stored in the buffer memory 2. Immediately, the DMA controller 8 is activated, and the recording of voice is started.

In the DMA controller 8, a current address CA and a current count CC are set. Then, the data A and B are sequentially DMA-transferred from the buffer memory 2 to the areas X and Y.

At the intermediate point of this DMA transfer, that is, at the end of the DMA transfer of data A to area X, 1 / n counter 3 detects that 11 Kbytes of DMA transfer have been performed, and generates an interrupt signal. I do.

The 1 / n interrupt processing routine is started by this interrupt signal, and the data A in the area X is transferred to the external storage device 9. This transfer can be completed by the end of the transfer of the data B to the area Y as shown.

Next, when the DMA transfer of the data B to the area Y is completed, the current address CA and the current count CC are set again, and an interrupt signal is generated. Thus, the DMA transfer of the data C to the empty area X is performed, and the data B of the area Y in which the data storage is completed (filled) is transferred to the external storage device 9.
Thereafter, the sound is continuously recorded by the same repetition.

[0061]

As described above, according to the present invention,
In PCM audio data processing using DMA transfer, by adding a 1 / n counter as hardware, the main memory can be apparently divided into n and data can be transferred to and from an external storage device. DMA transfer between the memory and the buffer memory can be performed continuously, and continuous recording and reproduction of audio can be performed. Further, by adding a simple configuration such as a 1 / n counter to an existing personal computer or the like, the DM
A transfer can be performed continuously, and continuous recording and reproduction of audio can be performed.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a diagram showing a transfer sequence (during reproduction).

FIG. 4 is a diagram showing a transfer sequence (during recording).

FIG. 5 is an explanatory view of a conventional technique.

[Description of Signs] 1 ADC 2, 5 Buffer memory 3, 6 1 / n counter 4 DAC 7 Main memory 8 DMA controller 9 External storage device 10 CPU 11 Data transfer means 25 Buffer memory 36 Interrupt signal generation means

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G10L 19/00

Claims (3)

(57) [Claims] A main memory for storing PCM audio data and an external storage device; a buffer memory for temporarily storing the PCM audio data for inputting / outputting audio; A data processing apparatus comprising: a DMA controller (8) for transferring the PCM audio data between a main memory (7) and a buffer memory (25); a transfer data amount set in the DMA controller (8) An interrupt signal generating means (36) for generating an interrupt signal every 1 / n of the time, transferring the PCM audio data between the main memory (7) and the external storage device (9) according to the interrupt signal. And an interrupt signal generating means (36) for transferring the P data between the main memory (7) and the buffer memory (25). M
The interrupt signal is generated every time the transfer amount of the audio data reaches 1 / n of the transfer data amount, and the data transfer means (11) responds to the interrupt signal by using the buffer in the main memory (7). The PCM audio data is transferred to and from the external storage device (9) in an area where the transfer of the PCM audio data to and from the memory (25) is completed.
CM audio data processing method. 2. The transfer of the PCM audio data between the main memory (7) and the buffer memory (25) is performed in byte units, the transfer data amount is set as a transfer byte number, and the interrupt signal 2. The PCM audio data processing system according to claim 1, wherein said generating means comprises a 1 / n counter for generating an interrupt signal for each 1 / n count value of said transfer byte number. . 3. The size of an area of the main memory (7) used for transferring the PCM audio data between the main memory (7) and the buffer memory (25) may be equal to the number of transfer bytes. 3. The PC according to claim 2, wherein:
M audio data processing system.