JP3188679B2 - Output buffer circuit with skew suppression function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an output buffer circuit having a skew suppression function.

[0002]

2. Description of the Related Art In recent years, when data is transmitted and received between two chips, as the data transfer rate increases,
Between the clock signal and the transmitted data or the transmitted 2
It is important to reduce the skew between types of data.

Conventionally, when high-speed data transfer is required, the output timing of a clock signal or data is adjusted to the same timing using a DLL or a PLL, so that skew, which is a phase shift of a signal, is reduced. Suppression is performed.

[0004]

However, the present inventors have found that simply adjusting the output timing of a clock signal or data to the same timing as in the prior art described above, in a higher-speed data transfer, requires the data and the like. It has been found that skew occurs even after adjustment of the output timing, and that data reception is not properly performed due to the skew.

As one of the causes of the skew occurring after the adjustment of the output timing, the present inventors point out that the length of a period during which signals to be transmitted are determined to have the same logical value (hereinafter referred to as a determined period). And focused on this. Hereinafter, this point will be described in detail with reference to FIG.

In FIG. 5, CLK is a clock signal, D
out1 and Dout2 indicate data output from the driver to the bus on the transmission side. Vref is a reference value for determining the logical value of data in the receiving device. The receiving device determines that a potential lower than the reference value Vref is "L" level and a potential exceeding the reference value Vref is "H" level. I do. The data Dout1 changes from the “L” level to the “H” level at the falling timing T1 of the clock signal CLK, and is held at the “L” level before the timing T1, and the determination period is long. Data. On the other hand, the data Dout2 is the clock signal C
At the rising timing T0 of the LK, the level changes from the “H” level to the “L” level, and at the next falling timing T1.
Changes from the “L” level to the “H” level. Therefore, the data Dout2 is data having a short “L” level period before the timing T1 and a short fixed period.
The data Dout1 has an “L” level potential VL at timing T1.
, And reaches the "H" level potential VH. On the other hand, although the data Dout2 drops from the potential VH at the timing T0, it does not reach the “L” level potential VL at the timing T1, and the predetermined potential dV is lower than the potential VL.
The potential rises only from a higher potential value. As a result, the data Dout1 having a long determinate period requires a longer period from the timing T1 to reach the reference value Vref as compared with the data Dout2 having a short determinate period. (Skew) SKt has occurred. The skew SKt becomes more remarkable as the frequency of the clock signal CLK increases and as the load on the bus on which data is loaded increases. From the above description, the data output timing at the driver on the transmitting side is determined by the two types of data Dout1 and Dout.
It can be seen that skew occurs due to the length of the data determination period even when the two are matched.

An object of the present invention is to provide an output buffer circuit capable of effectively suppressing data skew generated depending on a signal determination period.

[0008]

In order to achieve the above object, in the present invention, a fixed period of a signal is detected, and the driving capability of the bus is changed according to the length of the detected fixed period.

That is, an output buffer circuit having a skew suppressing function according to the first aspect of the present invention comprises: a drive unit for driving a bus according to a logical value of an input signal; and inputting the input signal based on a clock signal; A fixed period detecting means for detecting a fixed period in which this input signal is maintained at the same logical value, and outputting a signal indicating the detection result, receiving an output signal of the fixed period detecting means, And drivability control means for controlling the drivability of the drive means.

According to a second aspect of the present invention, in the output buffer circuit having the skew suppressing function according to the first aspect, the drive capability control means may be configured so that the determination period detected by the determination period detection unit is long. Is characterized in that the drive capability of the drive means is controlled to be higher than in the case of a short time.

According to a third aspect of the present invention, in the output buffer circuit having the skew suppressing function according to the first aspect, the definite period detecting means captures the input signal at a timing of capturing the clock signal. Comparing the logical value of the input signal with the logical value of the input signal taken at the signal taking timing one before the signal taking timing,
Thereby, the determination period of the input signal is detected.

According to a fourth aspect of the present invention, in the output buffer circuit having the skew suppression function according to the third aspect, the fixed period detecting means operates at every predetermined edge timing of the clock signal. And a second latch circuit, and a comparison circuit, wherein the first latch circuit latches the logical value of the input signal and outputs the latched logical value, and the second latch circuit , Latching the logical value output by the first latch circuit, and outputting the latched logical value.
The logical values output by the first and second latch circuits are compared with each other, and the comparison result is output to the drive capability control means.

According to a fifth aspect of the present invention, in the output buffer circuit having the skew suppressing function according to the first aspect, a signal output from the fixed period detecting means to the drive capability control means is delayed for a set time. The set time delayed by the delay means is changed in accordance with the first logical value change of the input signal after the drivability of the drive means is detected by the definite period detection means by the definite period. It is characterized by being set so that.

According to a sixth aspect of the present invention, in the output buffer circuit having the skew suppression function according to the first aspect, a plurality of buses driven by the drive means are provided with a plurality of buses for transmitting and receiving signals to and from each other. The semiconductor integrated circuit is connected.

With the above arrangement, according to the first to sixth aspects of the present invention, the bus drive capability of the drive unit is changed by the drive capability control unit according to the length of the input signal determination period. Therefore, for example, when the fixed period of the input signal is long, that is, when a long period is required for the transition of the logical value of the input signal to be performed thereafter, the drive unit is compared with the case where the fixed period of the input signal is short. Of the input signal is changed to be higher, so that the transition of the logical value of the input signal is shorter than the long period. As a result, regardless of the length of the fixed period of the input signal, the transition period of the logical value of the input signal is always almost the same period, and data skew depending on the fixed period of the input signal is effectively suppressed. become.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall schematic configuration of a signal transmission / reception system. In FIG. 1, reference numeral 1 denotes six semiconductor integrated circuits.
(LSI), and these semiconductor integrated circuits 1 are connected to a plurality of (two in the figure) shared buses 6. These semiconductor integrated circuits 1 transmit and receive signals to and from each other. When transmitting and receiving a signal between two predetermined semiconductor integrated circuits, the semiconductor integrated circuit on the transmitting side drives the potential of the bus 6 and the semiconductor integrated circuit on the receiving side detects a change in the potential of the bus 6. To receive the signal. In the semiconductor integrated circuit on the transmitting side, it is necessary to drive the capacity of the bus 6 and the input capacity of the other five semiconductor integrated circuits 1. The capacity of the bus 6 increases as the number of connected semiconductor integrated circuits increases, that is, as the bus length increases.

Each of the semiconductor integrated circuits 1 has an output buffer circuit 10 for signal transmission therein as shown in FIG. The output buffer circuits 10 are provided in a number equal to the number of the buses 6. FIG. 2 shows only the output buffer circuit 10 for one bus 6. In the output buffer circuit 10, DIN is an input signal, 14 is the input signal DIN, and a fixed period detecting circuit (fixed period detecting means) for detecting a fixed period in which the input signal DIN is maintained at the same logical value; Reference numeral 11 denotes a delay circuit (delay means) for delaying the output signal SEL1 of the definite period detection circuit 14 by a set time and outputting a delay signal SEL2, and 12 denotes a latch circuit (described later) included in the definite period detection circuit 14.
The driver (drive means) receives the output signal DL1 of 0 and outputs the signal DL1 to the bus 6. Also,
Reference numeral 15 denotes a drive capability control circuit (drive capability control means) that changes the drive capability of the driver 12 according to the length of the determination period detected by the determination period detection circuit 14.

The internal configuration of the fixed period detection circuit 14 will be described. In the fixed period detection circuit 14, reference numerals 20 and 21 denote first and second latch circuits each including a D latch.
It operates based on LK, and sets the rising edge of this clock signal CLK as the signal fetch timing. The first latch circuit 20 latches a logical value of the input signal DIN and outputs the latched logical value. Therefore,
As shown in FIG. 4, the output DL1 of the first latch circuit 20 is a signal obtained by delaying the input signal DIN until the rising edge of the clock signal CLK. The second latch circuit 21 latches the output DL1 of the first latch circuit 20, and outputs the latched logical value. Accordingly, the output DL2 of the second latch circuit 21 is a signal obtained by delaying the output signal DL1 of the first latch circuit 20 by one cycle of the clock signal CLK, as shown in FIG.

The fixed period detection circuit 14 further includes a comparison circuit 23. The comparison circuit 23 receives the outputs DL1 and DL2 of the first and second latch circuits 20 and 21 and compares these inputs. As can be seen from FIG. When they match, an "H" level selection signal SEL1 is output. When the logical values of both inputs do not match, an "L" level selection signal SEL1 is output. That is, the comparison circuit 23 calculates the logic value DL1 of the input signal DIN at the rising edge (signal fetch timing) of the clock signal CLK and the logic value DL2 of the input signal DIN at the rising edge immediately before the rising edge. To detect a state in which the logical value of the input signal DIN lasts for two cycles of the clock signal CLK. This state is determined to be a state in which the definite period of the input signal DIN is long, and the "H" level selection signal SEL1 is determined. Is output.

During the set time of the delay circuit 11, that is, the period for delaying the selection signal SEL1, the logical value of the output signal DL1 of the first latch circuit 20 is continuous as can be seen from the delay selection signal SEL2 shown in FIG. In the present embodiment, when the same value is obtained in two cycles, the next change in the logical value (timing A shown in FIG. 4) is within the generation period of the "H" level delay selection signal SEL2. Clock signal C
It is set to about half a cycle of LK.

Next, the internal configuration of the driver 12 and the drive capability control circuit 15 will be described with reference to FIG. In FIG. 1, a driver 12 includes a main driver 12a and an auxiliary driver 12b having the same internal configuration.
The main driver 12a receives a signal obtained by inverting the output signal DL1 of the first latch circuit 20, and drives the bus 6 with an output DOUT corresponding to the inverted signal. On the other hand, the auxiliary driver 12b receives the outputs CON1 and CON2 of the drive capability control circuit 15, and drives the bus 6 with an output DOUT corresponding to these signals.

The drive capability control circuit 15 shown in FIG.
It has an ND circuit 15a and a NOR circuit 15b. The N
The delay selection signal SEL2 from the delay circuit 11 and the output signal DL1 of the first latch circuit 20 are input to the AND circuit 15a. Output CON of NAND circuit 15a
1 is output to the PMOS transistor 200 of the auxiliary driver 12b. Further, a signal obtained by inverting the delay selection signal SEL2 from the delay circuit 11 by the inverter 15c and an output signal DL1 of the first latch circuit 20 are input to the NOR circuit 15b. NOR circuit 1
The output CON2 of the auxiliary driver 12b is connected to the NM of the auxiliary driver 12b.
Output to the OS transistor 210. In the drive capability control circuit 15, reference numeral 15d denotes an inverter for inverting the output signal DL1 of the first latch circuit 20,
The output is output to the main driver 12a.

Therefore, in the driver 12, the main driver 12a always operates according to the output signal DL1 of the first latch circuit 20. Also, the auxiliary driver 1
2b indicates that the delay selection signal SEL2 of the delay circuit 11 is "
Only when the logic level of the input signal DIN is the H level, that is, when the logic value of the input signal DIN is the same value in two consecutive cycles (when the determination period is long), the operation is performed in accordance with the output signal DL1 of the first latch circuit 20. , The drive capacity of the bus 6 is changed to be higher.

The configuration of the driver 12 can be variously changed. For example, the two drivers 12a and 12b are always operated, and the delay selection signal SEL2 of the delay circuit 11 is set to "
The operation of the auxiliary driver 12b may be stopped at the time of the L "level (when the fixed period is short) to control the drive capability of the bus 6 to be low. Is optional. For example, the input signal D
In the case where the transition of IN is frequent and many, the case where the determination period is short may be used as a reference. Further, the change width of the drive capability of the driver 12 can correspond to the magnitude of the skew generated due to the length of the fixed period of the signal DIN.
What is necessary is just to set according to the frequency of the clock signal CLK, the load capacity of the bus 6, etc.

According to the above configuration, in the present embodiment, the logical value of input signal DIN is one of clock signal CLK.
If it changes every cycle, that is, if the definite period of the input signal DIN is short, the definite period detection circuit 14 outputs an "L" level selection signal SEL1 and the drive capability control circuit 15
Is the driver 12 according to the output signals CON1 and CON2.
Of the auxiliary driver 12b is stopped. Therefore,
In the driver 12, only the main driver 12a operates according to the output signal DL1 of the first latch circuit 20, and the drive capability becomes a normal value.

On the other hand, when the logical value of the input signal DIN is the same value in two consecutive cycles of the clock signal CLK, that is, when the definite period of the input signal DIN is long, the definite period detection circuit 14 outputs the "H" level. And outputs the selection signal SEL1 of
The drive capacity control circuit 15 outputs the output signals CON1, C
The auxiliary driver 12b of the driver 12 is controlled to the operating state by ON2. As a result, the driving capability of the driver 12 is changed to the capability of the main driver 12a.
The driving capability is changed to a higher driving capability with the capability b. As a result, as shown in FIG. 4, when the logic value of the output signal DL1 of the first latch circuit 20 changes after the same value in two cycles (A and B shown in FIG. 4), the driver 12 The output DOUT waveform has a larger slope of change than the conventional output DOUT ′ waveform shown in FIG.
times tf1 and tr1 until the voltage f reaches t
When the potential f1 rises, tr1) becomes shorter than the same time tf2, tr2 at the conventional output DOUT '. As a result, as shown in FIG. 4, in the present embodiment, the time required to reach the reference value Vref is the same both when the signal DIN changes every cycle and when the same logical value continues for two cycles. Values tf1, tr
It becomes 1 and there is no skew.

In the above-described embodiment, the driving capability of the driver 12 is controlled in two stages. However, it is needless to say that the driving capability may be controlled in three or more stages as necessary. For example, on the receiving side of the signal, the reference value V for determining the level of “H” or “L” of the signal.
When there are a plurality of refs, the drive capability is controlled at a stage corresponding to this. In this case, the fixed period detection circuit 1
4 detects how many cycles of the same logical value of the signal DIN continue as a decision period of the signal DIN, and outputs a selection signal corresponding to the length of the decision period to the driver 12.

In the above embodiment, the rising edge of the clock signal CLK is taken as the timing for taking in the signal DIN. However, the present invention is not limited to this. In addition, the falling edge of the clock signal CLK may be taken as the signal taking-in timing. Of course, only the rising edge and the falling edge of the clock signal CLK may be used.

[0030]

As described above, according to the output buffer circuit of the first to sixth aspects of the present invention, the bus drive capability of the drive means is changed according to the length of the fixed period of the input signal. Regardless of the length of the input signal determination period, the transition period of the logic value of the input signal can always be made substantially the same, and data skew depending on the input signal determination period can be effectively suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an overall configuration of a signal transmission / reception system including an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an output buffer circuit according to the embodiment of the present invention.

FIG. 3 is a diagram showing an internal configuration of a drive capability control circuit and a driver provided in the output buffer circuit.

FIG. 4 is a timing chart illustrating the operation of the output buffer circuit.

FIG. 5 is a diagram illustrating a state in which a transition period of a logical value of an input signal varies according to the length of a fixed period of the input signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 6 Bus 10 Output buffer circuit 11 Delay circuit (Delay means) 12 Driver (Drive means) 12a Main driver 12b Auxiliary driver 14 Definite period detection circuit (Definite period detection means) 15 Drive capability control circuit (Drive capability control unit) 20) first latch circuit 21 second latch circuit 23 comparison circuit DIN input signal

Continuation of the front page (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 3/00 H03K 19/0175 Patent file (PATOLIS)

Claims (6)

(57) [Claims] 1. A drive means for driving a bus in accordance with a logical value of an input signal, the input signal being input based on a clock signal, and detecting a fixed period in which the input signal is maintained at the same logical value. ,
A fixed period detecting unit that outputs a signal indicating the detection result; and a drive capability control unit that receives an output signal of the fixed period detecting unit and controls the drive capability of the drive unit according to the length of the fixed period. An output buffer circuit having a skew suppression function, comprising: 2. The drive capability control unit controls the drive capability of the drive unit to be higher when the determination period detected by the determination period detector is longer than when the determination period is shorter. An output buffer circuit having a skew suppression function according to claim 1. 3. The method according to claim 1, wherein the determining period detecting means captures a logical value of the input signal captured at a signal capturing timing of the clock signal at a signal capturing timing immediately before the signal capturing timing. 2. The output buffer circuit having a skew suppression function according to claim 1, wherein the logic circuit compares the logical value of the input signal with the logical value of the input signal, thereby detecting the fixed period of the input signal. 4. The fixed period detecting means includes first and second latch circuits that operate at predetermined edge timings of a clock signal, and a comparison circuit, wherein the first latch circuit is configured to receive the input signal. The logic value of the signal is latched, and the latched logic value is output. The second latch circuit latches the logic value output by the first latch circuit, and outputs the latched logic value. 4. The skew suppression function according to claim 3, wherein the comparison circuit compares the logical values output by the first and second latch circuits, and outputs a result of the comparison to the drive capability control means. An output buffer circuit having: 5. A delay unit for delaying a signal output from the fixed period detection unit to the drive capability control unit for a set time, wherein the delay time of the delay unit is such that the drive capability of the drive unit is: 2. The output buffer circuit having a skew suppression function according to claim 1, wherein the output buffer circuit is set so as to be changed in accordance with a first logical value change of the input signal after the detection of the final period by the final period detector. . 6. An output having a skew suppression function according to claim 1, wherein a plurality of semiconductor integrated circuits for transmitting and receiving signals to and from each other are connected to a bus driven by said drive means. Buffer circuit.