JP3184344B2 - Simulated fault setting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo fault setting device for setting a pseudo fault in a device, and more particularly to a pseudo fault setting device for setting a pseudo fault in hardware operating under an OS. .

[0002]

2. Description of the Related Art Generally, a non-stop communication control processing device loads a communication control program into the device and realizes an input / output operation mainly for communication control by accessing a processor module (PM). At this time, in order to confirm a switching operation when a failure occurs in the device, it is necessary to generate a pseudo failure and confirm the switching.

Conventionally, when a pseudo-failure is set for an apparatus while a communication control program is operating under the control of an OS, it is performed manually by a hardware clip from the outside or compulsorily executed by executing a diagnostic command. Or set a false fault in the device.

[0004]

In the former method of setting a pseudo failure by a manual hardware clip,
Not only is it difficult to accurately set a pseudo-failure in hardware, but also there is a problem in recent high-density circuits that there is a risk of circuit destruction.

In the latter method of forcing a pseudo-failure to be set in a device by executing a diagnostic instruction, the pseudo-failure is set ignoring the state of the communication control program. As a result, there is a problem that confirmation corresponding to the original failure event may not be performed.

[0006] The present invention solves these problems,
Write a suspicion processing program and suspicious parameters in the empty area of the communication control unit, and write a branch instruction to the suspicion processing program in the interrupt area to set a pseudo-failure. It is an object of the present invention to activate a suspicion processing program, set a simulated failure corresponding to a suspicious parameter, and enable the setting of a simulated failure accurately and accurately in a synchronized manner.

[0007]

Means for solving the problem will be described with reference to FIG. In FIG. 1, an empty area 1
0 is the suspicion processing program 11 and the suspicion parameter 12
Is an empty area in which, for example, a BSP (bootstrap program) is written.

The suspicion processing program 11 sets a simulated failure in the apparatus according to the suspicion parameter 12. The suspicion parameter 12 indicates a simulated failure to be set in the apparatus.

The interrupt area 8 stores a suspicion processing program 11
This is the area to write the branch instruction to.

[0010]

According to the present invention, as shown in FIG. 1, a suspicious processing program 11 and a suspicious parameter 12 are written in an empty area 10 and a branch instruction to the suspicious processing program 11 is written in an interrupt area 8 so that an interrupt is generated. When a problem occurs, the suspected processing program 11 is started by the branch instruction written in the interrupt area 8, and the started suspected processing program 11 writes the branch instruction back to the original instruction, and in accordance with the suspected parameter 12, causes a pseudo failure. Is set to the device. At this time, the empty area 10 is set to an empty area 10 of a BSP (bootstrap program).

[0011] Further, with the pseudo failure set in the device,
When a processing request is issued to the device due to an interruption or the like, the set log information in a state where the pseudo failure has occurred is collected and the device is tested.

Therefore, an empty area (for example, an empty area of a bootstrap program) 10 of a device (for example, a communication control unit)
Writing a suspected processing program 11 and a suspected parameter 12 into the interrupt area 8 and writing a branch instruction in the interrupt area 8 to start the suspected processing program 11 at the time of a normal interruption to the device and to set a pseudo failure according to the suspected parameter 12 Accordingly, it is possible to set a pseudo fault accurately and accurately. In addition, it is possible to collect log information of a pseudo-failure caused by the set pseudo-failure and perform a test of the apparatus.

[0013]

Next, the structure and operation of an embodiment of the present invention will be sequentially described in detail with reference to FIGS.

FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 1A shows a configuration diagram. In FIG. 1A, a processor module (PM) 1 performs various controls according to a program.

The main memory 2 stores programs and data. Here, the main memory 2
The program which operates as the pseudo failure occurrence control unit 3 is stored in the storage unit.

The simulated fault occurrence control unit 3 writes the suspicious processing program 11 and the suspicious parameter 12 in an empty area of the BSP 9 of the communication control unit 4 which is a device to which a simulated fault is set, and executes the communication control unit 4. For example, a branch instruction to the suspicion processing program 11 is written in the interrupt area 8 of the program.

The communication control unit 4 is a device to which a pseudo fault of the present invention is set, and includes an I / O bus control adapter 5,
It comprises a logic unit 6, a communication scanner 13, and the like.

I / O bus control adapter (IOBC-A)
Reference numeral 5 denotes an I / O bus for controlling data transfer with the processor module 1. The logic unit (CCU) 6 executes a program.

The communication control program 7 is a program for controlling communication. The interrupt area 8 is an area that branches when an interrupt occurs, and more specifically, is an area at the head of an area (for example, address 100) of the level 3 interrupt processing to the communication control program 7 in the communication control unit 4. . In the present invention, a branch instruction (2 bytes) to the suspicion processing program 11 is written into the interrupt area 8, and when a level 3 interrupt to the communication control program 7 of the communication control unit 4 occurs, it is automatically performed. It is set so as to branch to the suspicion processing program 11.

The BSP 9 is a bootstrap program. A suspicion processing program 11 and a suspicion parameter 12 according to the present invention are written in the empty area 10 of the BSP 9.

The empty area 10 is an empty area of the BSP 9 here. The suspicion processing program 11 includes the suspicion parameter 1
2 to set a pseudo obstacle. For example, a pseudo fault is set, reset, and set only once according to the fault code of FIG. 1B. As the pseudo failure, IOBC-A, CCU, CS and the like are set, and for example, IO bus parity error, IOBC-A bus error and the like are set.

The suspicious parameter 12 is a parameter for causing a simulated failure, and sets the suspicious parameter 12 as shown in FIG. Communication scanner (CS)
Reference numeral 13 controls a line.

FIG. 1B shows an example of a suspected parameter.
This suspect parameter is composed of 2 bytes and is set as shown. Bit0 of Byte0, 1: Set OP code, 00: NOP (No operation) 01: SET (Set a pseudo fault) 10: RESET (Reset a pseudo fault) 11: SET / RESET (Once a pseudo fault occurs (Reset by only) Byte0 Bit2 to Bit7: Set a suspect code.

[0024] Byte 1 to Bit 7 to 7: Suspicion occurrence frequency control (sets the occurrence frequency of suspicions). As described above, the OP code, the suspicious code, and the number of times of occurrence of the suspicion are set in the suspicious parameter 12, and the suspicious processing program 11 started by the interrupt sets the quasi-failure in accordance with the suspicious parameter 12.

Next, the operation of the configuration of FIG. 1 will be described in detail according to the order shown in the flowchart of FIG. In FIG. 2, S1 loads the suspicion occurrence control unit 3 into the PM ((a) of FIG. 1). In this case, the suspicion occurrence control unit 3, which is a program, is written (loaded) from the floppy disk of FIG. 3 described later into the main memory 2 of the processor module 1.

In step S2, the suspicion occurrence control section 3 is started.
This activates the suspicion occurrence control unit 3 in a conversation with the operator. In S3, the suspicion occurrence control unit 3 writes the suspicion processing program 11 in the empty area 10 of the BSP 9 ((a) of FIG. 1).

In S4, the suspicion occurrence control unit 3 writes the suspicious parameter 11 in the empty area 10 of the BSP 9 (FIG. 1 (a)).
of). S5 holds the first instruction 2 bytes of the L3 interrupt area 8. This is the level 3 interrupt area 8 in FIG.
It holds the first two bytes of the instruction (eg, address 100) (two bytes of the branch instruction).

In step S6, a 2-byte branch instruction is written directly to the OS (communication control program) in the L3 interrupt area ((a) in FIG. 1). This writes 2 bytes of a branch instruction to the suspicion processing program 11 in the level 3 interrupt area 8 for the communication control program 7 in FIG. This allows
When a normal interrupt occurs, the suspicion processing program 11 is started by the written branch instruction, and the control is passed.

In step S7, when a normal interrupt process occurs between the PM and the CCM (communication control unit 4), L3 is executed by the CCM.
An interrupt occurs. In step S8, when the L3 interrupt occurs in step S7, the branch instruction stored in the interrupt area 8 is executed, and the suspect processing program 11 at the branch destination is activated. The L3 interrupt is also generated by an interval timer interrupt. Here, control is passed to the suspicious processing program 11 by a normal L3 interrupt, so that a simulated fault can be set as a normal interrupt processing as described later.

In step S9, the held 2-byte instruction is restored. This means that the original two-byte instruction is returned to the interrupt area 8, and the instruction storing the branch instruction to the suspicious processing program 11 is returned to the original instruction (the original instruction is restored at the end of the pseudo failure setting). ).

In step S10, the suspicious parameter 12 is analyzed to
Perform the operation according to the P code. For example, setting of a suspicion (“S” in which the OP code in FIG. 1B is 01)
In the case of “ET”, the suspicion is cleared (the OP code of FIG. 1B is “R” of 10).
ESET ”).

As described above, after the pseudo failure occurrence control unit 3 is loaded from the floppy disk or the like into the main memory 2 of the PM 1 and started (FIG. 1A), the pseudo failure occurrence control unit 3 11 and the suspect parameter 12 are stored in the empty area 10 of the BSP 9 in the communication control unit 4 and a branch instruction to the suspect processing program 11 is written in the interrupt area 8 (see (a) of FIG. 1).
). Then, when an interrupt occurs, the suspicious processing program 11 started by the branch instruction set in the interrupt area 8 sets a simulated fault according to the suspicious parameter 12.

FIG. 3 shows a system configuration diagram of the present invention.
This shows the actual configuration of the configuration shown in FIG. 1A. In FIG. 3, PM1 is a processor module that retrieves and executes a program stored in the main memory 2.

The main memory 2 includes a pseudo failure occurrence control unit 3
And a program that operates as a program.
The CCM (# 1) 4 and the CCM (# 2) 4
Which is a target device for setting a pseudo failure according to the present invention that performs communication control, and includes IOBC-A5, CCU6,
It is composed of MS14, CS13 and the like.

The IOBC-A5 is an IO bus control adapter 5 for controlling connection with the PM1. C
The CU 6 is a logic unit 6 for executing a program in the MS 14.

The MS 14 is a main memory for storing programs such as a communication control program and a BSP. The BSP is a bootstrap program which stores a communication control program and the like at power-on and the like.
14 is a program to be loaded.

The empty area 10 is an empty area of the area prepared for storing the BSP. The suspicion processing program 11 writes into the empty area 10 of the BSP, and executes the CCM (#
1) A pseudo fault is set in the CCM (# 2) 4 according to the suspect parameter 12.

The suspect parameter 12 is the empty area 10 of the BSP.
And instructs the suspicion processing program 11 to set a simulated failure in accordance with this (see FIG. 1 (b)).

CS13 is a communication scanner 13,
It controls the line. CC (# 1) 15, CC
(# 2) 15 is a line connection unit for connecting to a line.

The SFM 16 is an operator interface control unit that controls access to the floppy disk 17 and talks with the operator using a screen on the console display 18. Here, in response to an instruction from the operator, a pseudo failure occurrence control program is stored in the main memory 2 from a floppy disk.
To the pseudo failure occurrence control program (suspension failure occurrence control unit 3) to write the suspect processing program 11 and the suspect parameter 12 to the empty area 10 of the BSP, For example, a branch instruction to the processing program 11 is written in the interrupt area 8.

Based on the above configuration, the operator sets a pseudo failure to: IOBC-A, CCU, MS, CS, etc. by the following procedure.

(1) The operator instructs from the console display 18, takes out the pseudo fault occurrence control program from the floppy disk, writes it in the main memory 2, and starts up.

(2) The operator starts the pseudo fault occurrence control program (pseudo fault occurrence control unit 3) started in (1).
Then, the suspect processing program 11 and the suspect parameter 12 are written in the empty area 10 of the BSP of the MS 14 of the CCM 4.

(3) The operator talks with the pseudo fault occurrence control unit 3 and writes a branch instruction to the fault processing program 11 in the interrupt area 8 of the CCM 4. Thus, the operation of setting the pseudo failure by the operator is completed.

(4) When a normal interrupt occurs in the CCM 4, control is transferred to the suspect processing program 11 by the branch instruction written in the interrupt area 8.
A pseudo fault, for example, the IO bus parity error or the IOBC-A bus error described above, is set in a specified portion of, and the original instruction is written back to the interrupt area 8.

(5) Corresponding to the setting of the pseudo failure in (4), an error occurs, for example, the CCM 4 is disconnected, switched to the spare CCM 4, and log information is collected.

Accordingly, in response to the operator instructing the setting of the pseudo failure by the pseudo parameter, the operator predicts the CC to be set.
It is possible to read and know that the switching of M4 has occurred and that the information to that effect has been collected in the log information, and perform a test such as CCM4.

[0048]

As described above, according to the present invention,
When a suspect processing program 11 and a suspect parameter 12 are written in an empty area (eg, an empty area of a bootstrap program) 10 of a device (eg, a communication control unit), a branch instruction is written in an interrupt region 8, and a normal interrupt to the device is performed. Since the configuration in which the suspicion processing program 11 is started and the simulated failure is set in accordance with the suspicion parameter 12 is adopted, the simulated failure can be set accurately and accurately. As a result, (1) pseudo failures can be safely and accurately set, especially in response to normal interrupts, as compared to the case where a pseudo failure is set by executing a diagnosis instruction that does not consider the state of a conventional hardware clip or communication control program. Can be set and generated.

(2) Since a special tool is not required to set a pseudo fault, a test operation is simplified and a test with high uniformity can be realized. (3) From the point of view of the operator, that is, the tester, the pseudo fault can be set by the program control without considering the state of the communication control program and the like, and the setting of the pseudo fault can be completed only by checking the message from the program. You can know.

(4) A branch instruction to the suspicious processing program 11 is set in the interrupt area 8, and this branch instruction activates the suspicious program 11 to set a quasi-failure at a normal interruption, and then sets an interrupt. Since the original instruction is written back to the area 8, a pseudo failure can be generated without affecting the operating OS and the communication control.

(5) The suspicious processing program 11 and the suspicious parameter 12 are written in an empty area 10 of a BSP (bootstrap program) different from the area where the communication control program 7 is stored or used. Therefore, a pseudo failure can be set without being affected or affected by the communication control program 7.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention.

FIG. 2 is a flowchart illustrating the operation of the present invention.

FIG. 3 is a system configuration diagram of the present invention.

[Explanation of symbols]

 1: Processor module (PM) 2: Main memory 3: Pseudo fault occurrence control unit 4: Communication control unit (CCM) 5: IO bus control adapter (IOBC-A) 6: Logic unit (CCU) 7: Communication control program 8 : Interrupt area 9: BSP (bootstrap program) 10: Empty area 11: Suspicious processing program 12: Suspicious parameter 13: Communication scanner (CS) 14: MS (main memory) 15: CC (line connection unit) 16: SFM (operator interface control unit) 17: Floppy disk 18: Console display

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/277 G06F 9/46

Claims (2)

(57) [Claims] A simulated fault setting device for setting a simulated fault in an apparatus.
In the device, write the fault handling program and the fault parameters ,
An empty area of the bootstrap program and an interrupt area for writing a branch instruction to the fault processing program are provided in the apparatus for setting the fault, and the fault processing program and the fault parameter are stored in the empty area of the bootstrap program. At the same time, the branch instruction to the fault processing program is written in the interrupt area. When an interrupt occurs, the fault processing program is started by the branch instruction written in the interrupt area and written back to the original instruction. A simulated fault setting device, wherein the activated simulated fault processing program sets a simulated fault in the device according to a simulated fault parameter. 2. When a processing request due to an interrupt or the like occurs in the device with the pseudo failure set in the device,
2. The pseudo failure setting device according to claim 1, wherein the log information of the set pseudo failure is collected and a test of the device is performed.