JP2907808B1 - Flash memory emulation device and debug system using the same - Google Patents

Abstract

A specific command sequence is required for the operation of a flash memory, so that other types of ROM emulators cannot be used. SOLUTION: A flash memory command analysis unit 18 detects a flash memory command sequence input from a target substrate 4, and a controller 12 executes processing corresponding to the detected command sequence based on a program stored in a control program memory 14. Shows the emulation memory 16 as a RAM from the target substrate 4 as if it were a flash memory itself. The flash memory command analysis unit 18 is formed on a rewritable FPLA, and can easily absorb a difference in a command sequence for each manufacturer. Debugger command detector 10
2 detects a request from the target CPU 30 and reads the emulation memory 16 from the target substrate 4 side.
It can be handled as M.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a flash memory emulation device for emulating the operation of a flash memory and a debugging system using the same.

[0002]

2. Description of the Related Art A flash memory is an RO capable of electrically erasing stored contents and writing data.
M (read only memory). These features are:
Reduction of turnaround time in product development,
This is particularly advantageous in the case of producing a relatively small amount of various products with changed data, or in a product in which stored contents can be changed later. On the other hand, in a flash memory, a predetermined command sequence is required for batch erasing and writing of stored contents in order to protect the stored contents.

A flash memory is used in a system having, for example, a CPU (Central Processing Unit), and stores a program used in the system. During the development phase, the program is not finalized, and inconveniences are often found and corrected.

[0004] In a debugging operation for finding this inconvenience, a program is stopped at a desired position and the validity of the state of the system at that time is verified. Therefore, in the debugging work, a technique of writing a break instruction into the program as needed to control the execution of the program is used. Flash memory is not well suited for such tasks. This is because the flash memory can be erased only in a predetermined data unit such as the whole chip or a block unit. In other words, every time a program step is rewritten to a break instruction in debugging or returned to the original instruction again, a large amount of data that does not need to be rewritten is erased, and these must be written, which is inefficient. .

Conventionally, a system at the development stage has been designed so that a random access memo (RAM) can be stored so that a copy of a program stored in a flash memory can be stored.
ry). In debugging, a target program is read from the flash memory and stored in the RAM. And the CPU of the system
An operation of reading and executing a program stored in the AM and replacing a certain step with a break instruction as necessary has been performed.

Incidentally, regarding the fact that the program stored in the above-mentioned ROM cannot be directly changed from the debugger program, a mask ROM or another EPROM (erasable programmable ROM) such as an ultraviolet erasing type is used.
The same applies to M). For example, in a mask ROM, it is necessary to separately manufacture and remanufacture a mask having different storage contents, and the cost and the turnaround time become extremely large. In addition, EPROMs need to be removed from the board and attached to a device such as a ROM writer in order to rewrite the stored contents, which is troublesome and increases the cost because an adapter that allows the EPROM to be removed from the board is used. Occurs.

However, there is a device for emulating the operation of these other ROMs.
These problems are also added to the system RAM for debugging.
There is no need to separately mount the.

A conventional emulation device for such another ROM is called, for example, a ROM in-circuit emulator. The ROM in-circuit emulator is connected by a probe to a system (target system) in which the target ROM is used. The probe has, for example, an adapter at the tip and a ROM on the target system board.
Connected to the mounting position. A RAM is mounted on the main body of the ROM in-circuit emulator. In this RAM, contents equivalent to the ROM to be emulated are written from a computer connected to the ROM in-circuit emulator.

[0009] The ROM in-circuit emulator is connected to the target system and performs emulation as follows. In other words, when the target system performs a read operation by specifying an address for a ROM that should be present on its own board, a signal related to the read is output to the RO.
The data is transmitted to the RAM of the M-in-circuit emulator main body, and data equivalent to the ROM is read from the RAM and provided to the target system.

That is, with respect to another ROM, the RAM on such an emulation device is rewritten from a computer connected to the ROM in-circuit emulator, so that the ROM can be re-created or the data can be updated by removing the ROM from the board. It was possible to avoid trouble.

[0011]

In the above-described method of providing a RAM for debugging in the conventional target system, it is generally useless to mount an expensive RAM for unnecessary debugging in a product. In addition, there is a problem that it is disadvantageous in reducing the size of the product.
On the other hand, also in a product, it may be necessary to perform a debugging operation in a failure analysis or the like. In this case, if no RAM is provided, there is a problem that it is difficult to perform a debugging operation.

The flash memory can perform erasing and writing operations by a predetermined procedure in addition to reading. Therefore, a device that emulates a flash memory needs to be able to emulate those erasing and writing operations. However, other conventional R
The emulation device used in the OM only supports the operation of reading from the target system, and cannot be used to emulate the operation unique to the flash memory.

The present invention has been made to solve the above problems, and provides an emulation device that can be used for emulation of a flash memory, and a RAM for holding a copy of a program for debugging in a target system. It is an object of the present invention to make it possible to configure a debugging system that can easily debug a product by using the emulation device.

[0014]

A flash memory emulation device according to a first aspect of the present invention is connected to a target circuit and constitutes an equivalent circuit of a flash memory used in the target circuit. and a RAM for storing a copy of the stored contents, its
Address and data for the flash memory, respectively.
And the flash memory command analyzing unit for detecting a command sequence for selecting the operation of the flash memory is issued from said target circuit comprises a plurality of commands, represented by a combination of data, the RAM, flash memory operations selected sensed A memory operation emulation unit that controls the operation according to a command sequence .

The flash memory requires input of a predetermined command sequence when performing a specific operation.
According to the present invention, the command sequence issued to cause the flash memory to perform the specific operation is detected by the flash memory command analysis unit. The memory operation emulation unit is notified of the detection result, and causes the RAM to perform an operation according to the detected command sequence . Thus, the device can perform a function equivalent to a flash memory.

A flash memory emulation device according to a second aspect of the present invention includes a flash memory emulation device for executing a user program stored in the flash memory.
A RAM that is connected to a target circuit having a PU, constitutes an equivalent circuit of the flash memory, and is used for debugging the user program, and stores a copy of the storage content of the flash memory; a memory operation emulation unit for controlling the flash memory command analyzer, the RAM, in operation according to the detected flash memory operation selected command sequence to detect the command sequence to select the published operating the flash memory from, A debugger command detection unit that detects a free access request command issued from the target circuit and enables free writing from the target circuit to the RAM without being restricted by the flash memory operation selection command. Features.

The flash memory emulation device according to the present invention performs the same operation as the actual flash memory during the emulation operation of the flash memory.
That is, when data is rewritten from the target circuit, it is necessary to erase data in the entire chip or in block units corresponding to the portion to be rewritten. However, in order to efficiently debug a program, a rewrite operation of only some steps is required. According to the present invention, when the debugger command detection unit detects the free access request command issued by the CPU of the target circuit, for example, the debugger command detection unit directly issues the R command from the CPU of the target circuit regardless of the detection result of the flash memory command analysis unit.
It is configured to be able to access the AM. That is, after the detection of the free access request command, the emulation device switches so as to perform the same operation as a simple RAM. The debug system can easily change the program to be debugged using this mode.

A flash memory emulation device according to a third aspect of the present invention is characterized in that the flash memory emulation device has means for stopping a CPU of the target circuit while the memory operation emulation unit accesses the RAM.

The RAM of the emulation device cannot be accessed by the CPU of the target circuit while being accessed by the memory operation emulation unit. According to the present invention, runaway due to the CPU of the target circuit attempting to access the RAM during the inaccessible period is avoided.

In the debugger system according to the present invention, the flash memory emulation device includes a target CP for stopping a CPU of the target circuit.
U-stop means, and a debug instructing unit for giving a debug instruction to a CPU of the target circuit when debugging a user program stored in a flash memory, wherein the debug instructing unit comprises: While the CPU is stopped, the debug instruction is stored in the RAM, and after the stop by the target CPU stop unit is released, the R
By reading the debug instruction stored in the AM, communication from the debug instruction unit to the CPU is performed.

According to the present invention, communication of an instruction at the time of debugging from the debug instruction unit of the flash memory emulation device to the CPU of the target circuit is performed via the RAM. When storing the debugging instruction in the RAM,
The CPU of the target circuit is stopped, and runaway due to the CPU attempting to access the RAM during this period is avoided. The debug instruction stored in the RAM can be read by the CPU via a communication line provided for the CPU to use the flash memory emulation device as a flash memory. There is no need to provide a separate communication line.

In a flash memory emulation device according to a fifth aspect of the present invention, the flash memory command analysis unit is a logic circuit configured as hardware.

According to the present invention, the flash memory command analysis unit can analyze a flash memory command at a high speed in the same manner as performed in an actual flash memory. When used, emulation can be performed similarly.

In a flash memory emulation device according to a sixth aspect of the present invention, the flash memory command analysis unit is configured to be reconfigurable using a programmable semiconductor chip.

Flash memory commands for certain operations may differ, for example, depending on the manufacturer supplying the flash memory. According to the present invention, the flash memory command analysis unit is, for example, an FPLA (field programmable
ogic array) so that it can be reconfigured from outside. Therefore, by reconfiguring the flash memory command analysis unit, emulation of a flash memory having different flash memory commands can be performed.

According to a fourth aspect of the present invention, in the debugging system for performing the debugging using the flash memory emulation device according to the fourth aspect of the present invention, the debugger program executed by the CPU of the target circuit is configured to execute the user program. When the free access request command is issued in response to the interrupt processing instruction written therein, the mode shifts to a debug mode, and upon termination of the debug mode, a free access abandonment command for relinquishing the right of free writing to the RAM. The debugger command detection unit detects the free access abandonment command, prohibits free writing from the target circuit to the RAM, and leaves the writing to the control of the memory operation emulation unit. And

According to the present invention, the debugger program comprises:
When the interrupt processing instruction written in the user program is executed by the CPU of the target circuit, a free access request command is issued. The debugger command detection unit detects the free access request command and switches from the emulation mode of the flash memory to the free access mode in which the RAM can be freely accessed.
On the other hand, the debugger program shifts to debug mode,
Using the free access mode, for example, a process of writing a new interrupt processing instruction in the user program is performed. The debugger program issues a free access abandonment command when necessary debug processing ends. The debugger command detector detects the free access abandonment command and returns from the free access mode to the normal flash memory emulation mode.

[0028]

[First Embodiment] Next, a flash memory emulator according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a conceptual block diagram of the present apparatus connected to a target substrate. Emulator body 2
Are connected to a target substrate 4 which is a substrate using an actual flash memory. Emulator body 2
Is also connected to the host computer 6. The emulator main body 2 includes a host interface 10, a controller 12 including a CPU, a control program memory 14,
It includes an emulation memory 16 composed of an AM, a flash memory command analysis unit 18, an electrical characteristic emulation unit 20, and a buffer 22.

The emulation memory 16 is for storing basically the same contents as the flash memory mounted on the target substrate 4, and the control program memory 14 is for storing the program executed by the controller 12. belongs to. The flash memory command analysis unit 18 is one of the characteristic configurations of the present device. The flash memory command analysis unit 18
This is a circuit for detecting a flash memory command issued from a flash memory, and is configured in hardware using a logical operation element or the like in order to realize processing at a speed close to actual operation inside the flash memory. The operation will be described later. The electric characteristic emulation unit 20 is a circuit for realizing the same impedance as each terminal of the flash memory, for example.

A target bus 24 extends from the emulator body 2. The target bus 24 is formed of, for example, a flexible cable so as to be easily connected to the target substrate 4. The target board 4 side of the target bus 24 is connected to a flash memory emulator adapter 26.
Are arranged on the target substrate 4. The flash memory emulator adapter 26 and the mounting position of the flash memory on the target substrate 4 are connected via a probe 28. Thus, the emulator main body 2 and the target substrate 4 are connected. Incidentally, when the emulator main body 2 is connected, the actual flash memory is not arranged at the flash memory mounting position on the target substrate 4.

The target substrate 4 is a substrate of a product including a flash memory and a CPU (target CPU) 30, such as an automobile engine control circuit and a video camera control circuit. In the actual product, target C
The PU 30 reads out and executes a program from a flash memory disposed on the board, and performs other operations such as block erase and writing on the flash memory.

The host computer 6 is connected to the controller 12 via the host interface 10 and downloads data.

FIG. 2 is a schematic circuit configuration diagram of the emulator main body 2. In this circuit diagram, in addition to the components shown in FIG. 1, an interrupt control circuit 40, a BUSY status control circuit 42, an AND circuit 44, and a switch 46 are shown.

In the flash memory, for example, the stored contents can be collectively erased by an electric signal or new data can be written. To perform these operations,
It is necessary to give a command sequence consisting of a predetermined command or a series of commands to the flash memory. FIG.
Is an explanatory diagram showing an example of the command sequence.
FIG. 3A shows an example of a chip erase command sequence for simultaneously erasing all the stored contents of the flash memory.
When performing the chip erase, the target CPU 30 sequentially issues these commands S50 to S60 to the flash memory. When the flash memory detects this sequence, it performs a chip erase. Each of the commands S50 to S60 is composed of a combination of an address and data. For example, the command S50 indicates that the address “5555”
H "means that data" AAH "is applied to the data input terminal group.At this time, the write enable terminal WR of the flash memory is controlled to be able to write data. This is an example of a block erase command sequence for erasing the stored contents in block units, which is composed of commands S62 to S72, of which the address of the command S72 specifies the address of the block to be erased. Other types of R, such as a mask ROM
In the OM, such a command is not necessary because the stored contents cannot be electrically erased.
This device has a function of emulating an operation based on a command sequence unique to the flash memory.

The characteristic functions of the present apparatus as a flash memory emulator will be described below with reference to FIG. 2 by taking the above-described block erase processing as an example. The emulator main body 2 and the target CPU 30 are connected by an address bus / data bus 80 and a WR signal line 82. The flash memory command analysis unit 18 includes the address bus / data bus 8
1 to detect a command sequence unique to the flash memory. For example, when a block erase command sequence is input from the target substrate 4, the flash memory command analyzer 18 detects this and sends out a detection signal indicating a logical value “true” to the signal line 84.

The BUSY status control circuit 42 provides a BUSY status indicating that the emulation memory 16 is performing the block erase process based on the fact that the signal value of the signal line 84 has become "true". Output to With this, the target CPU
The notification of the busy state of the flash memory to 30 can be simulated.

Further, the interrupt control circuit 40 outputs an interrupt request signal to the controller 12 based on the fact that the signal value of the signal line 84 has become "true". Controller 1
2 receives this interrupt request signal and switches the selection buffer to B
(Buffer 22-2) is switched to A (Buffer 22-1), and the emulation memory 16 can be accessed from itself via the address bus / data bus 86. At the same time, the controller 12 switches the switch 46 to the contact A side so that the controller 12 can supply the WR signal to the emulation memory 16. As a result, the controller 12 can write to the emulation memory 16. The flash memory command analysis unit 18 determines the block number to be erased included in the block erase command sequence from the target CPU 30 (this is, for example, as shown in FIG.
It is specified as the address value of the command S72 of (b). ) Is also transmitted to the controller 12 via the signal line 84. The controller 12 obtains, from the flash memory command analysis unit 18, a notification that the target CPU 30 is requesting the block erase process, and obtains a block number to be erased, and writes all null data to cells of the corresponding block of the emulation memory 16, The previous data of the block is erased.

When the erasure of the data of the corresponding block is completed, the controller 12 switches the selection buffer and the switch 46 from the controller 12 to the target CPU 3.
Switch to 0 side. That is, specifically, the selection buffer is switched from A to B, and the contact point of the switch 46 is switched from A to B. Thereafter, the controller 12 notifies the flash memory command analysis unit 18 of the end of the block erase processing.
In response to this, the flash memory command analysis unit 18 returns the block erase detection signal, the interrupt request signal, and the like of the signal line 84 to the inactive state. The BUSY status control circuit 42 stops the BUSY status output when the block erase detection signal becomes inactive.

Incidentally, the target CPU 30 monitors the address bus / data bus 80 and determines whether or not the erasing process has been completed based on the BUSY status output.

As described above, the present device emulates the block erase process which is one of the characteristic operations of the flash memory. That is, in this process, the emulator main body 2 appears to the target CPU 30 as the flash memory itself. In this example, the controller 12 and the BUSY status control circuit 42 mainly function as a memory operation emulation unit that performs control for making the emulation memory 16 look like the flash memory itself.

As another simple example, the target CP
A case where writing is performed from the U30 to the flash memory will be described. The flash memory also receives data writing by receiving a predetermined command sequence. In the present apparatus, when the write command sequence is input from the target CPU 30, the flash memory command analysis unit 18 detects the
A logical value for permitting writing is given to the D circuit 44. AN
The D circuit 44 is connected to the WR signal line 8 from the target CPU 30.
The logical product of the write enable signal WR input via the interface 2 and the signal from the flash memory command analysis unit 18 is obtained, and only when the result is “true”, the WR terminal of the emulation memory 16 is in a write enabled state. And That is, the AND circuit 44 is connected to the target CPU
It is determined that two conditions, that is, a write command sequence has been issued from 30 and that the write enable signal to the flash memory is in the active state are satisfied, and the writing of data to the emulation memory 16 is performed. Plays the role of permitting. This AND circuit 4
4 permits write data from the target CPU 30 to the address bus / data bus 80, 81.
And emulation memory 1 via selection buffer B
6 is written.

Incidentally, in this example, the AND circuit 44 mainly functions as a memory operation emulation unit.

In the present apparatus, the flash memory command analysis unit 18 detects a command sequence unique to another flash memory, and operates the flash memory in accordance with the detected command sequence. To emulate

Now, the command sequence can differ between manufacturers providing flash memories. That is, the command sequence may be different even for the same operation of the flash memory. For flash memories having such different command sequences,
The hardware circuit configuration of the flash memory command analysis unit 18 is also different.

In the present apparatus, the flash memory command analysis unit 18 is configured using a reconfigurable FPLA so that it can easily cope with different command sequence systems. The FPLA is a device that can realize a desired logic circuit configuration by changing only connections at intersections between input / output lines and product term lines in a gate array completed up to wiring.

Incidentally, there are several types of methods for forming connections at intersections between input / output lines and product term lines. One of them is
A fuse is provided in advance at the intersection, and a current pulse is applied to an input / output line and a product term line at an unnecessary intersection to blow out the fuse to open the desired AND, O
That is, an R array is formed. In addition, as a method of defining the intersection and the connection, there are a method of applying a laser pulse to provide a short-circuited through hole and a method of cutting a fuse, and a method of repeatedly defining a connection using a floating gate.

The present apparatus uses the FPLA which can be changed by repeatedly opening and connecting the intersections. The reconfiguration of the internal circuit of the FPLA is performed by downloading logical data from the host computer 6 side. F in which the flash memory command analysis unit 18 is configured
The logic data is input to the terminal of the PLA, and a new circuit configuration is mapped to the FPLA accordingly.
As described above, the present apparatus uses the FPL for a part that may differ depending on the flash memory to be emulated, such as the flash memory command analysis unit 18, among the constituent parts.
By configuring on A, it is possible to absorb the differences between various flash memories. That is, it is possible to easily change the configuration in accordance with the difference, and to emulate them.

[Second Embodiment] Next, an embodiment of a debugging system using the flash memory emulator of the present invention will be described with reference to the drawings.

FIG. 4 is a conceptual block diagram of the present apparatus connected to a target substrate. 4, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. A major feature of the emulator body 100 is that it has a debugger command detection unit 102. In addition, the controller 12 is connected to the target CPU 30 via a cable, and the controller 12 is configured to be able to perform a HOLD request for temporarily stopping the target CPU 30 and release the suspension (HOLD release). It is one of the features.

FIG. 5 is a schematic circuit configuration diagram of the emulator main body 100. In this circuit diagram, portions necessary for the description are extracted and shown so as to facilitate understanding of the features of the debugger system. That is, the emulator main body 100 can naturally execute processing corresponding to the command sequence of the flash memory similarly to the emulator main body 2, and in fact, the interrupt control circuit 40, the BUSY status control circuit 42, and the Switch 4
6, and wiring such as a bus connecting them, but they are omitted in FIG. The output of the debugger command detection unit 102 and the output of the flash memory command analysis unit 18 are input to the OR circuit 104, and the output is
Connected to one input of ND circuit 44.

The debugging operation is performed for verifying a program stored in the flash memory and correcting a bug. Therefore, an operation of writing a break instruction in the program is performed. However, when rewriting data in a flash memory, it is necessary to erase data in the entire chip or in block units. It is difficult to efficiently perform a debugging operation with a flash memory. This inefficiency of the debugging work is the same in the present device when the flash memory itself is emulated. That is, in order to efficiently perform a program debugging operation, it is necessary to enable a rewriting operation of only some steps.

The emulator main body 100 responds to this request, and the debugger command detection unit 102 detects the free access request command issued by the target CPU
8 enables the target CPU 30 to directly access the emulation memory 16 without detecting the command sequence of writing or erasing. That is, when the debugger command detection unit 102 detects the free access request command, the emulator main body 100 switches to perform the same operation as a simple RAM as viewed from the target CPU 30. The debugger command detection unit 102
When detecting a free access abandonment command instructing return from the free access mode, the emulator main body 100 is returned from a state where free writing to the emulation memory 16 is possible to a state where the flash memory itself is emulated. The free access request command and the free access abandonment command are extended commands for using the emulator main body 100 as a debugging system, and can be common regardless of the type of flash memory.

More specifically, the debugger command detector 10
When the free access request command from the target CPU 30 is detected, the logical circuit 2 gives the OR circuit 104 a logical value permitting writing to the emulation memory 16. That is, the OR circuit 104 assigns the logical value that permits writing to the emulation memory 16 to the AND circuit 4 irrespective of the output from the flash memory command analysis unit 18 connected to the other input terminal.
Give to 4. Therefore, in this state, whether or not writing to the emulation memory 16 is possible is governed by the signal applied to the other end of the AND circuit 44. This A
The other end of the ND circuit 44 is configured so that a signal to be applied to the WR signal terminal of the flash memory by the target CPU 30 is input, so that the emulation memory 16 can freely write from the target CPU 30 side. (Free access mode).

On the contrary, the debugger command detection unit 102
When a free access abandonment command from the target CPU 30 is detected, a logical value that does not permit writing to the emulation memory 16 is given to the OR circuit 104. In this state, the output of the OR circuit 104 is connected to the flash memory command analysis unit 1 connected to the other input terminal.
8 will be dominated by the output. This is the same configuration as that of the above-described first embodiment. In the AND circuit 44, a write command sequence is issued from the target CPU 30 and a write enable signal to the flash memory is in an active state. Only when these conditions are satisfied, writing of data to the emulation memory 16 is permitted.
This means that the emulator body 100 has returned to the emulation mode of the flash memory.

The emulator main body 100 is a HOL
By issuing the D request to the target CPU 30, it is possible to prevent the target CPU 30 from accessing the flash memory emulated by the present device while the controller 12 is accessing the emulation memory 16. On the other hand, when access from the controller 12 to the emulation memory 16 is completed, H
The OLD request signal is released by setting the OLD request signal to the OFF state, and an access request to the flash memory emulated by the present device from the target CPU 30 is enabled. This prevents the target CPU 30 from running away by trying to access the flash memory during the period in which the access to the emulation memory 16 is not possible.

By the way, the HOL of the target CPU 30
If the controller D is not provided, when the controller 12 accesses the emulation memory 16, for example, the power supply of the target substrate 4 is turned off, the target CPU 30 is stopped, and after the operation of rewriting the program is performed, for example, Is turned on and the program is executed from the beginning. On the other hand, in this device, H
By the OLD means, the execution of the user program to be debugged in the target CPU 30 can be stopped halfway, and after the controller 12 performs a rewriting operation of the emulation memory 16 and the like, the program can be resumed from the position where the program was stopped. That is, according to the present apparatus, in addition to the efficiency of the debugging operation in the free access mode as described above, the efficiency of the debugging operation can be further improved by the HOLD means.

Further, by providing HOLD means,
As described above, the bus for accessing the emulation memory 16 is transferred from the target CPU 30 to the controller 1.
In addition to the effect that the operation of the target CPU 30 is guaranteed when switching to 2, the effect of increasing the efficiency of debugging work, and the effect that there is no need to separately provide a communication path with the device on the target board. That is, specifically, this last effect has an advantage that it is not necessary to specially create a target board having a communication path for debugging.

Next, the operation of the debugging system will be described. The debugging system includes a debugger program (hereinafter, referred to as a ROM debugger) executed on the target CPU 30 and a debugger program (hereinafter, referred to as a host debugger) executed on the host computer 6. ROM debugger and host debugger
While performing the communication, the debug operation of the user program stored in the emulation memory 16 is performed. FIG. 6 is a flowchart showing a schematic process of the ROM debugger, and FIG. 7 is a flowchart showing a schematic process of the host debugger.

In the debugging work, a break instruction for interrupting the processing is written in the user program. When the target CPU 30 executes the break instruction, a software interrupt occurs, and the ROM debugger is activated accordingly. One of the features of the ROM debugger of the present system is that when it is started, it issues the above-mentioned free access request command,
The point is that the data is transferred to the emulator main body 100 via the target bus 24 (S200). As described above, the emulator main body 100 is usually connected to the target CPU 30.
Act as flash memory itself,
When the debugger command detection unit 102 detects this free access request command, the emulation memory 16
It becomes a state where direct access to is possible. That is, by issuing the free access request command, the target C
The PU 30 can handle the emulator main body 100 as a mere RAM.

The debugging operation is performed on the host computer 6 based on a command input by the user (S30).
0). The host debugger repeats the processing loop until an end command is input (S305). If the input command is not the end command, it is checked whether it is an execution control command for instructing step execution or continuous execution (S310).

If the command is an execution control command, a break instruction is written at a desired position in the user program (S
315). The write position of the break instruction is specified by, for example, a user. After saving the instruction code at that position, the host debugger writes a break instruction. Then, the host debugger transmits a step execution command or a continuation execution command to the ROM debugger (S320).

If it is determined in step S310 that the command is another command such as a memory operation, the command is
It is transmitted to the M debugger (S325).

The host debugger performs steps S320 and S325.
When the command is transmitted to the ROM debugger in step S330, the process waits for notification of the processing result of the command by the ROM debugger (S330). For example, when the ROM debugger stops processing due to a break instruction or an error, it notifies the host debugger of the stop. The ROM debugger transfers data obtained by a requested memory operation or the like to the host debugger.

The host debugger performs post-processing for the command requested to the target CPU 30 according to the received processing result (S335). For example, when an error report is received, the command post-processing S335
In, post-processing including error processing is performed. Immediately after a break, post-break processing is performed. In the post-break processing, processing is performed in which the break instruction written in the user program on the emulation memory 16 is written back to the original instruction code. Further, for example, when the requested command is a memory operation or the like, post-processing according to the command is performed.

Thereafter, the host debugger returns to the command input processing S300 again, and repeats the above processing.

On the other hand, the following processing is performed in the ROM debugger. First, as described above, the ROM debugger is activated by the interruption due to the execution of the break instruction written in the user program, and the ROM debugger issues a free access request command, which is one feature of the present invention (S200).

After issuing the free access request command, the ROM debugger shifts to a substantial debugging process. First, it is determined whether the break instruction that caused the interrupt is due to step execution (S20).
5). In the case of step execution, the processing is interrupted by a break instruction every time the user program is executed one step. To realize such program control, RO
The M debugger shifts the position of the break instruction backward by one step on the user program. That is, in the step execution, the instruction code of the user program originally in the n-th step in which the break instruction causing the interruption of the processing is written is written back from the save destination (S21).
0), and the instruction code of the next (n + 1) th step is saved in the temporary buffer of the target CPU 30, and a new break instruction is written in the (n + 1) th step. When the processing of the user program is resumed in this state, the instruction code of the n-th step which has just been written back is executed, and the operation is interrupted again by the break instruction of the (n + 1) -th step. In the step execution, the user program is executed step by step in such a procedure, and the state change of the target system in each step can be closely examined. The process of writing a break instruction in the (n + 1) th step is performed in a subsequent step execution process S240. If the break is not caused by step execution, step S210 is skipped.

Here, the writing back of the instruction code and the writing of the break instruction are performed from the target CPU 30 to the emulation memory 16. At this time, the target CPU 30 is in the free access mode.
Does not need to perform the block erase process, and can overwrite only the target step.

After notifying the host computer 6 of the cause of the stop (S215), the ROM debugger waits for the reception of a command from the host computer 6 (S220). That is, the ROM debugger performs the processing S32 of the host debugger.
0, when the command transmitted in S325 is received, the process proceeds to the next process.

If the received command is a memory operation command (S225), the emulation memory 1
6 is performed (S230). In the case of a memory read process, data is read from a specified address, and the data is transferred to a host debugger. In the case of a memory write process, data is written to a specified address. Upon completion of the memory processing, the process waits for a new command from the new host (S220).

If the received command is a step execution command (S235), a step execution process is performed (S240), and then a free access abandonment command is issued to the emulator main body 100 (S245). As described above, the step execution process is a process of saving an instruction code of an address to be executed next in a user program to a temporary buffer and writing a break instruction at that address.

If the received command is a continuous execution command (S250), the process is restarted with the current user program without writing a new break instruction. At the time of this resumption, a free access abandonment command is also issued (S245). Step S220
If the received command is another non-executed command, processing corresponding to the command is performed (S255), and the process waits for reception of a new command (S220).

The issuance of the free access abandonment command is also a feature of the ROM debugger of the present system. Processing S
At 245, when the free access abandonment command is issued to the emulator main body 100, the emulator main body 100
The debugger command detection unit 102 detects this, and returns the emulator main body 100 from the free access mode to the normal flash memory emulation mode as described above. As a result, the user program stored in the emulation memory 16 can be executed in the same state as read from the actual flash memory and executed. Processing of the restarted user program is continued until the next break instruction. That is,
In the case of step execution, only during the execution of one step,
It will return to emulation mode and will immediately enter debugger mode. On the other hand, when the continuous execution command is received, the break insertion processing S31 of the host debugger is performed.
If there is a next break instruction written in step 5, the processing is continued up to that point.

As described above, the ROM debugger of this system issues the free access request command and the free access abandonment command, thereby causing the emulation memory 16 to behave as a RAM and the free access mode in which the emulation memory 16 can be handled as a RAM. The emulation mode can be freely switched.

In the free access mode characteristic of the present invention, unlike the emulation mode, an operation such as block erasure is not required when writing a break instruction or the like, and data can be rewritten and updated only at the address to be written. So the debugging work is done very efficiently.

A debug instruction from the host debugger operating on the host computer 6 to the ROM debugger is transmitted via the target bus 24, the flash memory emulator adapter 26, and the probe 28. That is, in the present apparatus, there is no need to provide a separate communication path for a debug instruction. To realize this, the above-mentioned HOLD means plays a large role. That is, in the present apparatus, the debug instruction from the host debugger is temporarily written into the emulation memory 16 via the controller 12 and is read out by the ROM debugger via the target bus 24 or the like, so that the transmission of the debug instruction is performed. Will be When writing the debug instruction into the emulation memory 16, the HOLD means stops the target CPU 30. After the debug instruction has been written into the emulation memory 16, HOL
D is released and the target CPU 30 resumes operation.
The ROM debugger program reads and acquires a debug instruction from the emulation memory 16.

The host computer 6 and the target CPU
It is of course possible to provide a configuration in which a separate communication line is provided between the communication device 30 and the device 30 to transmit a debug instruction. By the way, R
The ESET request is provided as means for resetting the target CPU 30 by remote operation.

[0079]

According to the flash memory emulation apparatus of the present invention, the provision of the flash memory command analysis section enables emulation of operations involving command operations unique to the flash memory. An effect is obtained that a test and a failure analysis at the time of product development can be performed with high accuracy without using an actual flash memory. Also,
R to copy the user program during debugging
Since it is not necessary to provide the AM on the target substrate, the size and cost of the product can be reduced. Further, according to the present invention, the flash memory command analysis unit is formed on a programmable semiconductor chip whose hardware configuration can be redefined. Therefore, it is easy to reconfigure the flash memory command analysis unit, and it is possible to easily cope with, for example, a command system that may be different for each maker, and to obtain a versatile device.

Further, the flash memory emulation device of the present invention includes the debugger command detecting section, so that the target circuit can respond to the free access request command issued from the target circuit without passing through a command sequence specific to the flash memory. The mode is switched to a mode in which erasing / rewriting of memory contents can be performed directly. This makes it possible to write a break instruction and change some data in the debugging work without performing a process such as chip erase or block erase, and the effect of dramatically improving the efficiency of the debug work can be obtained.

The flash memory has a limit on the number of times of writing / erasing. However, since the flash memory emulation device of the present invention makes the RAM appear as a flash memory, there is also an advantage that such a number of times is not limited. In other words, frequent writing / erasing does not affect the durability of the device, and does not cause a problem in operation reliability. This is very advantageous for debugging work.

[Brief description of the drawings]

FIG. 1 is a conceptual block diagram of a flash memory emulator according to a first embodiment of the present invention connected to a target substrate.

FIG. 2 is a schematic circuit configuration diagram of an emulator main body according to the first embodiment.

FIG. 3 is an explanatory diagram showing an example of a command sequence unique to a flash memory.

FIG. 4 is a conceptual block diagram of a flash memory emulator according to a second embodiment of the present invention connected to a target substrate.

FIG. 5 is a schematic circuit configuration diagram of an emulator main body for describing a second embodiment.

FIG. 6 is a flowchart showing a schematic process of a ROM debugger.

FIG. 7 is a flowchart showing a schematic process of a host debugger.

[Explanation of symbols]

2,100 emulator body, 4 target boards,
6 host computer, 10 host interface, 1
2 controller, 14 control program memory, 1
6 emulation memory, 18 flash memory command analysis unit, 20 electrical characteristic emulation unit, 22 buffer, 24 target bus, 26 flash memory emulator adapter, 28 probe, 30 target CPU, 102 debugger command detection unit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Katsushi Toma 6-2 Minamikurokawa, Aso-ku, Kawasaki-shi, Kanagawa Prefecture Sophia Systems Microcomputer Works (56) References JP-A-9-244915 (JP, A JP-A-1-217524 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 11/22-11/ ²⁶

Claims (7)

(57) [Claims] 1. A flash memory emulation device connected to a target circuit and constituting an equivalent circuit of a flash memory used in the target circuit, wherein the RA stores a copy of the storage content of the flash memory.
M, the address and data for the flash memory , respectively.
And the flash memory command analyzing unit for detecting a command sequence for selecting a plurality of containing a command issued from the target circuit operation of the flash memory represented by a combination of chromatography data, said RAM, sensed flash memory operation A flash memory emulation device, comprising: a memory operation emulation unit that controls by an operation according to a selection command sequence . 2. A CPU having a flash memory and executing a user program stored in the flash memory
A flash memory emulation device connected to a target circuit having a flash memory emulation device, which constitutes an equivalent circuit of the flash memory, and is used for debugging the user program.
And M, wherein the flash memory command analyzing unit for detecting a command sequence is issued from the target circuit for selecting the operation of the flash memory, the RAM, and control operation according to the detected flash memory operation selected command sequence A memory operation emulation unit, a free access request command issued from the target circuit is detected, and the RAM is read from the target circuit without being restricted by the flash memory operation selection command.
And a debugger command detection unit that enables free writing to the flash memory emulation device. 3. The flash memory emulation device according to claim 1, further comprising means for stopping a CPU of the target circuit while the memory operation emulation unit accesses the RAM. Flash memory emulation device. 4. A debugging system for debugging a user program executed by a CPU of the target circuit using the flash memory emulation device according to claim 1 or 2, wherein the flash memory emulation device comprises: Target C to stop CPU of target circuit
A PU stop unit; and a debug instruction unit that gives a debug instruction to a CPU of the target circuit when debugging a user program stored in a flash memory. The debug instruction unit includes a target CPU stop unit. Storing the debug instruction in the RAM while the CPU is stopped, and reading out the debug instruction stored in the RAM after the stop by the target CPU stop unit is released. And a communication from the debug instructing unit to the CPU is performed by: 5. The flash memory emulation device according to claim 1, wherein the flash memory command analysis unit is a logic circuit configured as hardware. Memory emulation device. 6. The flash memory emulation device according to claim 1, wherein the flash memory command analysis unit is configured to be reconfigurable using a programmable semiconductor chip.
A flash memory emulation device characterized by the above-mentioned. 7. A debugging system for performing the debugging using the flash memory emulation device according to claim 2, wherein the debugger program executed by the CPU of the target circuit is an interrupt processing instruction written in the user program. When the free access request command is issued in response to the command, the mode shifts to a debug mode, and at the end of the debug mode, a free access relinquish command for relinquishing the right of free writing to the RAM is issued. The unit detects the free access abandonment command and outputs the RA from the target circuit.
A debugging system, wherein free writing to M is prohibited, and the writing is entrusted to control of the memory operation emulation unit.