JP3142700B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device used in a high-frequency region above the UHF band and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the progress of semiconductor technology, the degree of integration of semiconductor integrated circuits has been remarkably improved. In particular, the integration of a semiconductor device using a heterojunction can be made submicron due to the development of microfabrication technology.
It is confirmed that it shows excellent characteristics in the high frequency band of z or more,
It has already been put to practical use in many fields. Regarding capacitors in such an integrated circuit, an increase in capacity and a reduction in area have been promoted by a technique of thinning a silicon nitride film or a silicon oxide film.

[0003]

However, a dielectric such as a silicon nitride film or a silicon oxide film which has been conventionally used for forming a capacitor has a small dielectric constant εr (εr <7). If a dielectric such as a silicon nitride film is to be integrated as a capacitor having a large capacitance value such as a bypass capacitor, the ratio of the capacitor to the chip area becomes extremely large, and as a result, the overall area of the chip becomes small. There is a drawback that it is difficult to integrate on a chip. In particular, since a heterojunction semiconductor substrate is expensive and a large chip area leads to an increase in cost, a capacitor made of a dielectric such as a silicon nitride film is not integrated on a large-area heterojunction substrate.

Therefore, for example, it is conceivable to form a capacitor using a high dielectric material.
As a manufacturing method, a heat treatment step at a temperature higher than the hetero-substrate formation temperature is required at the time of forming a high dielectric substance. Therefore, when such a high-temperature heat treatment step is performed, the steepness of the hetero interface of the semiconductor substrate deteriorates, There is a problem that the original characteristics of the junction transistor cannot be obtained.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having a heterojunction transistor in which a capacitor or the like having a large capacitance value is integrated on a chip having a small area and the steepness of a heterointerface is not deteriorated. It is to provide a manufacturing method.

[0006]

In order to solve the above problems SUMMARY OF THE INVENTION The present inventors have found that the result of the extensive studies, as a high-dielectric thin film, at a lower heat treatment temperature than the formation temperature of the heterojunction of the semiconductor substrate It is found that there is a material which can be formed, particularly a high dielectric constant material which is composed of a mixed crystal of barium titanate and strontium titanate and has a composition ratio of barium titanate of 70% or less. A large-capacity capacitor or the like is formed on a semiconductor substrate having a hetero junction.

That is, a specific configuration of the invention according to claim 1 is that a semiconductor device is formed on a semiconductor substrate having a heterojunction and a heat treatment temperature lower than the formation temperature of the heterojunction. and a possible high dielectric thin film, the high dielectric thin film consists of a mixed crystal of barium titanate and strontium titanate, the composition ratio of the barium titanate is 70% or less of the dielectric material constituting It is.

[0008]

[Action] Accordingly, the present invention, as a high dielectric thin film formed on a semiconductor substrate having a heterojunction, the composition ratio of the barium titanate in the mixed crystal of titanium barium strontium titanate 70% Since the following dielectric materials are used, the dielectric constant of the dielectric material is high,
Even with the same film thickness, the area occupied in the chip is reduced as compared with the case where a conventional silicon nitride film or the like is used, and the chip area is significantly reduced.

[0009] Moreover, the high-dielectric thin film, since it is formed at a temperature lower than the formation temperature of the heterojunction of the semiconductor substrate, rapid Shun of the hetero interface of the semiconductor substrate is secured satisfactorily <br/> .

[0010]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to the present invention. The figure shows a field effect transistor (hereinafter abbreviated as MODFET) 2 using a semiconductor substrate having a heterojunction.
0, and a large-capacity capacitor (capacitance element) 21 and a resistance element (not shown) are formed on the semiconductor substrate.

In FIG. 1, reference numeral 1 denotes a semi-insulating semiconductor substrate made of GaAs having a GaAs / AlGaAs heterojunction (modulation doping structure).
And, the formation temperature of the heterojunction is, for example, C. 620 degrees. 2 is an active region of the MODFET 20 formed on the semiconductor substrate 1 by mesa etching, 3 is a SiN film formed on the semiconductor substrate 1, and 4 is an SiO2 film formed on the SiN film 3. .

Reference numeral 5 denotes a lower electrode of the capacitor 21 formed in a region below the step formed by the active region 2 of the MODFET 20.
Is formed on. Reference numeral 6 denotes a dielectric layer of the capacitor 21, which is formed of a thin film using a mixed crystal of barium titanate and strontium titanate (hereinafter abbreviated as BSTO), and has a composition ratio of the barium titanate to the whole. It is made of a dielectric material of 70% or less, and the heat treatment temperature for the formation is a temperature (for example, 600 degrees Celsius) or less, which is lower than the formation temperature (620 degrees Celsius) of the hetero junction of the semiconductor substrate 1. Reference numeral 7 denotes an upper electrode of the capacitor 21.

Further, 8 is an SiO 2 film as a spacer,
9 is an ohmic electrode of the MODFET 20, 10 is a gate electrode, and 11 is a SiN formed on the MODFET 20.
Reference numeral 12 denotes a wiring connecting elements such as the MODFET 20 and the capacitor 21, and reference numeral 13 denotes a wiring connection opening formed in the SiN film 11.

Next, a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to FIG. First, GaAs is deposited on a GaAs semiconductor substrate 1 at 620 degrees Celsius by molecular beam epitaxy.
After growing a heterojunction (modulation doping structure) of s / AlGaAs, the semiconductor substrate 1 is subjected to mesa etching to form a selective active region 2 and a resistor (see FIG. 2A).

Subsequently, the SiO 2 film 3 having a thickness of about 3000
The lower electrode layer 5 of the capacitor 21 made of Pt / Ti is formed on the SiO2 film 3 by the VD method, and the BSTO thin film 6 is further formed on the lower electrode layer 5 by spin coating of a sol-gel liquid of alcoholate. Coating is performed while controlling the number of revolutions, and in an atmosphere where the partial pressure of oxygen or ozone is 0.2 atm or more, the heat treatment temperature is a temperature not higher than the growth formation temperature of the heterojunction of the semiconductor substrate 1 (620 degrees Celsius), For example, by performing sintering at 600 degrees Celsius for one minute, a dielectric layer made of the BSTO thin film 6 of about 2500 ° is formed. Thereafter, a Pt layer is formed on the dielectric layer (BSTO thin film 6) as the upper electrode 7 of the capacitor 21. Thereafter, after patterning the lower portion of the mesa by using photolithography, the upper electrode 5 and the BSTO film 6 other than the portion to be the capacitor 21 are accelerated at an acceleration voltage of 1 keV and a degree of vacuum of 10 -4 torr by ion milling with argon ions. The photoresist 21 is selectively etched and removed under the same conditions, and then the lower electrode 5 is patterned by the photoresist mask using ion milling under the same conditions as above to form the capacitor 21 (see FIG. 2B). .

Thereafter, the SiO2 film 4 is further removed by wet etching using hydrofluoric acid using a photoresist mask, and the SiN film 3 is further removed by low-damage plasma etching using CF4. Expose the surrounding area, 4000Å
Is formed on the entire surface of the substrate 1 by the normal pressure CVD method. Subsequently, a SiO2 film 4 is formed using a photoresist.
Is etched, and a metal of AuGeNi / Au is vacuum-deposited at 2500/2000 ° each, lifted off, and alloyed in an argon atmosphere at 500 ° C. for 5 minutes to form the ohmic electrode 9 of the MODFET 20.
Further, the MODFET 20 is formed using a photoresist mask.
Is patterned, the SiO2 film 4 is etched, and Ti / Pt / Au is formed at 500.degree./1500.
Å / 2000Å MODFET by vacuum deposition
20 gate electrodes 10 are formed (see FIG. 3C).

Finally, after depositing 5000 nm of SiN film 11 by the plasma CVD method, contact holes 13 are formed at predetermined positions of SiN film 11 by reactive ion etching using CF4 gas using a photoresist mask. . Then, Ti / Au is formed on the SiN film 11.
Are deposited 500/5000 each and etched by ion milling using a photoresist mask,
Wirings 12 are formed, and thereafter, if necessary, a silicon oxide film is deposited as a protective film to a thickness of about 5000 °, and necessary portions are opened to complete a semiconductor integrated circuit.

Therefore, in this embodiment, GaAs / A
As a dielectric layer (high dielectric thin film) formed on the semiconductor substrate 1 having a heterojunction of 1GaAs, a BSTO thin film (composed of a mixed crystal of barium titanate and strontium titanate), Since the dielectric material thin film 6 having a barium acid composition ratio of 70% or less is used, the BSTO thin film 6 has a high dielectric constant and can be disposed in a small area of the chip.

Now, the BSTO manufactured under the conditions of this embodiment
FIG. 3A shows a comparison between the dielectric constant .epsilon.r of the thin film 6 and the dielectric constants of the conventional SiN film and SiO2 film. For comparison, FIG. 2B shows the capacitor area required to manufacture a capacitor having a thickness of 100 nm and a capacitance of 1000 pF. As can be seen from the figure, the dielectric constant εr of the BSTO thin film is 320, which is 55 times that of the SiO2 film and 38 times that of the SiN film.
/ 38, so that even if the capacitor 21 has a large capacity, the chip area can be significantly reduced.

In addition, the semiconductor substrate 1 having a hetero junction
The BSTO thin film 6 formed thereon is formed by being heat-treated at a temperature of 600 degrees Celsius, which is less than 620 degrees Celsius, at which the heterojunction is formed. Therefore, the steepness of the hetero interface is not deteriorated and can be effectively maintained.

FIG. 4 shows the result of measuring the frequency characteristics of the capacitor 21 manufactured under the conditions of the above embodiment with the composition ratio x of the BSTO thin film 6. When the composition ratio x is less than 0.7, the high-frequency characteristics exceed 10 GHz, and it can be seen that the SHF band can be covered when x is less than 0.7.

FIG. 5 shows a capacitance change characteristic of the capacitor 21 made of the manufactured BSTO thin film 6 with respect to a temperature change. As can be seen from the figure, since the change in capacitance between -25 ° C. and 85 ° C. is 10% or less, a capacitance change due to a phase change occurring in the BSTO thin film 6 made of ceramic and having a composition ratio x = 0.7 appears. Not.

FIG. 6 shows the relationship between the firing temperature of the BSTO thin film 6 and the dielectric constant. As can be seen from the figure, the dielectric constant sharply increases at a temperature of 500 degrees Celsius or higher. Therefore, in order to form a high dielectric thin film, the upper limit of the heterojunction formation temperature of 6 degrees Celsius is required.
It is desirable to bake in the range of 50 degrees to 500 degrees Celsius.

In this embodiment, the capacitor 21 is
Since the upper and lower portions of the BSTO thin film 6 are completely covered with the silicon nitride film (SiN film), it is possible to prevent the contamination of the MODFET 20 and the like by heavy metals such as Ba and Sr.

Further, in this embodiment, the alloy temperature of the ohmic electrode 9 of the MODFET 20 (that is, 500 degrees Celsius)
Is the heat treatment temperature for forming the BSTO thin film 6 (that is, 6 degrees Celsius).
00 degrees), the problem of deterioration of the BSTO thin film 6 does not occur.

In this embodiment, the MODFET 20
In this case, the capacitor 21 is integrated on the semiconductor substrate 1 that constitutes a part of the semiconductor device 1, so that the circuit configuration is equivalent to that of the present embodiment in which the MODFET alone is connected to the ferroelectric capacitor outside the package as in the related art. As compared with, parasitic inductance components such as wires and leads can be suppressed low,
The characteristics of the MODFET 20 are greatly improved as measured, with a transconductance of 500 mS / mm and a noise figure of 0.5 dB at 12 GHz.

In the present embodiment, the MODFET 20 and the capacitor 21 are separated from each other by mesa etching. However, the device may be separated by ion implantation of protons, oxygen, or the like.

Furthermore, in the present embodiment, the dielectric thin film having a high dielectric constant the example of using as the capacitor insulating film, other capacitive element have use a dielectric thin film having a high dielectric constant, focus It goes without saying that the present invention can be similarly applied to a case where an electric element or a piezoelectric element is formed and is integrated on a heterojunction semiconductor substrate.

[0030]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, a thin film formed on a semiconductor substrate having a heterojunction has a lower temperature than the heterojunction forming temperature of the semiconductor substrate. formation available-at a low heat treatment temperature
Since a high dielectric thin film, that is, a mixed material of barium titanate and strontium titanate and the composition ratio of barium titanate is 70% or less is used, a capacitor using the dielectric material is used. The area occupied by the element in the chip can be reduced, and the chip area can be significantly reduced, and the abruptness of the hetero interface of the semiconductor substrate can be secured well.

In particular, in the case where a dielectric material having a mixed crystal of barium titanate and strontium titanate and having a composition ratio of barium titanate of 70% or less is used as the high dielectric thin film, the formation of the high dielectric thin film is difficult. When the heat treatment is performed at a temperature of 500 to 650 degrees Celsius and in an atmosphere in which the partial pressure of oxygen or ozone is 0.2 atm or more, the characteristics of the heterojunction of the semiconductor substrate can be more favorably secured. .

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the semiconductor device.

FIG. 3 is a diagram showing a comparison between a dielectric constant of a dielectric used in an embodiment of the present invention and a conventional example and an occupied area thereof.

FIG. 4 is a diagram showing frequency characteristics of the semiconductor device of the present invention.

FIG. 5 is a diagram showing temperature characteristics of the semiconductor device of the present invention.

FIG. 6 is a diagram showing a change characteristic of a dielectric constant with respect to a firing temperature of a semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GaAs substrate (semiconductor substrate) 3 SiN film 4 SiO2 film 5 Lower electrode 6 BSTO film 7 Upper electrode 8 Spacer (SiO2 film) 9 Ohmic electrode 10 Gate electrode 11 Interlayer SiN film 12 Wiring 20 Field effect transistor 21 Capacitor

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-129345 (JP, A) JP-A-63-178556 (JP, A) JP-A-5-116913 (JP, A) 116454 (JP, A) JP-A-1-286922 (JP, A) JP-A-2-231754 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/312-21 / 318 H01L 21/32 H01L 21/47-21/475 H01L 21/337 H01L 21/338 H01L 27/095 H01L 29/778 H01L 29/80-29/812

Claims (5)

(57) [Claims] A semiconductor substrate having a heterojunction ; and a forming temperature of the heterojunction formed on the semiconductor substrate.
High dielectric thin film that can be formed at a heat treatment temperature
A semiconductor device , wherein the high dielectric thin film is made of a mixed crystal of barium titanate and strontium titanate, and the composition ratio of the barium titanate is 70% or less. 2. A semiconductor substrate has a step formed by etching a mesa shape, the lower region of the step, the claims, characterized in that the capacitive element made of high-dielectric thin film is formed 1 Symbol mounting semiconductor device. 3. A high-dielectric thin film, the semiconductor device according to claim 1 Symbol mounting, characterized in that the covered around by a silicon nitride film. 4. A semiconductor substrate having a heterojunction forms a part of a field effect transistor, and an alloy temperature of an ohmic electrode of the field effect transistor is set to a temperature lower than a heat treatment temperature of a high dielectric thin film. the semiconductor device of claim 1 Symbol mounting features. 5. A heterojunction is epitaxially formed on a semiconductor substrate.
Le grown, then said on a semiconductor substrate, a high dielectric thin film composition ratio of and the barium titanate consists mixed crystal less 70% of barium titanate and strontium titanate, said hetero contact
Forming at a heat treatment temperature of 500 ° C. to 650 ° C. lower than the growth temperature at the time of the epitaxial growth and a partial pressure of oxygen or ozone of 0.2 atm or more. producing how the semi conductor device you.