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JP3141378B2 - Semiconductor substrate manufacturing method - Google Patents

Semiconductor substrate manufacturing method

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Publication number
JP3141378B2
JP3141378B2 JP01299264A JP29926489A JP3141378B2 JP 3141378 B2 JP3141378 B2 JP 3141378B2 JP 01299264 A JP01299264 A JP 01299264A JP 29926489 A JP29926489 A JP 29926489A JP 3141378 B2 JP3141378 B2 JP 3141378B2
Authority
JP
Japan
Prior art keywords
single crystal
oxide film
crystal layer
concave portion
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP01299264A
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Japanese (ja)
Other versions
JPH03159257A (en
Inventor
文敏 豊川
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NEC Corp
Original Assignee
NEC Corp
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Publication of JPH03159257A publication Critical patent/JPH03159257A/en
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体基板の製造方法に利用され、特に、絶
縁物層上にシリコン半導体単結晶層が設けられているSO
I(Silicon−on−insulator)基板の製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for a method of manufacturing a semiconductor substrate, and particularly, an SO in which a silicon semiconductor single crystal layer is provided on an insulator layer.
The present invention relates to a method of manufacturing an I (Silicon-on-insulator) substrate.

〔概要〕〔Overview〕

本発明は、絶縁物層上にシリコン単結晶層を有する半
導体基板の製造方法において、 シリコン単結晶基板の一主面に所定の寸法および配置
で凹部を設け、熱酸化により全面にシリコン酸化膜を形
成し、凹部の底面を構成するシリコン単結晶層を所定の
厚さに研磨し素子領域となるシリコン単結晶層を形成す
ることにより、 結晶性の優れたSOI基板が得られるようにしたもので
ある。
The present invention relates to a method for manufacturing a semiconductor substrate having a silicon single crystal layer on an insulator layer, wherein a recess is provided with a predetermined size and arrangement on one main surface of the silicon single crystal substrate, and a silicon oxide film is formed on the entire surface by thermal oxidation. By forming and polishing a silicon single crystal layer constituting the bottom surface of the concave portion to a predetermined thickness to form a silicon single crystal layer serving as an element region, an SOI substrate having excellent crystallinity can be obtained. is there.

〔従来の技術〕[Conventional technology]

今日の大規模集積回路は、動作速度の高速化の要請か
ら、種々の改善がなされてきている。しかし、より高速
動作が可能な大規模集積回路を実現するには、大幅な寄
生容量の低減が不可欠である。このような寄生容量の大
幅低減には、絶縁物層上にSi(シリコン)単結晶薄膜を
形成し、このSi単結晶薄膜上に素子を形成するSOI技術
が有望と考えられており、これまでにも種々のSOI基板
の製造方法が提案されている。
Various improvements have been made to today's large-scale integrated circuits in response to demands for higher operating speeds. However, in order to realize a large-scale integrated circuit that can operate at higher speed, it is essential to significantly reduce parasitic capacitance. SOI technology, in which a single-crystal Si (silicon) thin film is formed on an insulator layer and an element is formed on the single-crystal Si thin film, is considered promising for such a drastic reduction in parasitic capacitance. Also, various SOI substrate manufacturing methods have been proposed.

その一つとして、SIMOX(Separation by Im−planted
Oxygen)法が挙げられる。(例えば、泉他、エレクト
ロンレター「K.Izumi et al.Elect−ron Lett.」14巻、
P593、1978年) 第4図(a)および(b)はこのSIMOX法によるSOI基
板の製造工程の一例を示す模式的縦断面図である。第4
図(a)に示すように、Si単結晶基板(以下、Si基板と
いう。)21の表面すなわち素子形成面から、高加速で所
定量の酸素イオン注入24を行い、イオン注入損傷層22を
形成する。次いで、第4図(b)に示すように、高温熱
処理を施して注入された酸素と基板のSiとを化学結晶さ
せて埋込みSi酸化膜層23とし、かつ、この埋込みSi酸化
膜23の上部を薄いSi単結晶層25として素子形成領域に供
するというものである。
One of them is SIMOX (Separation by Im-planted
Oxygen) method. (For example, Izumi et al., Electron Letter "K. Izumi et al. Elect-ron Lett." Volume 14,
(P593, 1978) FIGS. 4 (a) and 4 (b) are schematic longitudinal sectional views showing an example of a manufacturing process of an SOI substrate by the SIMOX method. 4th
As shown in FIG. 1A, a predetermined amount of oxygen ions 24 are implanted at a high acceleration from a surface of a Si single crystal substrate (hereinafter, referred to as a Si substrate) 21, that is, an element formation surface, to form an ion implantation damaged layer 22. I do. Next, as shown in FIG. 4 (b), a high-temperature heat treatment is performed to chemically crystallize the implanted oxygen and the Si of the substrate to form a buried Si oxide film layer 23, and an upper part of the buried Si oxide film 23. Is provided as a thin Si single crystal layer 25 to the element formation region.

SIMOX法は、絶縁膜上に多結晶Si(あるいは非晶質S
i)を堆積し、これを大径結晶粒に育成する方法や、Si
選択エピタキシャル成長を応用して、下地Si基板から絶
縁膜上にSi単結晶を成長する方法と比較して、大面積で
かつ、比較的結晶性の優れた絶縁膜上のSi単結晶層を形
成できることから、最も有望なSOI基板の製造方法と考
えられている。
SIMOX method uses polycrystalline Si (or amorphous S
i) depositing and growing this into large-diameter grains,
The ability to form a Si single crystal layer on an insulating film with a large area and relatively excellent crystallinity compared to the method of growing a Si single crystal on an insulating film from an underlying Si substrate by applying selective epitaxial growth Therefore, it is considered to be the most promising SOI substrate manufacturing method.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

前述したSIMOX法によるSOI基板の製造方法では、後に
素子が形成される基板表面を通して、高加速で大容量の
酸素をイオン注入するため、素子形成領域となるSi層の
結晶性回復が不充分であったり、第4図(b)に示すよ
うに、埋込みSi酸化膜23とSi単結晶層25との界面に結晶
欠陥26が誘起されやすい問題がある。このようなSi層の
結晶性回復および界面の結晶欠陥の消去は、イオン注入
後の熱処理を1200℃以上に高温化することである程度改
善される。
In the above-described method for manufacturing an SOI substrate by the SIMOX method, since high-capacity oxygen is ion-implanted at high acceleration through the substrate surface on which an element is to be formed later, the crystallinity recovery of the Si layer serving as the element formation region is insufficient. In addition, as shown in FIG. 4 (b), there is a problem that a crystal defect 26 is easily induced at the interface between the buried Si oxide film 23 and the Si single crystal layer 25. Such recovery of the crystallinity of the Si layer and elimination of crystal defects at the interface can be improved to some extent by raising the temperature of the heat treatment after the ion implantation to 1200 ° C. or higher.

しかし、埋込みSi酸化膜23と素子形成領域となるSi単
結晶層25との界面の結晶欠陥26を完全に消去する方法
は、現在も確立されていない(例えば、吉野明他、電子
情報通信学会、技術研究報告、SDM87−39,P73、1987年
参照)。これらの結晶欠陥26は後に形成される素子のリ
ーク特性劣化の原因となるもので、従来提案されている
SIMOX法によるSOI基板の製造方法の最大の欠点である。
However, a method for completely erasing crystal defects 26 at the interface between the buried Si oxide film 23 and the Si single crystal layer 25 serving as an element formation region has not yet been established (for example, Akira Yoshino et al., IEICE). , Technical Research Report, SDM87-39, P73, 1987). These crystal defects 26 cause deterioration of leak characteristics of an element to be formed later, and have been conventionally proposed.
This is the biggest drawback of the SOI substrate manufacturing method by the SIMOX method.

以上のような欠点は、埋込みSi酸化膜23の形成と同時
に、酸素のイオン注入により非晶質化した表面Si層を再
結晶化する製造手順、すなわち、埋込みSi酸化膜23上に
改めてSi単結晶層25を形成する製造手順をとるかぎりは
避けられない。これは前述の絶縁膜上でのSi層(非晶質
もしくは多結晶Si層)の固相エピタキシャル成長やSi選
択エピタキシャル成長を応用する場合も同様である。
The drawbacks described above are a manufacturing procedure for recrystallizing the surface Si layer which has been made amorphous by ion implantation of oxygen at the same time as the formation of the buried Si oxide film 23, that is, a single Si step on the buried Si oxide film 23. It is inevitable that a manufacturing procedure for forming the crystal layer 25 is taken. The same applies to the case where solid-phase epitaxial growth or selective Si growth of a Si layer (amorphous or polycrystalline Si layer) on the above-mentioned insulating film is applied.

本発明の目的は、前記の欠点を除去することにより、
結晶欠陥の発生を防止し、優れた結晶性を有するSOI基
板を製造できる。半導体基板の製造方法を提供すること
にある。
The object of the present invention is to eliminate the disadvantages mentioned above,
An SOI substrate having excellent crystallinity can be manufactured by preventing generation of crystal defects. An object of the present invention is to provide a method for manufacturing a semiconductor substrate.

〔問題点を解決するための手段〕[Means for solving the problem]

本発明は、シリコン単結晶基板に形成された絶縁膜上
にシリコン単結晶層を有する半導体基板の製造方法にお
いて、前記シリコン単結晶基板の一主面に所定の寸法お
よび配置で複数の凹部を形成する工程と、この凹部の形
成されたシリコン単結晶基板の全面を熱酸化し所定の厚
さのシリコン酸化膜を形成する工程と、前記凹部が形成
されていない側の主面を研磨して前記凹部の底部を構成
するシリコン単結晶層を所定の厚さまで薄膜化し素子形
成領域となるシリコン単結晶層を形成する工程と、シリ
コン酸化膜が形成された凹部の両角部分のみを所定の幅
で選択的に酸化して前記凹部の底面のシリコン酸化膜の
両端部分に所定の大きさのシリコン酸化膜の突起部を形
成する工程と、前記凹部の底面を構成するシリコン単結
晶層を前記突起部の面まで研磨する工程とを含むことを
特徴とする。
The present invention relates to a method for manufacturing a semiconductor substrate having a silicon single crystal layer on an insulating film formed on a silicon single crystal substrate, wherein a plurality of recesses are formed with a predetermined size and arrangement on one main surface of the silicon single crystal substrate. Forming a silicon oxide film having a predetermined thickness by thermally oxidizing the entire surface of the silicon single crystal substrate having the concave portions formed thereon, and polishing the main surface on the side where the concave portions are not formed by polishing. A step of thinning the silicon single crystal layer forming the bottom of the recess to a predetermined thickness to form a silicon single crystal layer to be an element formation region, and selecting only a predetermined width of both corners of the recess in which the silicon oxide film is formed Forming a projection of a silicon oxide film of a predetermined size on both ends of the silicon oxide film on the bottom surface of the concave portion, and forming a silicon single crystal layer forming the bottom surface of the concave portion on the bottom portion of the concave portion. Characterized in that it comprises a step of polishing until.

また、本発明は、前記凹部の熱酸化工程が完了した
後、前記凹部を塗布焼成シリコン酸化膜で埋める工程を
追加して実施することができる。
Further, the present invention can be implemented by adding a step of filling the recess with a coated and baked silicon oxide film after the completion of the thermal oxidation step of the recess.

〔作用〕[Action]

前述した従来のSOI基板の製造方法に対し、本発明
は、素子形成領域は、常時、単結晶の状態が維持され、
埋込みSi酸化膜は、Si基板裏面を熱酸化することで形成
するため、素子が形成されるSi単結晶層と埋込みSi酸化
膜との界面には、結晶血管が全く発生せず、優れた結晶
性を有するSOI基板を得ることができる。
In contrast to the above-described conventional method of manufacturing a SOI substrate, the present invention provides that the element formation region is always maintained in a single crystal state,
Since the buried Si oxide film is formed by thermally oxidizing the back surface of the Si substrate, no crystal blood vessels are generated at the interface between the Si single crystal layer on which the element is formed and the buried Si oxide film, and excellent crystallization is achieved. Thus, an SOI substrate having properties can be obtained.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明す
る。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第1図(a)は本発明の実施例における初期工程の概
要を示すSOI基板の模式的縦断面図、および第1図
(b)はその平面図で、第1図(a)は第1図(b)の
AA′断面図である。
FIG. 1A is a schematic longitudinal sectional view of an SOI substrate showing an outline of an initial step in an embodiment of the present invention, and FIG. 1B is a plan view thereof, and FIG. (B)
It is AA 'sectional drawing.

伝導型P型、比抵抗10Ω−cm、面方位〈100〉で、両
面を鏡面研磨した直径100mm、厚さ400μmのSi基板1の
一主面に、縦15mm、横15mm、深さ350μmの凹部2を10m
m間隔で形成する。
Conductive P-type, specific resistance 10Ω-cm, plane orientation <100>, mirror-polished on both sides, 100 mm diameter, 400 μm thick Si substrate 1 with one main surface, 15 mm long, 15 mm wide, 350 μm deep recess 2 for 10m
Formed at m intervals.

第2図(a)および(b)は、本発明の参考例の主要
製造工程におけるSOI基板の模式的縦断面図で、第1図
(a)および(b)で示した初期工程において、凹部2
が形成された以後の工程について、一つの凹部2に着目
して示したものである。なお、説明の便宜上、上下を逆
転して図を描いてある。
2 (a) and 2 (b) are schematic longitudinal sectional views of an SOI substrate in a main manufacturing process according to a reference example of the present invention. In the initial process shown in FIGS. 1 (a) and 1 (b), a concave portion is shown. 2
Are shown focusing on one recess 2. In addition, for convenience of explanation, the drawing is drawn upside down.

第1図(a)に示したように凹部2を形成したSi基板
1を、水素燃焼酸化により1000℃で酸化し、第2図
(a)に示すように、厚さ1.1μmのSi酸化膜3を形成
する。次に、凹部2に塗布焼成酸化膜4を埋め、凹凸を
平坦化する。
The Si substrate 1 on which the recesses 2 are formed as shown in FIG. 1A is oxidized at 1000 ° C. by hydrogen combustion oxidation, and as shown in FIG. 2A, a 1.1 μm thick Si oxide film is formed. Form 3 Next, the concave / convex oxide film 4 is buried in the concave portion 2 to flatten the irregularity.

その後、第2図(b)に示すように、凹部2が形成さ
れていない側のSi酸化膜3を除去し、Si単結晶面を露出
させる。続いて、アルミナ等の微細砥粒で約45μmの研
磨取り代でSi単結晶面を研磨し、さらに鏡面研磨仕上げ
でSi酸化膜3上のSi単結晶層5を厚さ0.3μmで形成
し、素子形成領域とする。
Thereafter, as shown in FIG. 2 (b), the Si oxide film 3 on the side where the recess 2 is not formed is removed, exposing the Si single crystal plane. Subsequently, the Si single crystal surface is polished with a polishing allowance of about 45 μm using fine abrasive grains such as alumina, and the Si single crystal layer 5 on the Si oxide film 3 is formed to a thickness of 0.3 μm by mirror polishing. This is an element formation region.

本参考例で作製したSOI基板の下地のSi酸化膜3と、
素子形成領域となるSi単結晶層5との界面を、透過電子
顕微鏡で観察した結果、界面における結晶欠陥は皆無で
あった。一方従来のSIMOX法(酸素注入条件180KeV、1.5
×1018/cm2、熱処理条件1280℃3時間)によるSOI基板
では、埋込みSi酸化膜と上部Si単結晶層との界面には多
数の積層欠陥と双晶が観察され、本発明の優位性が確か
められた。
A Si oxide film 3 as a base of the SOI substrate manufactured in this reference example,
As a result of observing the interface with the Si single crystal layer 5 as the element formation region using a transmission electron microscope, there was no crystal defect at the interface. On the other hand, the conventional SIMOX method (oxygen injection conditions 180 KeV, 1.5
In the SOI substrate under the conditions of × 10 18 / cm 2 and heat treatment at 1280 ° C. for 3 hours, a large number of stacking faults and twins are observed at the interface between the buried Si oxide film and the upper Si single crystal layer. Was confirmed.

第3図(a)〜(d)は本発明の実施例の主要製造工
程におけるSOI基板の模式的縦断面図で、参考例と同様
の表し方をしてある。
3 (a) to 3 (d) are schematic vertical sectional views of an SOI substrate in a main manufacturing process according to an embodiment of the present invention, in the same manner as in the reference example.

第3図(a)に示すように、Si基板11に縦15mm、横15
mm、深さ350μmの凹部12を形成した。このSi基板11を
第3図(b)に示すように、乾燥酸素雰囲気中1000℃で
酸化し、厚さ0.04μmのSi酸化膜13を形成した後、化学
気相成長法により、厚さ0.1μmのSi窒化膜16を堆積し
た。
As shown in FIG. 3A, the Si substrate 11 is 15 mm long and 15 mm wide.
The concave portion 12 having a depth of 350 μm was formed. This Si substrate 11 is oxidized in a dry oxygen atmosphere at 1000 ° C. to form a 0.04 μm-thick Si oxide film 13 as shown in FIG. 3 (b). A μm Si nitride film 16 was deposited.

この後、第3図(c)に示すように、凹部12の壁面か
ら500μmの幅でSi窒化膜16を除去し、さらに1000℃の
水素燃焼酸化により、Si窒化膜除去部のSi酸化膜13の厚
さを0.7μmとし突起部17を形成し、凹部12を塗布焼成
酸化膜14で埋め、平坦化した。
Thereafter, as shown in FIG. 3C, the Si nitride film 16 is removed from the wall surface of the concave portion 12 with a width of 500 μm, and further subjected to hydrogen combustion oxidation at 1000 ° C. to remove the Si oxide film 13 in the Si nitride film removed portion. The projections 17 were formed with a thickness of 0.7 μm, and the recesses 12 were filled with a coated and baked oxide film 14 and planarized.

続いて、第3図(d)に示すように、凹部12が形成さ
れていない側のSi窒化膜16およびSi酸化膜13を除去し、
アルミナ等の微細砥粒で約45μm粗研磨し、さらに、ピ
ペラジン(NH(CH24NH)によるSi選択研磨技術(浜口
他、電子情報通信学会、技術研究報告、SSD86−13、P3
7、1986年参照)、により仕上げ研磨を行った。ピペラ
ジンによる選択研磨では、Siだけが研磨され、Si酸化物
は研磨されないため、第3図(d)に示したように、凹
部12の壁面近傍に形成された0.7μmのSi酸化膜が、段
差0.3μmのSi酸化物の突起部17としてSi単結晶側へ突
き出して、Si選択研磨のストッパーとしての役割を果た
す。従って、素子形成領域となる薄いSi単結晶層15の厚
さは、Si酸化物の突起部17の段差と等しい値をとるよう
制御される。
Subsequently, as shown in FIG. 3D, the Si nitride film 16 and the Si oxide film 13 on the side where the concave portion 12 is not formed are removed,
Approximately 45 μm rough polishing with fine abrasive grains such as alumina, and further, Si selective polishing technology using piperazine (NH (CH 2 ) 4 NH) (Hamaguchi et al., IEICE, Technical Report, SSD86-13, P3
7, 1986). In the selective polishing using piperazine, only Si is polished and Si oxide is not polished. Therefore, as shown in FIG. 3D, the 0.7 μm Si oxide film formed near the wall surface of the concave portion 12 It protrudes toward the Si single crystal as a projection 17 of a 0.3 μm Si oxide, and serves as a stopper for selective polishing of Si. Therefore, the thickness of the thin Si single crystal layer 15 that is to be an element formation region is controlled to have a value equal to the step of the projection 17 of the Si oxide.

この実施例では、素子形成領域となる薄いSi単結晶層
15の厚さを制御する工程が付加されていることから、薄
いSi単結晶層15の厚さの均一性が大幅に改善できる利点
がある。参考例では、Si単結晶層5の厚さが0.3μmと
なるよう製造した場合、バラツキが±(0.1〜0.2)μm
程度であったのに対し、第二実施例では、Si単結晶層15
の厚さのバラツキは±(0.005〜0.015)μmであった。
In this embodiment, a thin Si single crystal layer serving as an element formation region is used.
Since the step of controlling the thickness of the thin 15 is added, there is an advantage that the uniformity of the thickness of the thin Si single crystal layer 15 can be greatly improved. In the reference example, when the silicon single crystal layer 5 is manufactured to have a thickness of 0.3 μm, the variation is ± (0.1 to 0.2) μm.
On the other hand, in the second embodiment, the Si single crystal layer 15
Was ± (0.005 to 0.015) μm.

なお、参考例および実施例共に、Si基板に凹部を形成
する際、縦15mm、横15mm、深さ350μmとしたが、本発
明の製造工程および、後の素子製造工程で、機械強度を
維持できるものであれば任意に変更可能である。
In addition, in both the reference example and the example, when forming the concave portion on the Si substrate, the length was 15 mm, the width was 15 mm, and the depth was 350 μm.However, in the manufacturing process of the present invention and the subsequent device manufacturing process, the mechanical strength can be maintained. It can be arbitrarily changed as long as it is a thing.

また、実施例では、Si酸化物の突起部17の段差を0.3
μmとするため、凹部壁面近傍の厚い酸化膜の厚さを0.
7μmとしたが、これは素子形成領域となるSi単結晶層
の厚さを設定するために任意に変更可能であり、実施例
に記載された値に限定されるものではない。
Further, in the embodiment, the step of the projection 17 of the Si oxide is set to 0.3
μm, the thickness of the thick oxide film near the wall surface of the recess is set to 0.
The thickness is set to 7 μm, but this can be arbitrarily changed in order to set the thickness of the Si single crystal layer to be an element formation region, and is not limited to the value described in the embodiment.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明は、Si基板の素子形成領
域の裏面側にSiの熱酸化膜を形成し、これを下地の絶縁
膜としてSOI構造を完成させるものであり、下地絶縁膜
と、素子形成領域となるSi単結晶層との界面に発生する
結晶欠陥を完全に抑制できる効果がある。
As described above, the present invention forms a thermal oxide film of Si on the back surface side of the element formation region of the Si substrate, and completes the SOI structure using this as a base insulating film. This has the effect of completely suppressing crystal defects occurring at the interface with the Si single crystal layer that is to be an element formation region.

従って、本発明によれば、結晶性の優れた、大面積の
SOI基板を容易に製造することが可能となり、その効果
は大である。
Therefore, according to the present invention, excellent crystallinity, large area
The SOI substrate can be easily manufactured, and the effect is great.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)および(b)は本発明の実施例における初
期工程の概要を示すSOI基板の模式的縦断面図および平
面図。
FIGS. 1A and 1B are a schematic longitudinal sectional view and a plan view of an SOI substrate showing an outline of an initial step in an embodiment of the present invention.

【図2】本発明の参考例の主要製造工程におけるSOI基
板の模式的縦断面図。
FIG. 2 is a schematic longitudinal sectional view of an SOI substrate in a main manufacturing process according to a reference example of the present invention.

【図3】本発明の実施例の主要製造工程におけるSOI基
板の模式的縦断面図。 第4図(a)および(b)は従来例の主要製造工程にお
けるSOI基板の模式的縦断面図。 1、11、21……Si基板、2、12……凹部、3、13……Si
酸化膜、4、14……塗布焼成酸化膜、5、15、25……Si
単結晶層、16……Si窒化膜、17……突起部、22……イオ
ン注入損傷層、23……埋込みSi酸化膜、24……酸素イオ
ン注入、26……結晶欠陥。
FIG. 3 is a schematic longitudinal sectional view of an SOI substrate in a main manufacturing process according to an embodiment of the present invention. 4 (a) and 4 (b) are schematic longitudinal sectional views of an SOI substrate in a main manufacturing process of a conventional example. 1, 11, 21 ... Si substrate, 2, 12 ... recess, 3, 13 ... Si
Oxide film, 4, 14… Coated and baked oxide film, 5, 15, 25… Si
Single crystal layer, 16 ... Si nitride film, 17 ... Protrusion, 22 ... Implantation damaged layer, 23 ... Buried Si oxide film, 24 ... Oxygen ion implantation, 26 ... Crystal defect.

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/70 H01L 21/74 - 21/764 H01L 21/768 H01L 21/78 H01L 21/3205 H01L 21/3213 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/70 H01L 21/74-21/764 H01L 21/768 H01L 21/78 H01L 21/3205 H01L 21 / 3213

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】絶縁膜上にシリコン単結晶層を有する半導
体基板の製造方法であって、 シリコン単結晶基板の一主面に所定の寸法および配置で
複数の凹部を形成する工程と、 この凹部の形成されたシリコン単結晶基板の全面を熱酸
化し所定の厚さのシリコン酸化膜を形成する工程と、 前記凹部が形成されていない側の主面を研磨して前記凹
部の底部を構成するシリコン単結晶層を所定の厚さまで
薄膜化し素子形成領域となるシリコン単結晶層を形成す
る工程と、 シリコン酸化膜が形成された凹部の両角部分のみを所定
の幅で選択的に酸化して前記凹部の底面のシリコン酸化
膜と両端部分に所定の大きさのシリコン酸化膜の突起部
を形成する工程と、 前記凹部の底面を構成するシリコン単結晶層を前記突起
部の面まで研磨する工程とを含むことを特徴とする半導
体基板の製造方法。
1. A method of manufacturing a semiconductor substrate having a silicon single crystal layer on an insulating film, comprising the steps of: forming a plurality of recesses with a predetermined size and arrangement on one main surface of a silicon single crystal substrate; Forming a silicon oxide film of a predetermined thickness by thermally oxidizing the entire surface of the silicon single crystal substrate on which is formed, and polishing the main surface on the side where the recess is not formed to form the bottom of the recess A step of thinning the silicon single crystal layer to a predetermined thickness to form a silicon single crystal layer to be an element formation region; and selectively oxidizing only two corners of the concave portion in which the silicon oxide film is formed with a predetermined width. Forming a silicon oxide film on the bottom surface of the concave portion and a protrusion of a silicon oxide film of a predetermined size on both end portions; polishing the silicon single crystal layer constituting the bottom surface of the concave portion to the surface of the protrusion portion; Including The method of manufacturing a semiconductor substrate according to claim.
【請求項2】前記凹部の熱酸化工程が完了した後、前記
凹部を塗布焼成シリコン酸化膜で埋める工程を含む請求
項1記載の半導体基板の製造方法。
2. The method of manufacturing a semiconductor substrate according to claim 1, further comprising the step of filling the concave portion with a coated and baked silicon oxide film after the completion of the thermal oxidation step of the concave portion.
JP01299264A 1989-11-17 1989-11-17 Semiconductor substrate manufacturing method Expired - Fee Related JP3141378B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP01299264A JP3141378B2 (en) 1989-11-17 1989-11-17 Semiconductor substrate manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01299264A JP3141378B2 (en) 1989-11-17 1989-11-17 Semiconductor substrate manufacturing method

Publications (2)

Publication Number Publication Date
JPH03159257A JPH03159257A (en) 1991-07-09
JP3141378B2 true JP3141378B2 (en) 2001-03-05

Family

ID=17870288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01299264A Expired - Fee Related JP3141378B2 (en) 1989-11-17 1989-11-17 Semiconductor substrate manufacturing method

Country Status (1)

Country Link
JP (1) JP3141378B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100511903B1 (en) * 1999-06-29 2005-09-02 주식회사 하이닉스반도체 Method of manufacturing SOI substrate

Also Published As

Publication number Publication date
JPH03159257A (en) 1991-07-09

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