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JP3090561B2 - Semiconductor device thin film forming method - Google Patents

Semiconductor device thin film forming method

Info

Publication number
JP3090561B2
JP3090561B2 JP05145070A JP14507093A JP3090561B2 JP 3090561 B2 JP3090561 B2 JP 3090561B2 JP 05145070 A JP05145070 A JP 05145070A JP 14507093 A JP14507093 A JP 14507093A JP 3090561 B2 JP3090561 B2 JP 3090561B2
Authority
JP
Japan
Prior art keywords
thin film
gas
based gas
semiconductor device
reaction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP05145070A
Other languages
Japanese (ja)
Other versions
JPH0722316A (en
Inventor
晋介 水野
克之 六平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to JP05145070A priority Critical patent/JP3090561B2/en
Priority to US08/259,584 priority patent/US5571571A/en
Publication of JPH0722316A publication Critical patent/JPH0722316A/en
Application granted granted Critical
Publication of JP3090561B2 publication Critical patent/JP3090561B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板等の試料面
に薄膜を形成するプラズマ励起CVD(Plasma Enhance
d CVD)法を適用した半導体装置の薄膜形成方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma enhanced CVD (Plasma Enhancement) for forming a thin film on a sample surface such as a semiconductor substrate.
The present invention relates to a method for forming a thin film of a semiconductor device to which the (dCVD) method is applied.

【0002】[0002]

【従来の技術】従来、半導体基板等の試料面に薄膜を形
成するためには、プラズマ励起CVD(以下、PECV
Dという)装置の反応容器内にプラズマを発生させると
共に、この反応容器内に導入した反応ガスをプラズマ放
電エネルギーを用いて活性化させ、この反応ガスの化学
的気相成長によって生成される沈積物の試料面への被着
を推進させるプラズマ励起CVD法が、広く適用されて
いる。
2. Description of the Related Art Conventionally, in order to form a thin film on a sample surface such as a semiconductor substrate, a plasma-enhanced CVD (hereinafter referred to as PECV) has been proposed.
A plasma is generated in a reaction vessel of the apparatus, and a reaction gas introduced into the reaction vessel is activated by using plasma discharge energy, and a deposit generated by chemical vapor deposition of the reaction gas is generated. The plasma-excited CVD method for promoting the deposition on the sample surface is widely applied.

【0003】ここで、反応ガスとしては、例えば、半導
体基板の表面にSiO2 薄膜を被着させるために、Si
4 系ガス(シラン系ガス)やTEOS(テトラエチル
オルソシリケート)系ガスが適用されている。
Here, as a reaction gas, for example, Si is used to deposit a SiO 2 thin film on the surface of a semiconductor substrate.
An H 4 -based gas (silane-based gas) or a TEOS (tetraethyl orthosilicate) -based gas is used.

【0004】[0004]

【発明が解決しようとする課題】ところで、近年の更な
る高密度半導体集積装置(VLSI)の実現要求に伴
い、サブミクロンでの微細化生成技術の開発が極めて重
要になってきた。そこで、従来のプラズマ励起CVD法
によって生成される薄膜の形状を実験的に検証すること
によって、従来技術によるサブミクロン化への適用可能
性を調べた。
By the way, with the demand for realizing a further high-density semiconductor integrated device (VLSI) in recent years, the development of a submicron miniaturization generation technology has become extremely important. Therefore, by experimentally verifying the shape of a thin film formed by the conventional plasma-excited CVD method, the applicability of the conventional technology to submicronization was examined.

【0005】図4(a)〜(f)は、前記PECVD装
置の反応容器内に設けられている対向電極間に13.5
6MHz等の高周波電力を印加することによってプラズ
マを発生させると共に、反応容器内にSiH4 系の反応
ガスを導入することにより半導体基板表面のSiO2
化膜上及びその表面に形成されているAl配線上に絶縁
被覆のためのSiO2 薄膜を形成した場合の縦断面形状
を示す。尚、同図は顕微鏡写真をトレースして示したも
のである。
FIGS. 4 (a) to 4 (f) show 13.5 between counter electrodes provided in a reaction vessel of the PECVD apparatus.
Plasma is generated by applying a high-frequency power such as 6 MHz, and Al wiring formed on the SiO 2 oxide film on the surface of the semiconductor substrate and on the surface by introducing a SiH 4 -based reaction gas into the reaction vessel. The vertical cross-sectional shape when an SiO 2 thin film for insulating coating is formed is shown above. The figure is a trace of a micrograph.

【0006】かかる実験結果から明らかなように、Si
2 薄膜は、側面が凸状の丸みを持ち且つその頭部より
も基部の方が抉れたような埋込能力の悪い成膜形状とな
るので、Al配線の底部近傍にボイド(隙間)が発生す
る問題がある。特に、Al配線間の隙間間隔が小さくな
るサブミクロンでの高密度配線(図4(e)(f)参
照)にあっては極めて深刻な問題を招来する。
[0006] As is apparent from the above experimental results, Si
Since the O 2 thin film has a rounded shape with a convex side surface and has a poor embedding ability such that the base is hollowed out from the head, a void (gap) is formed near the bottom of the Al wiring. There is a problem that occurs. In particular, a very serious problem is caused in a high-density wiring at a submicron where the gap between the Al wirings is small (see FIGS. 4E and 4F).

【0007】図5(a)〜(f)は、前記PECVD装
置の反応容器内に設けられている対向電極間に13.5
6MHzの高周波電力を印加することにより反応容器内
にプラズマを発生させる共に、反応容器内にTEOS系
ガスを導入することにより、半導体基板表面のSiO2
酸化膜上及びその表面に形成されているAl配線上に更
に絶縁被覆のためのSiO2 薄膜を形成した場合の実験
結果(縦断面図)を示す。尚、図5も顕微鏡写真をトレ
ースして示したものである。
FIGS. 5 (a) to 5 (f) show 13.5 between counter electrodes provided in a reaction vessel of the PECVD apparatus.
Plasma is generated in the reaction vessel by applying a high-frequency power of 6 MHz, and a TEOS-based gas is introduced into the reaction vessel, thereby forming SiO 2 on the surface of the semiconductor substrate.
The experimental results (longitudinal sectional view) when an SiO 2 thin film for insulating coating is further formed on the oxide film and the Al wiring formed on the surface thereof are shown. FIG. 5 also shows a trace of a micrograph.

【0008】この実験結果によれば、図5(a)〜
(f)から明らかなように、形成されたSiO2 薄膜の
側壁部分の形状が図4(a)〜(f)の場合と較べて丸
みを有さず、この結果、ボイド発生の低減化が実現され
た。したがって、生成薄膜の制御性の向上に大きく貢献
した技術と言える。
According to the results of this experiment, FIG.
As is apparent from FIG. 4F, the shape of the side wall portion of the formed SiO 2 thin film is not round as compared with the case of FIGS. 4A to 4F, and as a result, the generation of voids is reduced. It was realized. Therefore, it can be said that the technique has greatly contributed to the improvement of the controllability of the generated thin film.

【0009】このように、SiH4 系の反応ガスを用い
るよりもTEOS系ガスを用いる方が高密度の薄膜を形
成するのに好適であるが、図5(e)(f)に示すよう
に、Al配線の相互間隔が狭くなるサブミクロンでの更
なる高密薄膜生成にあっては埋込能力が十分に発揮され
なくなるので、ボイドの低減化が不十分であり、TEO
S系ガスを適用しても更なる高密度化の要求に対応する
ことが困難である。
As described above, the use of a TEOS-based gas is more suitable for forming a high-density thin film than the use of a SiH 4 -based reaction gas, but as shown in FIGS. In order to form a denser thin film at a submicron where the distance between Al wirings is narrower, the burying ability is not sufficiently exhibited.
Even if an S-based gas is applied, it is difficult to meet the demand for higher density.

【0010】更に、かかる成膜形状及び埋込特性の向上
を図るために、O3 −TEOS系ガスを用いた常圧CV
D法による技術が知られているが、この製造技術によっ
て形成された酸化薄膜は吸湿性が高くなるために、最終
的に製造される半導体集積装置の耐湿性が低下するとい
う問題があった。
[0010] Further, in order to improve the film formation shape and the embedding characteristics, a normal pressure CV using an O 3 -TEOS-based gas is used.
Although the technique by the D method is known, the oxide thin film formed by this manufacturing technique has a high hygroscopicity, and thus has a problem that the moisture resistance of a finally manufactured semiconductor integrated device is reduced.

【0011】本発明は、このような従来のPECVD法
の問題点に鑑みて成されたものであり、更なる高密度化
・高信頼性化に対応し得る半導体装置の薄膜形成方法を
提供することを目的とする。
The present invention has been made in view of such problems of the conventional PECVD method, and provides a method of forming a thin film of a semiconductor device which can cope with higher density and higher reliability. The purpose is to:

【0012】[0012]

【課題を解決するための手段】かかる目的を達成するた
めに本発明は、単一周波数の高周波電力により反応容器
内にプラズマを発生させ、前記反応容器内に導入した反
応ガスをプラズマ放電エネルギーを用いて活性化させる
ことにより、前記反応ガスの化学的気相成長によって生
成される沈積物を試料面へ被着させる半導体装置の薄膜
形成方法において、前記反応ガスとして、TEOS系ガ
スとハロゲン系ガスとの混合ガスを前記反応容器内に導
入することにより、ハロゲン原子を取り込んで低誘電率
となる前記沈積物を前記試料面へ被着させることを特徴
とする。また、前記ハロゲン系ガスは、飽和炭素骨格を
有するハロゲン系ガスであり、CF4、CHF3、C
26、CCl4、CCl22、C38のいずれか一つの
ガスを適用する。また、前記ハロゲン系ガスは、F2
Cl2、NF3、SF6、SiF4、SiCl4、ClF3
BCl3、HCl、HBr、HFのいずれか一つのガス
を適用する。
SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of generating plasma in a reaction vessel by using a single-frequency high-frequency power, and converting a reaction gas introduced into the reaction vessel into a plasma discharge energy. In the method for forming a thin film of a semiconductor device, wherein a deposit generated by chemical vapor deposition of the reaction gas is applied to a sample surface by activating the reaction gas, a TEOS-based gas and a halogen-based gas are used as the reaction gas. By introducing a mixed gas with the above into the reaction vessel, halogen atoms are taken in and the deposit having a low dielectric constant is deposited on the sample surface. The halogen-based gas is a halogen-based gas having a saturated carbon skeleton, and includes CF 4 , CHF 3 , and C 4 .
2 F 6, CCl 4, CCl 2 F 2, applied to any one of the gas of C 3 F 8. Further, the halogen-based gas includes F 2 ,
Cl 2 , NF 3 , SF 6 , SiF 4 , SiCl 4 , ClF 3 ,
Any one gas of BCl 3 , HCl, HBr, and HF is applied.

【0013】尚、前記飽和炭素骨格を有するハロゲン系
ガスとして、 を適用し、また、前記ハロゲン系
ガスとして、F、Cl、NF、SF、Si
、SiCl、ClF、BCl、HCl、HB
r、HFのいずれか一種類のガスを適用することとす
る。
[0013] As the halogen-based gas having a saturated carbon backbone, to apply the C 2 F 6, also, as the halogen-containing gas, F 2, Cl 2, NF 3, SF 6, Si
F 4 , SiCl 4 , ClF 3 , BCl 3 , HCl, HB
Any one of r and HF is applied.

【0014】[0014]

【作用】このように、単一周波数の高周波電力により反
応容器内にプラズマを発生させるPECVD方法におい
て、前記TEOS系ガスと飽和炭素骨格を有するハロゲ
ン系ガスとの混合ガスを反応ガスに適用して、凹凸状の
下地材料の表面上に薄膜を形成すると、薄膜の側壁が順
テーパ状に形成されるのでボイドが発生しない。更に高
密度配線等を有する半導体装置の製造に適用する場合に
は、薄膜全体が凹凸状の下地材料の凹部に十分に埋込ま
れた状態となるので、ボイドが発生しない。又、上記薄
膜の側壁の緻密性が良好となることから、成膜制御性に
優れた方法を提供することができる。更に、薄膜中にフ
ッ素が取り込まれて誘電率の低い薄膜が形成されるの
で、トランジスタ等の電気的特性の向上を図ることが可
能となる。そして、O3 −TEOS系ガスを用いた常圧
CVD法による薄膜と比較しても、成膜形状及び埋込特
性に関して同等若しくはそれ異常の能力が発揮されると
共に、吸湿性の点で遥かに優れた(即ち、吸湿性が極め
て低い)薄膜を形成することができる。
As described above, in the PECVD method in which plasma is generated in a reaction vessel by high frequency power of a single frequency, a mixed gas of the TEOS-based gas and a halogen-based gas having a saturated carbon skeleton is applied to the reaction gas. When a thin film is formed on the surface of an uneven base material, voids do not occur because the side walls of the thin film are formed in a forward tapered shape. Furthermore, when the present invention is applied to the manufacture of a semiconductor device having high-density wiring or the like, voids do not occur because the entire thin film is sufficiently buried in the concave portions of the uneven base material. Further, since the denseness of the side wall of the thin film is improved, it is possible to provide a method excellent in film formation controllability. Further, since fluorine is taken into the thin film to form a thin film having a low dielectric constant, it is possible to improve the electrical characteristics of the transistor and the like. Compared with a thin film formed by an atmospheric pressure CVD method using an O 3 -TEOS-based gas, the same or abnormal ability is obtained with respect to the film forming shape and the embedding property, and the moisture absorbing property is much higher. An excellent (that is, extremely low hygroscopic) thin film can be formed.

【0015】[0015]

【実施例】以下、本発明の一実施例を図面と共に説明す
る。まず、図1に基づいて、この実施例に適用したPE
CVD装置の概略構成を説明すると、外気から密封され
た反応室1を実現するための絶縁性の反応容器2内に対
向電極3,4が収容され、一方の電極4はアース電位に
保持されると共に、その対向面に薄膜形成用の半導体基
板5が取り付けられ、他方の電極3にはプラズマ発生用
の高周波発振源8から出力された高周波電力がインピー
ダンスマッチング回路9を介して印加されようになって
いる。又、電極3の上側から反応室1へ配管6を介して
反応ガスが導入されると共に、反応ガスの不要分を反応
容器2の一側から排気する構造となっている。又、電極
4側には温度制御用のヒーター7が設けられている。
尚、上記高周波電力の周波数は例えば13.56MHz
に設定されている。
An embodiment of the present invention will be described below with reference to the drawings. First, based on FIG. 1, the PE applied to this embodiment will be described.
The general configuration of the CVD apparatus will be described. Counter electrodes 3 and 4 are accommodated in an insulated reaction vessel 2 for realizing a reaction chamber 1 sealed from the outside air, and one electrode 4 is maintained at a ground potential. At the same time, a semiconductor substrate 5 for forming a thin film is attached to the opposite surface, and high-frequency power output from a high-frequency oscillation source 8 for generating plasma is applied to the other electrode 3 via an impedance matching circuit 9. ing. Further, a reaction gas is introduced from above the electrode 3 into the reaction chamber 1 via the pipe 6, and an unnecessary portion of the reaction gas is exhausted from one side of the reaction vessel 2. A heater 7 for controlling temperature is provided on the electrode 4 side.
The frequency of the high frequency power is 13.56 MHz, for example.
Is set to

【0016】かかる構成のPECVD装置において、上
記の反応ガスとして、飽和炭素骨格を有するハロゲン系
ガスとTEOS系ガスとの混合ガスを反応室1内に導入
し、高周波発振源8からの高周波電力によって対向電極
3,4間に発生するプラズマ放電エネルギーで混合ガス
を活性化させることにより、半導体基板5の表面にSi
2 薄膜を生成させる。尚、記飽和炭素骨格を有するハ
ロゲン系ガスとしては、例えば、CF4 、CHF3 、C
2 6 、CCl4 、CCl2 2 、C3 8 等のいずれ
か一種類のガスを適用する。
In the PECVD apparatus having such a configuration, a mixed gas of a halogen-based gas having a saturated carbon skeleton and a TEOS-based gas is introduced into the reaction chamber 1 as the above-mentioned reaction gas, and the reaction gas is supplied by high-frequency power from a high-frequency oscillation source 8. By activating the mixed gas with the plasma discharge energy generated between the counter electrodes 3 and 4, Si
An O 2 thin film is generated. The halogen-based gas having a saturated carbon skeleton includes, for example, CF 4 , CHF 3 , C
2 F 6, CCl 4, CCl 2 F 2, applied to any one kind of gas such as C 3 F 8.

【0017】図2(a)〜(f)は、半導体基板表面の
SiO2 酸化膜上及びその表面に形成されたAl配線上
に、本発明による薄膜形成方法によって、更に絶縁被覆
のためのSiO2 薄膜を形成した場合の縦断面形状を示
す。尚、同図は、縦断面形状の顕微鏡写真の輪郭部分を
トレースして示す断面図であり、縦横の長さは同図中の
単位スケール(0.5μm)にて示す通りである。
FIGS. 2 (a) to 2 (f) show the SiO 2 oxide film on the semiconductor substrate surface and the Al wiring formed on the surface by the thin film forming method according to the present invention and the SiO 2 oxide film for insulating coating. 2 shows a longitudinal sectional shape when two thin films are formed. The figure is a cross-sectional view showing the outline of the micrograph of the vertical cross-sectional shape by tracing, and the vertical and horizontal lengths are as indicated by the unit scale (0.5 μm) in the figure.

【0018】同図(a)〜(d)のように、夫々のAl
配線の幅及び相対間隔が比較的大きな場合には、SiO
2 薄膜の側壁が順テーパ状に形成されるので、ボイドの
発生が解消される。
As shown in FIGS.
If the width and relative spacing of the wiring are relatively large, SiO
(2) Since the side wall of the thin film is formed in a forward tapered shape, generation of voids is eliminated.

【0019】一方、同図(e)のように、夫々のAl配
線の幅及び相対間隔がサブミクロン範囲の場合にあって
も、SiO2 薄膜の側壁形状が平坦となるので、ボイド
の発生が大幅に低減化される。又、同図(f)のよう
に、サブミクロン範囲において夫々のAl配線の幅及び
相対間隔が更に小さくなると、Al配線間の凹部にもS
iO2 薄膜が埋まり、ボイド発生の問題は完全に解消さ
れる。即ち、埋込特性の優れた薄膜が形成されるという
効果が得られる。又、同図(e)(f)に示すこれらの
場合には、かかる薄膜の側壁部分は緻密な組成構造とな
るので、品質の向上が実現される。
On the other hand, as shown in FIG. 1E, even when the width and relative interval of each Al wiring are in the submicron range, the sidewall shape of the SiO 2 thin film becomes flat, so that voids are generated. It is greatly reduced. Further, as shown in FIG. 3F, when the width and the relative spacing of each Al wiring are further reduced in the submicron range, the recesses between the Al wirings also have S
The iO 2 thin film is buried, and the problem of void generation is completely eliminated. That is, the effect of forming a thin film having excellent embedding characteristics can be obtained. Further, in these cases shown in FIGS. 7E and 7F, since the side wall portion of the thin film has a dense composition structure, the quality is improved.

【0020】因みに、この様にボイドが低減化され且つ
SiO2 薄膜の側壁部分がテーパ状に形成されるのは、
TEOS系ガスに基づいてAl配線及びSiO2 酸化膜
の上面に堆積物が沈積されるのと同時に、飽和炭素骨格
を有するハロゲン系ガスによってその堆積物(SiO2
薄膜)が等方性エッチングされることによるものと推察
される。又、かかるSiO2 薄膜はフッ素が取り込まれ
るので、その誘電率が低くなり、Al配線がMOSFE
Tのゲート電極との間を接続するためのゲート間配線と
して適用される場合等においては、電気的に良好なMO
SFETを実現することが可能となる。更に、従来、良
好な薄膜形成を実現することができるとされているO3
−TEOS系ガスを用いた常圧CVD法による薄膜と比
較しても、成膜形状及び埋込特性に関して同等若しくは
それ以上の能力が発揮されると共に、、吸湿性が極めて
低い薄膜を形成することができる。
Incidentally, the reason why the voids are reduced and the side wall portion of the SiO 2 thin film is formed in a tapered shape is as follows.
At the same time as deposits are deposited on the upper surface of the Al wiring and the SiO 2 oxide film based on the TEOS-based gas, the deposits (SiO 2
It is presumed that the thin film is isotropically etched. Further, since the SiO 2 thin film incorporates fluorine, its dielectric constant is lowered, and the Al wiring is made of MOSFE.
In the case where it is applied as an inter-gate wiring for connecting between the gate electrode of T and the like, an electrically good MO
An SFET can be realized. Furthermore, O 3, which is conventionally considered to be capable of realizing good thin film formation,
-Forming a thin film that exhibits the same or better performance with respect to the film forming shape and embedding characteristics and has extremely low hygroscopicity even when compared with a thin film formed by a normal pressure CVD method using a TEOS-based gas. Can be.

【0021】尚、かかる実施例では、反応ガスとして、
飽和炭素骨格を有するハロゲン系ガスとTEOS系ガス
との混合ガスを適用する場合を説明したが、他のハロゲ
ン系ガスとTEOS系ガスとの混合ガスを適用しても同
様の効果が得られる。この場合、ハロゲン系ガスとして
は、例えば、F2 、Cl2 、NF3 、SF6 、Si
4 、SiCl4 、ClF3 、BCl3 、HCl、HB
r、HF等のいずれか一種類のガスを適用する。
In this embodiment, as the reaction gas,
Although the case where a mixed gas of a halogen-based gas having a saturated carbon skeleton and a TEOS-based gas is applied has been described, similar effects can be obtained by using a mixed gas of another halogen-based gas and a TEOS-based gas. In this case, as the halogen-based gas, for example, F 2 , Cl 2 , NF 3 , SF 6 , Si
F 4 , SiCl 4 , ClF 3 , BCl 3 , HCl, HB
Any one kind of gas such as r and HF is applied.

【0022】更に、本発明をECRプラズマCVD装置
に適用した場合にも同様に、優れた成膜形状と優れた埋
込特性のSiO2 薄膜を生成することができる。この場
合には、例えば、図3に概略的に示すECRプラズマC
VD装置のプラズマ発生室に導波管を介して2.45G
Hzのマイクロ波を導波すると共に、プラズマ発生用ガ
スとして窒素(N2 )等を導入し、更に、反応ガスとし
て前述した混合ガス(即ち、飽和炭素骨格を有するハロ
ゲン系ガスとTEOS系ガスとの混合ガス、又は、ハロ
ゲン系ガスとTEOS系ガスとの混合ガスのいずれか一
方の混合ガス)を反応室内に導入する。
Further, similarly, when the present invention is applied to an ECR plasma CVD apparatus, a SiO 2 thin film having an excellent film formation shape and excellent burying characteristics can be produced. In this case, for example, the ECR plasma C schematically shown in FIG.
2.45G via the waveguide to the plasma generation chamber of the VD device
Hz microwaves are introduced, nitrogen (N 2 ) or the like is introduced as a plasma generation gas, and the above-mentioned mixed gas (that is, a halogen-based gas having a saturated carbon skeleton and a TEOS-based gas is used as a reaction gas). Or a mixed gas of a halogen-based gas and a TEOS-based gas) is introduced into the reaction chamber.

【0023】[0023]

【発明の効果】以上説明したように本発明によれば、単
一周波数の高周波電力により反応容器内にプラズマを発
生させ、この反応容器内に導入した反応ガスをプラズマ
放電エネルギーを用いて活性化させることにより、反応
ガスの化学的気相成長によって生成される沈積物を試料
面へ被着させる半導体装置の薄膜形成方法において、上
記反応ガスとして、飽和炭素骨格を有するハロゲン系ガ
スとTEOS系ガスとの混合ガス、又はハロゲン系ガス
とTEOS系ガスとの混合ガスを適用することとしたの
で、凹凸状の下地材料の表面上に薄膜を形成しても、薄
膜の側壁が順テーパ状に形成されてボイドが発生しな
い。そして、例えば配線密度や素子間密度の極めて高い
半導体集積回路装置等の製造に適用される場合には、配
線間や素子間の凹部い薄膜が十分に埋込まれた状態とな
るので、ボイドが発生せず優れた埋込特性が得られる。
又、上記薄膜の側壁の緻密性が良好となることから、膜
質制御性に優れた方法を提供することができる。更に、
薄膜中にフッ素が取り込まれて誘電率の低い薄膜を形成
することができると共に、吸湿性の極めて低い薄膜を形
成することができる等の成膜膜質制御が容易となるの
で、トランジスタ等の電気的特性の向上を図ることが可
能となる等の優れた効果が得られる。
As described above, according to the present invention, plasma is generated in a reaction vessel by high frequency power of a single frequency, and a reaction gas introduced into the reaction vessel is activated using plasma discharge energy. In the method of forming a thin film for a semiconductor device, wherein a deposit generated by chemical vapor deposition of a reactive gas is applied to a sample surface, the reactive gas includes a halogen-based gas having a saturated carbon skeleton and a TEOS-based gas. Or a mixed gas of a halogen-based gas and a TEOS-based gas, so that even if a thin film is formed on the surface of an uneven base material, the side wall of the thin film is formed in a forward tapered shape. No voids occur. For example, when the present invention is applied to the manufacture of a semiconductor integrated circuit device having an extremely high wiring density or inter-element density, a thin film having a recess between the wirings or between the elements is sufficiently buried, so that voids are formed. Excellent embedding characteristics can be obtained without generation.
Further, since the denseness of the side wall of the thin film is improved, it is possible to provide a method excellent in film quality controllability. Furthermore,
Fluorine is taken into the thin film to form a thin film having a low dielectric constant, and it is easy to control the quality of the formed film, for example, to form a thin film having extremely low hygroscopicity. Excellent effects such as improvement of characteristics can be obtained.

【0024】このように、成膜形状及び埋込特性に優れ
た薄膜を成形することができることから、更なる高密度
・高集積半導体装置の実現に対応し得る半導体装置の薄
膜形成方法を提供することができる。
As described above, since a thin film having an excellent film-forming shape and an excellent embedding property can be formed, a method for forming a thin film of a semiconductor device which can cope with the realization of a further high-density and highly integrated semiconductor device is provided. be able to.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による半導体装置の薄膜形成方法の一実
施例を説明するためのPECVD装置の概略構成を示す
説明図である。
FIG. 1 is an explanatory view showing a schematic configuration of a PECVD apparatus for explaining one embodiment of a method for forming a thin film of a semiconductor device according to the present invention.

【図2】図1に示すPECVD装置によって生成された
SiO2 薄膜の形状を示す縦断面図である。
FIG. 2 is a longitudinal sectional view showing a shape of a SiO 2 thin film generated by the PECVD apparatus shown in FIG.

【図3】ECRプラズマCVD装置を適用した場合の本
発明の一実施例を説明するための説明図である。
FIG. 3 is an explanatory diagram for explaining an embodiment of the present invention when an ECR plasma CVD apparatus is applied.

【図4】従来のSiN系ガスを用いたPECVD法によ
って生成されたSiO2 薄膜の形状を示す縦断面図であ
る。
FIG. 4 is a longitudinal sectional view showing a shape of a SiO 2 thin film generated by a conventional PECVD method using a SiN-based gas.

【図5】従来のTOES系ガスを用いたPECVD法に
よって生成されたSiO2 薄膜の形状を示す縦断面図で
ある。
FIG. 5 is a longitudinal sectional view showing a shape of a SiO 2 thin film produced by a conventional PECVD method using a TOES-based gas.

【符号の説明】[Explanation of symbols]

1…反応室、2…反応容器、3,4…対向電極、5…半
導体基板、6…配管、7…ヒーター、8…高周波電源、
9…インピーダンスマッチング回路。
DESCRIPTION OF SYMBOLS 1 ... Reaction chamber, 2 ... Reaction container, 3, 4 ... Counter electrode, 5 ... Semiconductor substrate, 6 ... Piping, 7 ... Heater, 8 ... High frequency power supply,
9 ... Impedance matching circuit.

フロントページの続き (72)発明者 水野 晋介 千葉県成田市新泉14−3野毛平工業団地 内 アプライド マテリアルズ ジャパ ン 株式会社内 (72)発明者 六平 克之 千葉県成田市新泉14−3野毛平工業団地 内 アプライド マテリアルズ ジャパ ン 株式会社内Continuing on the front page (72) Inventor Shinsuke Mizuno 14-3 Shinsen, Narumi, Narita-shi, Chiba Applied Materials Japan Co., Ltd. (72) Inventor Katsuyuki Rokuhei 14-3 Shinsen, Narumi-shi, Narita-shi, Chiba Applied Materials Japan Co., Ltd.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 単一周波数の高周波電力により反応容器
内にプラズマを発生させ、前記反応容器内に導入した反
応ガスをプラズマ放電エネルギーを用いて活性化させる
ことにより、前記反応ガスの化学的気相成長によって生
成される沈積物を試料面へ被着させる半導体装置の薄膜
形成方法において、前記反応ガスとして、TEOS系ガ
スとフッ素系ガスとの混合ガスを前記反応容器内に導入
することにより、フッ素原子を取り込んで低誘電率とな
る前記沈積物を前記試料面へ被着させ、SiOF膜を成
膜することを特徴とする半導体装置の薄膜形成方法.
A plasma is generated in a reaction vessel by high frequency power of a single frequency, and a reaction gas introduced into the reaction vessel is activated by using plasma discharge energy, whereby a chemical gas of the reaction gas is generated. In the method for forming a thin film of a semiconductor device, wherein a deposit generated by phase growth is deposited on a sample surface, by introducing a mixed gas of a TEOS-based gas and a fluorine-based gas into the reaction vessel as the reaction gas, A method of forming a thin film for a semiconductor device, comprising: depositing the deposit having a low dielectric constant by incorporating fluorine atoms onto the sample surface, and forming a SiOF film.
【請求項2】 前記フッ素系ガスは、CF4、CHF3
CCl22、C38のいずれかであることを特徴とする
請求項1に記載の半導体装置の薄膜形成方法。
2. The fluorinated gas is CF 4 , CHF 3 ,
2. The method according to claim 1, wherein the method is one of CCl 2 F 2 and C 3 F 8 .
【請求項3】 前記フッ素系ガスは、F2、NF3、SF
6、SiF4、ClF3、HFのいずれかであることを特
徴とする請求項1に記載の半導体装置の薄膜形成方法。
3. The fluorine-based gas includes F 2 , NF 3 and SF.
6. The method for forming a thin film of a semiconductor device according to claim 1, wherein the method is any one of SiF 4 , ClF 3 , and HF.
JP05145070A 1993-06-16 1993-06-16 Semiconductor device thin film forming method Expired - Fee Related JP3090561B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP05145070A JP3090561B2 (en) 1993-06-16 1993-06-16 Semiconductor device thin film forming method
US08/259,584 US5571571A (en) 1993-06-16 1994-06-14 Method of forming a thin film for a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05145070A JP3090561B2 (en) 1993-06-16 1993-06-16 Semiconductor device thin film forming method

Publications (2)

Publication Number Publication Date
JPH0722316A JPH0722316A (en) 1995-01-24
JP3090561B2 true JP3090561B2 (en) 2000-09-25

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Country Link
JP (1) JP3090561B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0724286A1 (en) * 1995-01-25 1996-07-31 Applied Materials, Inc. A method of forming a thin film of silicon oxide for a semiconductor device
JPH0964176A (en) * 1995-08-21 1997-03-07 Oki Electric Ind Co Ltd Fabrication method of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268429A (en) * 1990-03-19 1991-11-29 Hitachi Ltd Method and equipment for formation of wiring insulation film of semiconductor device
JPH04341568A (en) * 1991-05-16 1992-11-27 Toshiba Corp Method for forming thin film and device therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268429A (en) * 1990-03-19 1991-11-29 Hitachi Ltd Method and equipment for formation of wiring insulation film of semiconductor device
JPH04341568A (en) * 1991-05-16 1992-11-27 Toshiba Corp Method for forming thin film and device therefor

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