JP3074958B2 - Serial multiplier with addition function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit for multiplying or adding / subtracting input parallel data in a digital signal processing circuit.

[0002]

2. Description of the Related Art In recent years, with the integration of digital signal processing circuits, the processing capability and circuit configuration of an arithmetic circuit that performs various processes on input data have become major factors in determining the overall circuit scale.

Hereinafter, the configuration of a conventional arithmetic circuit will be described with reference to the drawings. First, FIG. 3 shows a configuration of a conventional serial multiplication circuit. In FIG. 3, reference numeral 4 denotes a 1-bit multiplier for performing parallel 1-bit multiplication of input parallel data 1 (D3, D2, D1, D0) and 1-bit coefficient data 2 (K3, K2, K1, K0); Reference numeral 6 denotes an output register for latching the output of the full adder 5 with a clock signal 9 by adding a signal obtained by feeding back the output of the entire multiplier one clock before and the output of the 1-bit multiplier 4.
Reference numeral 7 denotes a clear circuit for resetting the feedback signal to all zeros by a clear signal 8.

The operation of the conventional serial multiplier configured as described above will be described below. FIG. 4 shows the timing of each signal. The input parallel data 1 holds the same value for four clocks of the clock signal 9, and the 1-bit coefficient data 2 has the LSB first and the 1
Data is serially input for each clock. First, in the first first clock, the clear signal 8 goes low in synchronization with the clock signal 9, whereby the feedback signal 10
Is reset to all zeros. At the same time, data D3 (1) to
The result of parallel 1-bit multiplication of D0 (1) and K0 (1) which is the LSB of the coefficient data input from the 1-bit coefficient data 2 is output from the 1-bit multiplier 4.

Since the output of the clear circuit 7 is zero, the output of the 1-bit multiplier 4 becomes the output of the full adder 5 as it is. At this time, the carry input of the least significant bit of the full adder 5 is set to "0" as shown in FIG. The carry output 1 of the full adder 5
The upper three bits of the bit and the sum output are latched by the output register 6, and the parallel data output 3 is fed back as it is as the feedback signal 10. Since the clear signal 8 becomes high level at the second clock, the feedback signal 10 is input to the full adder 5 in the form of shifting the output of the full adder 5 one clock before in the LSB direction by one bit. The 1-bit multiplier 4 multiplies the input data D3 (1) to D0 (1) by one bit in parallel with the coefficient data K1 (1), and in a full adder 5, the feedback signal 10 and the output of the 1-bit multiplier 4 And the result of the addition is latched again in the output register 6. Further, the same operation is repeated while changing the value of the 1-bit coefficient data 2 for each clock, and the output parallel data 3 at the fifth clock is D3 (1) to D0 (1) and K3 (1) to K0 (1). The result is the multiplication result (upper 4 bits).

Next, the configurations of the conventional adder and subtractor are shown in FIGS. 5 (a) and 5 (b). The full adder 5 and output register 6 in FIG. 5 are the same as those in FIG. An inverter 11 inverts each bit of the inputs B3 to B0. In the adder shown in FIG. 5A, the carry input of the least significant bit of the full adder 5 is set to "0", and the inputs A3 to A0 and the inputs B3
ＢB0 are input to the full adder 5 to add both. Then, the addition result is latched by the output register 6 in synchronization with the clock signal 9. In the case of the subtractor shown in FIG. 5B, the carry input of the least significant bit of the full adder 5 is set to "1", and the signals obtained by inverting the inputs B3 to B0 by the inverter 11 and the inputs A3 to A0 In the full adder 5. Thus, the inputs B3 to B0 are subtracted from the inputs A3 to A0. Then, the subtraction result is latched by the output register 6 in synchronization with the clock signal 9.

[0007]

However, in the above configuration, different operation circuits are required depending on the type of operation. Further, when the operation results are output to the same data bus, transfer gates and selectors are required at the output portions of the individual operation circuits in order to prevent the output signals of the individual operation circuits from colliding with each other. For this reason, especially when the number of bits of the input parallel data is large, there is a problem that the circuit scale becomes very large.

The present invention has been made to solve the above-mentioned conventional problems, and has been made for the purpose of reducing the circuit scale by performing various arithmetic processes with one arithmetic circuit.

[0009]

In order to solve the above problems, a serial multiplier with an addition function according to the present invention comprises: a 1-bit multiplier for performing parallel 1-bit multiplication of input parallel data and 1-bit coefficient data; A clear circuit for resetting a parallel feedback signal from output parallel data of the entire multiplier to zero, a full adder for adding the output of the 1-bit multiplier and the output of the clear circuit, and an output register for delaying the output of the full adder by one clock; A selector for switching the output of the register by one bit for feedback or for feedback without shifting. When multiplication, 1-bit coefficient data is serially input for each clock in LSB first, and the register is Shifts the output parallel data of the entire serial multiplier, which is the output of, by one bit to the MSB side In this case, the input parallel data is serially multiplied by the 1-bit coefficient data. At the time of addition, the 1-bit coefficient data is fixed at "1" and the output parallel data of the entire serial multiplier is not shifted. , The addition operation of the value stored in the output register and the input parallel data is performed.

[0010]

According to the present invention, a full adder and an output register, which are separately required for each arithmetic circuit in the conventional arithmetic circuit, can be shared by the above configuration. Furthermore, since there is only one output as an arithmetic circuit, a transfer gate and a selector are not required as in the conventional case when an arithmetic result is output to a data bus. Therefore, particularly when the number of bits of the input parallel data is large, the circuit scale can be significantly reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A serial multiplier with an addition function according to the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a serial multiplier with an addition function according to one embodiment of the present invention. In FIG. 1, a 1-bit multiplier 4, a full adder 5,
The output register 6 and the clear circuit 7 are the same as those shown in FIG. Reference numeral 12 denotes an EX-OR gate for inverting or inverting the input parallel data 1 to be input to the 1-bit multiplier 4, reference numeral 13 denotes a first switch for switching the EX-OR gate between inversion and inversion, and 14 Is a second switch for switching the input of the 1-bit multiplier 4 to 1-bit coefficient data 2 or “1” or “0”,
Reference numeral 5 denotes a third switch for switching the carry input of the least significant bit of the full adder 5 to "0" or "1", and reference numeral 16 denotes whether the output of the output register 6 is fed back without shifting or shifted by 1 bit. Is a fourth switch for changing over. Further, reference numeral 17 denotes an OR gate for setting a specific bit in the feedback signal cleared by the clear circuit 7, and is controlled by a set signal 18. Then, output parallel data 3 (S3 to S0) which is the output of the entire serial multiplier with the addition function
Is the output signal of the fourth switch 16.

The operation of the serial multiplier with the addition function of the present invention configured as described above will be described below. First, when serial multiplication is first performed, the first switch 13 is fixed to “0”, and the second switch 14 is set to “1”.
The third switch 15 is fixed to “0”, and the fourth switch 16 is shifted to the side that shifts one bit. By setting as described above, the serial multiplier with the addition function according to the present invention shown in FIG.
Is exactly the same as the conventional serial multiplication circuit shown in FIG. Therefore, the operation timing is exactly the same as the timing chart shown in FIG. Also, in FIG.
In order to clear the feedback signal 10 to all zeros before starting the operation as in the conventional example, the set signal 18 may be fixed to zero. However, the serial multiplier with the addition function according to the present invention can add a certain value in advance to a value obtained as a result of the multiplication by setting a specific bit after all-clearing the feedback signal 10. is there. In FIG. 1, a signal obtained by inverting the clear signal 8 is added as a set signal 18 so that the initial value is “1”.
000B ". In the multiplication result finally obtained by this processing, bits after the decimal point can be rounded by rounding.

Next, the case of performing the addition operation will be described with reference to the timing chart shown in FIG. First, the first switch 13 is fixed to “0”, the second switch 14 is fixed to “1”, and the third switch 15 is set to “0”.
Fixed to. Then, the fourth switch 16 is moved to the non-shift side. Thereby, the input parallel data 1 “D
"(1)" is input to the full adder 5 as it is. Then, at the first first clock, the clear signal 8 and the set signal 18 are set to low level, the feedback signal 10 is reset to all zeros, and input to the full adder 5. As a result, the output of the full adder 5 becomes the input parallel data 1 “D
(1) ", and the input parallel data 1 to be added at the next clock is stored in the output register 6. By setting the clear signal 8 to the high level at the second clock, the data stored in the output register 6 is fed back as it is, and is added to the data "D (2)" newly added from the input parallel data 1. , The addition result "D
(1) + D (2) "is latched and output by the output register 6 at the third clock.

When the subtraction is performed, first, the input parallel data 1 "D (3)" is processed in the same procedure as in the case of the addition.
Is stored in the output register 6. At the second clock, the clear signal 8 is set to the high level, and at the same time, the first switch 13 is set to “1” to input the parallel data 1 “D (4)”
Is bit-inverted. And the second switch 14
Fixed to "1" for through, and the third switch 1
5 as “1”, carry input to full adder 5 “+1”
Add. As a result, the data “D (4)” newly added from the input parallel data 1 is subtracted from the data “D (3)” initially stored in the output register 6, and 3
At the clock, the subtraction result “D (3) −D
(4) "is latched and output.

Further, the second switch 14 is set to "0" to clear the input parallel data 1 to all zeros, the third switch 15 is fixed to "0", the fourth switch 16 is fixed to the non-shift side, and a clear signal is set. By setting 8 to the high level and the set signal 18 to the low level, the data “D (3) -D (4)” stored in the output register 6 can be held.

When the above addition / subtraction operation is performed continuously after the end of serial multiplication, it is not necessary to store the input parallel data 1 in the output register 6 at the first clock. That is, if the operation of the second clock in the addition or subtraction operation is performed with the fourth switch 16 shifted to the side that shifts one bit, the addition / subtraction operation of the multiplication result and the input parallel data 1 can be performed in one clock. Can be done.

[0017]

As described above, the serial multiplier with the addition function of the present invention comprises a 1-bit multiplier for performing parallel 1-bit multiplication of input parallel data and 1-bit coefficient data;
A clear circuit for resetting a parallel feedback signal from output parallel data of the entire serial multiplier to zero;
A full adder for adding the output of the bit multiplier and the clear circuit, an output register for delaying the output of the full adder by one clock, and switching between feedback of the register output by one bit and feedback without shifting. And a selector, in which, during multiplication, 1-bit coefficient data is serially input for each clock in LSB first, and the output parallel data of the entire serial multiplier, which is the output of the register, is shifted by 1 bit to the MSB side and fed back. Thus, serial multiplication of the input parallel data and the 1-bit coefficient data is performed, the 1-bit coefficient data is fixed to "1" at the time of addition, and the output parallel data of the entire serial multiplier is fed back without being shifted. By
By performing the addition operation of the value stored in the output register and the input parallel data, it is possible to use a full adder and an output register which are separately required for each arithmetic circuit in the conventional arithmetic circuit, and Since there is only one output as an arithmetic circuit, a transfer gate and a selector are not required as in the related art even when an arithmetic result is output to a data bus. Therefore, especially when the number of bits of the input parallel data is large, there is an effect that the circuit scale can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a serial multiplier with an addition function according to an embodiment of the present invention.

FIG. 2 is a diagram showing timing of a serial multiplier with an addition function according to the present invention;

FIG. 3 is a configuration diagram of a conventional serial multiplier.

FIG. 4 is a diagram showing the timing of a conventional serial multiplier.

5A is a configuration diagram of a conventional adder. FIG. 5B is a configuration diagram of a conventional subtractor.

[Explanation of symbols]

 Reference Signs List 4 1-bit multiplier 5 Full adder 6 Output register 7 Clear circuit 11 Inverter 12 EX-OR gate 13 First switch 14 Second switch 15 Third switch 16 Fourth switch 17 OR gate

Claims (4)

(57) [Claims] A 1-bit multiplier for performing parallel 1-bit multiplication of input parallel data and 1-bit coefficient data; a clear circuit for resetting a parallel feedback signal from output parallel data of the entire serial multiplier to zero; A full adder for adding the output of the 1-bit multiplier and the output of the clear circuit, an output register for delaying the output of the full adder by one clock, and determining whether the output of the register is shifted back by one bit or fed back without being shifted. And a selector for switching, and inputting 1-bit coefficient data serially for each clock in LSB first at the time of multiplication, and shifting the output parallel data of the entire serial multiplier, which is the output of the register, by 1 bit to the MSB side and feeding back. In this way, serial multiplication of input parallel data and 1-bit coefficient data is performed. At the time of addition, the 1-bit coefficient data is fixed to "1" and the output parallel data of the entire serial multiplier is fed back without being shifted, so that the value stored in the output register and the input parallel data are compared. Serial multiplier with addition function characterized by performing addition operation. 2. Using an EX-OR gate or the like, switching between inputting the input parallel data as it is to the 1-bit multiplier or inputting after inverting all bits, and carrying the least significant bit of the full adder Input "0"
2. A serial multiplier with an addition function according to claim 1, wherein switching between "1" and "1" enables subtraction operation in addition to serial multiplication and addition operation. 3. The clearing circuit has a function of setting a feedback signal to all zeros, in addition to a function of setting the feedback signal to a specific value, and can perform an addition operation of the input parallel data and a specific value. 2. A serial multiplier with an addition function according to claim 1, wherein: 4. The value stored in the output register is held by fixing the 1-bit coefficient data to “0” and feeding back the output parallel data of the entire serial multiplier without shifting it. 2. A serial multiplier with an addition function according to claim 1, wherein: