JP3047839B2 - Single-chip microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
More particularly, the present invention relates to a single-chip microcomputer having a function of detecting unauthorized access to a built-in memory or a built-in I / O register.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 3-216746 proposes a memory protection device capable of reliably protecting memory data in a RAM from runaway of a processor or intentional unauthorized access. . That is, the publication discloses a data memory protection device that stores data for a plurality of words in word units, an attribute memory that stores an attribute for each word of the data memory in one or a plurality of word units, Memory attribute generating means for generating an attribute corresponding to a data word to be accessed from the attribute memory in response to data access; access attribute generating means for generating an attribute indicating a type of data access to the data memory; There has been proposed a memory protection device comprising: a determination unit that determines whether to permit execution of data access to the data memory based on a combination of a memory attribute and an access attribute generated by the unit.

[0003] In this memory protection device, information such as whether to permit or prohibit writing of data and whether to permit or prohibit reading of data is stored in the attribute memory as one or more attributes as attributes of each word of the data memory. Store in multiple word units.

Thus, when a data access is made from the processor to the data memory, an attribute corresponding to the data word of the access destination is generated from the attribute memory by the memory attribute generating means, and at the same time, the access attribute generating means generates the attribute. An attribute indicating the type of the data access is generated, and it is determined whether execution of the data access is permitted based on a combination of these attributes.
Therefore, data in which data that prohibits rewriting is stored.
The attribute which inhibits writing corresponding to the data word of the data memory is stored in the attribute memory to protect the remaining data.

[0005]

However, in the above-mentioned prior art, an illegal word length is used to access one of a plurality of built-in I / O registers of a single-chip microcomputer having a variable word length. Cannot be protected against

The reason is that, in the conventional technique, only protection of a memory in which each word has only a uniform function is assumed, and therefore, only a means for determining a memory attribute in units of fixed-length words is provided. This is because protection regarding the effective word length at the time of access is not considered.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above circumstances, and has as its object to provide a plurality of ICs of a single-chip microcomputer having a variable word length.
An object of the present invention is to provide a single-chip microcomputer which realizes protection against an access to an / O register with an illegal word length.

[0008]

In order to achieve the above-mentioned object, a single-chip microcomputer according to the present invention comprises:
A word length management memory for storing word length information for each access unit of the built-in memory and the built-in I / O register;
CPU for built-in memory or built-in I / O register
Access unit information output means for outputting word length information and read / write attributes corresponding to an access unit from a word length management memory and an attribute management memory in response to an access from the CPU, a built-in memory and a built-in I / O register from the CPU CPU access information generating means for generating an effective word width and a read / write attribute of an access cycle to the word, word length information and read / write attribute output by the access unit information output means, and CPU access information generating means. An unauthorized access detector for determining a combination of the effective word width and the read / write information, and an interrupt generating means for generating an interrupt for the CPU according to the determination result output from the unauthorized access detector.

The outline of the single-chip microcomputer according to the present invention will be described below. In the present invention, the CP
When U accesses an internal I / O register having an arbitrary word length, if the word length of the internal I / O register to be accessed differs from the effective word width of an access cycle activated by the CPU, an access unit is determined. Output data of the word length management memory output by the information output means,
Based on a combination of information output by the CPU access information generating means, the detecting means detects an unauthorized access and
An interrupt is issued to U.

Therefore, according to the present invention, the CPU can prevent runaway of the system due to the unauthorized access and detect a defect in the program of the CPU by interrupt processing upon detection of the unauthorized access. .

[0011]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. Referring to FIG. 1, an embodiment of the present invention comprises:
An I / O register group 5 composed of I / O registers having an irregular word length and a data memory 8 are provided to the CPU 1 via an address bus 2, a data bus 3, and a control bus 4. Connected. Further, a word length management memory 6 and an attribute management memory 7 are connected to the address bus 2 and the data bus 3, and a read / write attribute signal 10 from the word length management memory 6 and an attribute The access unit signal 11 from the management memory 7 is input to the unauthorized access detector 9.

The word length management memory 6 has an address
Access unit information for each address allocated to the data memory 8 and the I / O register group 5 on the bus 2 is stored in advance in such a manner as to correspond to the addresses on a one-to-one basis.

On the other hand, the attribute management memory 7 has a data memory 8 and an I / O register group 5 on the address bus 2.
The information corresponding to the read / write attribute for each address assigned to each address is stored in advance in such a manner as to correspond one-to-one to the address.

A bus access status signal 13 from the CPU 1 is input to the unauthorized access detector 9, and an interrupt request signal 12 output from the unauthorized access detector 9 is
It is input to U1.

Next, the operation of the embodiment of the present invention will be described with reference to FIG.

When the CPU 1 accesses an I / O register constituting the I / O register group 5, the attribute management memory 7 is specified by the address of the I / O register on the address bus 2. Output stored data (read /
Write attribute signal) 10. These stored data are the read / write attributes of the I / O registers constituting the I / O register group 5.

On the other hand, the word length management memory 6 outputs the storage data specified by the address of the I / O register on the address bus 2 to an output (access unit signal) 11. These stored data are access unit information of the I / O register.

When the combination of the read / write attribute signal 10 and the access unit signal 11 does not match the state of the bus access state signal 13 and is in an unauthorized access state, the unauthorized access detector 9 Signal 1
2 is output to the CPU 1. Upon receiving the interrupt request signal 12, the CPU 1 suspends the execution of a series of programs, and the interrupt processing is started.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 2 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 2, in one embodiment of the present invention, the address bus 2
And a plurality of 8-bit or 16-bit I / Os via a 16-bit data bus 15 and a control bus 4.
An I / O register group 5 composed of registers and a data memory 8 having a 16-bit input / output width are connected.

Further, the address bus 2 and the 16-bit
The data bus 15 is connected to a word length management ROM (read only memory) 16 having a 2-bit output width and an attribute management ROM 17 having a 2-bit output width. Input to the container 9.

The word length management ROM 16 has a data memory 8 and an I / O register group 5 on an address bus 2.
The 8-bit access availability information and the 16-bit access availability information for each address allocated to each address are stored in advance in such a manner that each bit has a one-to-one correspondence with the address.

On the other hand, the attribute management ROM 17 has a read / write permission attribute and a write permission attribute for each address allocated to the data memory 8 and the I / O register group 5 on the address bus 2. The information to be stored is stored in advance in the form of one bit at a time corresponding to the address.

The control bus 4 is connected to the unauthorized access detector 9, and an interrupt request signal 12 output from the unauthorized access detector 9 is input to the 16-bit CPU 14.

FIG. 3 shows a connection configuration of the attribute management ROM 17 in one embodiment of the present invention. Referring to FIG. 3, the attribute management ROM 17 includes a control bus 4 in addition to the address bus 2, and a data strobe signal 20 indicating the activation state of the address bus 2 and the 16-bit data bus 15. Are connected to an OE (output enable) terminal, and a read enable / disable attribute signal 21 and a write enable / disable attribute signal 22 are output as an output signal 19 (see FIG. 2).

FIG. 4 shows a connection configuration of the word length management ROM 16 in one embodiment of the present invention. Referring to FIG. 4, in addition to the address bus 2, the data strobe signal 20 is stored in the ROM 16 for word length management.
8 bit access permission / inhibition information signal 23
And the 16-bit access permission / inhibition information signal 24 are output as the output signal 18 (see FIG. 2).

FIG. 5 is a diagram showing an example of a circuit configuration of the unauthorized access detector 9 in one embodiment of the present invention. FIG.
, The unauthorized access detector 9 outputs, from the control bus 4, an access width signal 25 indicating, as 1-bit information, either 8 bits or 16 bits, which is the access word width of the 16-bit CPU 14, A read strobe signal 26 indicating a read state of the data bus 15, a write strobe signal 27 indicating a write state, and a data strobe signal 20 are input.

The read enable / disable attribute signal 21 and the write enable / disable attribute signal 22 output from the attribute management ROM 17
And an 8-bit access permission / inhibition information signal 23 and a 16-bit access permission / inhibition information signal 24 output from the word length management ROM 16, and output an interrupt request signal 12 to the 16-bit CPU 14.

More specifically, referring to FIG. 5, an unauthorized access detector 9 includes an access width signal 25 indicating, as 1-bit information, either 8 bits or 16 bits, which is the access word width of the 16-bit CPU 14. AND gate AND1 that receives an input of an access width signal 25 and an AND gate AND2 that receives an inverted signal of an access width signal 25 and a 16-bit access availability information signal 24, a read strobe signal 26 and a read availability. AND gate AND3 receiving the attribute signal 21 and AND gates AND4, AND1, AND receiving the write strobe signal 27 and the write enable / disable attribute signal 22 as inputs.
NOR gates NOR1 and AND having the output of 2 as input
3. NOR gate NOR having the output of AND4 as input
2, an OR gate OR having inputs of NOR1 and NOR2 as inputs, an output of the OR gate is input to a data input terminal D of a D-type flip-flop 28, and the D-type flip-flop receives a data strobe signal 20 as a clock input; The output terminal Q is connected to the interrupt request signal 12 for the CPU 14.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG. 2, FIG. 3, FIG. 4, and FIG.

When the 16-bit CPU 14 performs a 16-bit write access to the readable and writable 8-bit I / O registers constituting the I / O register group 5, the attribute management ROM 17 Outputs 2-bit storage data specified by the address of the I / O register on the address bus 2 as a read enable / disable attribute signal 21 and a write enable / disable attribute signal 22 in synchronization with the data strobe signal 20. . As these stored data, the read enable / disable attribute and the write enable / disable attribute of the I / O register are stored in advance. In this case, the read enable / disable attribute signal 21 and the write enable / disable attribute signal 22 indicate the read enable / write enable status. (State).

On the other hand, the word length management ROM 16 accesses the 2-bit storage data specified by the address of the I / O register on the address bus 2 in synchronism with the data strobe signal 20 to perform 8-bit access. Availability information signal 2
3 and a 16-bit access availability information signal 24. As these stored data, 8-bit access permission / inhibition information and 16-bit access permission / inhibition information of the I / O register are stored in advance. In this case, an 8-bit access permission / inhibition information signal 23 and a 16-bit access permission signal are stored. The availability information signal 24 indicates a status in which only 8-bit access is possible.

Therefore, the access width signal 25 (indicating an access in units of 16 bits) does not match the state of the 8-bit access permission signal 23, and the unauthorized access detector 9 outputs the data strobe signal In order to output the interrupt request signal 12 in synchronization with the
4 interrupts the execution of a series of programs, and interrupt processing is started. That is, the AND output of the access signal 25 and the 8-bit accessible signal 23 becomes "0", the inverted output of the access signal 25 and the AND output of the 16-bit accessible signal 24 become "0", and the NOR gate N
The output of OR1 becomes "1", is input to the D-type flip-flop 28 via the OR gate, and the interrupt request signal 12 is output in synchronization with the data strobe signal 20.

[0035]

As described above, according to the present invention,
This has the effect of making it possible to detect access to an I / O register with a variable word length built in a single-chip microcomputer with an incorrect word length. For this reason, according to the present invention, there is an advantage that the runaway of the system due to unauthorized access can be prevented with higher accuracy than that of the above-described conventional method, and a defect in the CPU program can be detected.

The reason is that, in the present invention, a word length management memory for storing word length information for each access unit and a word length management memory for storing access unit information for each address are provided. When accessing the / O register, if the word length of the I / O register indicating the word length management memory is different from the effective word width of the access cycle activated by the CPU, an illegal access is detected and an interrupt is issued to the CPU. It depends on what was made to occur.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 3 is a block diagram showing a connection configuration of an attribute management memory (ROM) in one embodiment of the present invention.

FIG. 4 is a block diagram showing a connection configuration of a word length management memory (ROM) in one embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an unauthorized access detector in one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Address bus 3 Data bus 4 Control bus 5 I / O register group 6 Word length management memory 7 Attribute management memory 8 Data memory 9 Unauthorized access detector 10 Output 11 Output 12 Interrupt request signal 13 Access status signal 14 16-bit CPU 15 16-bit data bus 16 Word length management ROM 17 Attribute management ROM 18 Output 19 Output 20 Data strobe signal 21 Read enable / disable attribute signal 22 Write enable / disable attribute signal 23 8-bit access enable / disable signal 24 16 Bit access enable / disable signal 25 Access width signal 26 Read strobe signal 27 Write strobe signal

Claims (5)

(57) [Claims] 1. A single-chip microcomputer having at least a CPU, a data memory, and an I / O register on a single semiconductor pellet, wherein each of the data memory and the I / O register is accessed. A word length management memory that stores word length information for each unit; an attribute management memory that stores read / write attributes of each access unit; and an access from the CPU to the data memory or the I / O register. Responsively, access unit information output means for outputting word length information corresponding to the access unit and read / write attribute from the word length management memory and the attribute management memory; From the valid word of the access cycle to the data memory and the I / O register Width and
CPU access information generating means for generating a read / write attribute; word length information and read / write attribute output by the access unit information output means; an effective word width generated by the CPU access information generating means; Unauthorized access detection means for determining a combination with read / write information; and interrupt generation means for causing the CPU to generate an interrupt in accordance with a determination result output by the unauthorized access detection means. Features a single-chip microcomputer. 2. A word length management memory for storing access unit information for each address of an I / O register group including a plurality of I / O registers to which addresses are assigned,
Further, when the CPU accesses one of the I / O registers of the I / O register group, the word length management memory is accessed and the I / O register output from the word length management memory is accessed.
When the word length information corresponding to the / O register is different from the effective word width which is the access information of the access cycle activated by the CPU, means for detecting an illegal access and generating an interrupt to the CPU is provided. A single-chip microcomputer. 3. An attribute management memory for storing read / write availability information for each address of the I / O register group, wherein the CPU accesses the I / O register when the CPU accesses the I / O register.
The attribute management memory is accessed, and read / write availability information corresponding to the I / O register output from the attribute management memory and corresponding to the I / O register output from the word length management memory. 3. The single-chip microcomputer according to claim 2, wherein an unauthorized access is detected from a combination of word length information to be accessed and access information from the CPU. 4. A word length management memory for storing access unit information for each address of a data memory, further comprising: when the CPU accesses the data memory, the word length management memory is accessed; If the word length information of the data memory output from the management memory is different from the effective word width which is the access information of the access cycle activated by the CPU, it is detected as an illegal access, and an interrupt is issued to the CPU. A single-chip microcomputer comprising means for generating. 5. An attribute management memory for storing read / write enable / disable information for each address of said data memory, wherein said attribute management memory is accessed when said CPU accesses said data memory, Unauthorized access is detected from a combination of read / write permission information output from the management memory, word length information corresponding to the data memory output from the word length management memory, and access information from the CPU. The single-chip microcomputer according to claim 4, wherein