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JP2930186B2 - Semiconductor device mounting method and semiconductor device mounted body - Google Patents

Semiconductor device mounting method and semiconductor device mounted body

Info

Publication number
JP2930186B2
JP2930186B2 JP7367496A JP7367496A JP2930186B2 JP 2930186 B2 JP2930186 B2 JP 2930186B2 JP 7367496 A JP7367496 A JP 7367496A JP 7367496 A JP7367496 A JP 7367496A JP 2930186 B2 JP2930186 B2 JP 2930186B2
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
thermal expansion
resin composition
inorganic filler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7367496A
Other languages
Japanese (ja)
Other versions
JPH09266229A (en
Inventor
芳宏 別所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7367496A priority Critical patent/JP2930186B2/en
Publication of JPH09266229A publication Critical patent/JPH09266229A/en
Application granted granted Critical
Publication of JP2930186B2 publication Critical patent/JP2930186B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、詳しくは半導体装置の実装方法およびその実装体に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for mounting a semiconductor device and a mounted body thereof.

【0002】[0002]

【従来の技術】従来、半導体装置を回路基板上へ実装す
る場合には、半田付けによる方法が一般的である。しか
し、近年、半導体装置のパッケージの小型化と接続端子
数の増加により、接続端子間の間隔が狭くなり、従来の
半田付け技術によって対処することが次第に困難になっ
てきている。
2. Description of the Related Art Conventionally, when a semiconductor device is mounted on a circuit board, a soldering method is generally used. However, in recent years, with the miniaturization of the package of the semiconductor device and the increase in the number of connection terminals, the interval between the connection terminals has been narrowed, and it has become increasingly difficult to cope with the conventional soldering technology.

【0003】そこで、最近では、裸の半導体装置を回路
基板上に直付けすることによって、実装面積の小型化と
効率的使用とを図ろうとする方法が考え出されている。
その一例として次のようなものがある。
[0003] Therefore, recently, a method has been devised in which a bare semiconductor device is directly mounted on a circuit board so as to reduce the mounting area and use it efficiently.
The following is an example.

【0004】その方法は、まず、半導体装置を回路基板
に電気的に接続する際に、半導体装置の端子電極上にあ
らかじめ密着金属や拡散防止金属の蒸着膜と、メッキに
よって形成された半田層とを積層させる。そして、次
に、以上の電極構造を有する半導体装置を回路基板上に
フェースダウンさせ、高温に加熱して半導体装置の端子
電極上の半田を回路基板の接続電極に融着させるという
ものである。
According to the method, first, when a semiconductor device is electrically connected to a circuit board, a deposition film of an adhesion metal or a diffusion preventing metal is previously formed on a terminal electrode of the semiconductor device, and a solder layer formed by plating is used. Are laminated. Then, the semiconductor device having the above-described electrode structure is face-down on a circuit board, heated to a high temperature, and the solder on the terminal electrodes of the semiconductor device is fused to the connection electrodes of the circuit board.

【0005】この方法によれば、接続を一括して行うこ
とができ、さらに、この方法による実装構造は、接続後
の機械的強度が強いという特徴を有する。したがって、
この方法は、有効な方法であるとされている。
[0005] According to this method, the connection can be performed collectively, and the mounting structure by this method has a feature that the mechanical strength after the connection is strong. Therefore,
This method is considered to be an effective method.

【0006】また、米国特許第5121190号明細書
には、半田による接合部の安定性を確保するために、半
導体装置と回路基板との間を樹脂封止した半導体装置の
実装体が開示されている。
Further, US Pat. No. 5,121,190 discloses a semiconductor device package in which a resin is sealed between a semiconductor device and a circuit board in order to ensure the stability of a joint portion formed by soldering. I have.

【0007】以下、従来の半導体装置の実装方法とその
実装体について説明する。図5は、従来技術における半
導体装置の実装体の要部断面図である。図5において、
1は半導体装置、2は半導体装置1の端子電極、4は回
路基板、5は接続電極、13は半田による接合部、14
は封止樹脂である。
Hereinafter, a conventional method for mounting a semiconductor device and its mounting body will be described. FIG. 5 is a cross-sectional view of a main part of a semiconductor device package according to the related art. In FIG.
1 is a semiconductor device, 2 is a terminal electrode of the semiconductor device 1, 4 is a circuit board, 5 is a connection electrode, 13 is a solder joint, 14
Is a sealing resin.

【0008】この従来技術においては、まず、端子電極
2上に半田バンプが形成された半導体装置1を、回路基
板4の接続端子5の所定の位置に、フェースダウンで搭
載する。次に、200〜300℃の高温に加熱して、端
子電極2上の半田バンプを溶融させ接続端子5に融着さ
せる。こうすることにより、半導体装置1と回路基板4
とが半田による接合部13により接続される。その後、
半導体装置1と回路基板4との間隙に液状の封止樹脂1
4を充填し、150℃程度の温度で加熱硬化する。以上
の工程により、半導体装置1を封止樹脂14で封止した
実装体を得ることができる。
In this conventional technique, first, a semiconductor device 1 having a solder bump formed on a terminal electrode 2 is mounted face-down on a predetermined position of a connection terminal 5 of a circuit board 4. Next, the solder bumps on the terminal electrodes 2 are melted by heating to a high temperature of 200 to 300 ° C. and fused to the connection terminals 5. By doing so, the semiconductor device 1 and the circuit board 4
Are connected by a joint 13 made of solder. afterwards,
Liquid sealing resin 1 is provided in the gap between semiconductor device 1 and circuit board 4.
4 and cured by heating at a temperature of about 150 ° C. Through the above steps, a mounted body in which the semiconductor device 1 is sealed with the sealing resin 14 can be obtained.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、以上の
従来の半導体装置の実装体においては、この半導体装置
の実装体を使用する際の環境温度の変化により、半導体
装置1と回路基板4との熱膨張係数の差による熱応力が
生じ、その熱応力が半田による接合部13に加わること
となる。また、この半導体装置の実装体を特に高温領域
で使用する場合には、半導体装置1と回路基板4との間
隙に充填されている封止樹脂14においても熱膨張によ
る新たな熱応力が生じ、この熱応力も半田による接合部
13に加わることとなる。したがって、この従来の実装
体においては、これらの熱応力がすべて半田による接合
部13に加わるので、半導体装置1と回路基板4との電
気的接続の信頼性が悪化する。
However, in the above-mentioned conventional package of a semiconductor device, the heat generated between the semiconductor device 1 and the circuit board 4 due to a change in environmental temperature when the package of the semiconductor device is used. A thermal stress is generated due to a difference in expansion coefficient, and the thermal stress is applied to the joint 13 by solder. Further, when the package of the semiconductor device is used in a particularly high-temperature region, a new thermal stress due to thermal expansion also occurs in the sealing resin 14 filled in the gap between the semiconductor device 1 and the circuit board 4, This thermal stress is also applied to the joint 13 by the solder. Therefore, in the conventional mounting body, since all of these thermal stresses are applied to the joint portion 13 made of solder, the reliability of the electrical connection between the semiconductor device 1 and the circuit board 4 deteriorates.

【0010】これらの熱応力を避けるためには、封止樹
脂14として熱膨張係数の小さなもの(さらに好ましく
は半田による接合部13の熱膨張係数に一致するもの)
を用いて、半田による接合部13の安定性を確保する必
要がある。このような(熱膨脹係数の小さい)封止樹脂
14としては、封止樹脂14中に無機フィラーを約40
〜75重量%(さらに好ましくは約50〜60重量%)
含有させたものが考えられる。
In order to avoid these thermal stresses, the sealing resin 14 having a small coefficient of thermal expansion (more preferably, matching the coefficient of thermal expansion of the joint 13 by soldering) is used.
It is necessary to secure the stability of the joint 13 by soldering. As such a sealing resin 14 (having a small coefficient of thermal expansion), an inorganic filler is added to the sealing resin 14 by about 40%.
~ 75% by weight (more preferably about 50-60% by weight)
It is conceivable that they are contained.

【0011】しかし、このような封止樹脂14(半田に
よる接合部13の熱膨脹係数に合致する程に小さい熱膨
脹係数を有するもの)を用いると、回路基板に対して垂
直方向(以下、単に「垂直方向」ともいう。)に働く半
田による接合部13の熱応力については解決するが、回
路基板に沿って平行方向(以下、「平面方向」とい
う。)に働く半導体装置1と回路基板4との熱膨張係数
の差によって生ずる熱応力については解決できない。そ
ればかりか、このような封止樹脂14を用いると、平面
方向の熱応力は一層増大する。
However, when such a sealing resin 14 (having a coefficient of thermal expansion small enough to match the coefficient of thermal expansion of the joint 13 by soldering) is used, a direction perpendicular to the circuit board (hereinafter simply referred to as “vertical”) is used. Although the thermal stress of the joint portion 13 due to the solder acting in the "direction" is solved, the semiconductor device 1 and the circuit board 4 which work in a parallel direction (hereinafter, referred to as "plane direction") along the circuit board. The thermal stress caused by the difference in thermal expansion coefficient cannot be solved. In addition, the use of such a sealing resin 14 further increases the thermal stress in the planar direction.

【0012】このような平面方向の熱応力の増大は、半
田による接合部13と半導体装置1および回路基板4と
の熱膨脹係数が大きく異なることにより生ずる。つま
り、封止樹脂14の熱膨脹係数を半田の接合部13に合
致させたとしても、半導体装置1および回路基板4の熱
膨脹係数とは合致させることができないので、その熱膨
脹係数の差によって熱応力の増大が起こるのである。し
たがって、これら平面方向の熱膨脹係数の差により生ず
る熱応力が、半田による接合部13へ加わり、半導体装
置1と回路基板4との電気的接続の信頼性を悪化させ
る。
Such an increase in the thermal stress in the plane direction is caused by a large difference between the thermal expansion coefficients of the joint portion 13 made of solder and the semiconductor device 1 and the circuit board 4. In other words, even if the coefficient of thermal expansion of the sealing resin 14 is matched with the joint 13 of the solder, the coefficient of thermal expansion cannot be matched with the coefficients of thermal expansion of the semiconductor device 1 and the circuit board 4. An increase occurs. Therefore, thermal stress generated due to the difference between the thermal expansion coefficients in the planar direction is applied to the joint 13 by solder, and the reliability of the electrical connection between the semiconductor device 1 and the circuit board 4 is deteriorated.

【0013】本発明は、このような課題を解決するため
になされたもので、信頼性の高い半導体装置の実装体
と、これを得るための半導体装置の実装方法を提供する
ことを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a highly reliable semiconductor device package and a semiconductor device mounting method for obtaining the same. .

【0014】[0014]

【課題を解決するための手段】上記目的を達成するため
の本発明は、半導体装置をフェースダウンで回路基板に
実装する半導体装置の実装方法であって、前記半導体装
置を前記回路基板に実装する工程と、前記半導体装置と
前記回路基板との間隙に樹脂と無機フィラーとを含む液
状の樹脂組成物を充填する工程と、前記無機フィラーが
熱膨脹係数の小さい部材の近傍に位置する状態で前記樹
脂組成物を硬化する工程とを有することを特徴とする。
According to the present invention, there is provided a method of mounting a semiconductor device on a circuit board face down, wherein the semiconductor device is mounted on the circuit board. A step of filling a liquid resin composition containing a resin and an inorganic filler in a gap between the semiconductor device and the circuit board; and a step of filling the resin in a state where the inorganic filler is located near a member having a small coefficient of thermal expansion. Curing the composition.

【0015】こうすることにより、前記半導体装置と前
記回路基板との間に介在する硬化後の前記樹脂組成物に
おいては、前記無機フィラーの分布状態、つまり前記無
機フィラーの在る部分と無い部分との間で熱膨脹係数の
傾きが発生することとなる。したがって、前記無機フィ
ラーを如何に分布させるかにより、前記樹脂組成物の熱
膨脹による熱応力の発生を、垂直方向および平面方向と
もに効果的に防止することができる。
By doing so, in the cured resin composition interposed between the semiconductor device and the circuit board, the distribution state of the inorganic filler, that is, the portion where the inorganic filler exists and the portion where the inorganic filler does not exist, Between them, a gradient of the coefficient of thermal expansion occurs. Therefore, depending on how the inorganic filler is distributed, generation of thermal stress due to thermal expansion of the resin composition can be effectively prevented in both the vertical direction and the planar direction.

【0016】また、前記半導体装置の熱膨脹係数が前記
回路基板の熱膨脹係数よりも大きい場合には、前記無機
フィラーが前記回路基板の近傍に位置する状態で前記樹
脂組成物を硬化することが好ましい。ここで前記無機フ
ィラーは、熱伝導性を向上させる効果を有するので、前
記実装方法によれば前記回路基板に対する熱伝導が向上
し、前記半導体装置と前記回路基板の熱膨脹係数の差が
緩和される。したがって、硬化後の前記樹脂組成物は垂
直方向に熱膨脹係数の傾きを有することとなり、前記樹
脂組成物の熱膨脹による熱応力の発生を垂直方向および
平面方向ともに防止することができ、前記半導体装置と
前記回路基板とを信頼性高く実装することができる。
When the coefficient of thermal expansion of the semiconductor device is larger than the coefficient of thermal expansion of the circuit board, it is preferable that the resin composition is cured while the inorganic filler is located near the circuit board. Here, since the inorganic filler has an effect of improving thermal conductivity, according to the mounting method, heat conduction to the circuit board is improved, and a difference in thermal expansion coefficient between the semiconductor device and the circuit board is reduced. . Therefore, the cured resin composition has a gradient of the thermal expansion coefficient in the vertical direction, and can prevent the occurrence of thermal stress due to the thermal expansion of the resin composition in both the vertical direction and the planar direction. The circuit board can be mounted with high reliability.

【0017】さらに、前記半導体装置の熱膨脹係数が前
記回路基板の熱膨脹係数よりも小さい場合には、前記無
機フィラーが前記半導体装置の近傍に位置する状態で前
記樹脂組成物を硬化することが好ましい。こうすること
により、前記半導体装置に対する熱伝導が向上し、前記
半導体装置と前記回路基板の熱膨脹係数の差が緩和さ
れ、前記樹脂組成物の熱膨脹による熱応力の発生を垂直
方向におよび平面方向ともに防止することができる。
Further, when the coefficient of thermal expansion of the semiconductor device is smaller than the coefficient of thermal expansion of the circuit board, it is preferable to cure the resin composition in a state where the inorganic filler is located near the semiconductor device. By doing so, the heat conduction to the semiconductor device is improved, the difference in the coefficient of thermal expansion between the semiconductor device and the circuit board is reduced, and the generation of thermal stress due to the thermal expansion of the resin composition is reduced in both the vertical direction and the planar direction. Can be prevented.

【0018】また、前記無機フィラーの位置決めを行う
方法としては、前記液状の樹脂組成物中の前記樹脂と前
記無機フィラーとの比重差を利用する方法、および前記
液状の樹脂組成物中の前記樹脂の粘度が高温状態で急激
に下がる性質を利用する方法等が好ましい。さらに、前
記無機フィラーを前記半導体装置の近傍に位置させる方
法として、前記回路基板を裏返して前記樹脂と前記無機
フィラーとの比重差を利用する方法も好ましい。また、
前記無機フィラーの位置決めと、前記液状の樹脂組成物
の硬化とを同一の工程で行う方法も好ましい。
Further, as a method of positioning the inorganic filler, a method of utilizing a specific gravity difference between the resin in the liquid resin composition and the inorganic filler, and a method of positioning the resin in the liquid resin composition, A method utilizing the property of rapidly decreasing the viscosity of the polymer at high temperatures is preferred. Furthermore, as a method of positioning the inorganic filler near the semiconductor device, a method of turning over the circuit board and utilizing a difference in specific gravity between the resin and the inorganic filler is also preferable. Also,
A method in which the positioning of the inorganic filler and the curing of the liquid resin composition are performed in the same step is also preferable.

【0019】さらに、前記半導体装置を半田バンプを用
いて前記回路基板に実装する方法、前記半導体装置を導
電性接着剤を用いて前記回路基板に実装する方法、およ
び前記半導体装置を突起電極と導電性接着剤とを用いて
前記回路基板に実装する方法等も好ましい。
Further, a method for mounting the semiconductor device on the circuit board using solder bumps, a method for mounting the semiconductor device on the circuit board using a conductive adhesive, and a method for mounting the semiconductor device on a bump electrode It is also preferable to use a method of mounting on the circuit board using a conductive adhesive.

【0020】また、本発明に係る半導体装置に実装体
は、半導体装置が回路基板に実装され、前記半導体装置
と前記回路基板との間隙に樹脂と無機フィラーとを含む
樹脂組成物が備えられ、前記樹脂組成物中の前記無機フ
ィラーが熱膨脹係数の小さい部材の近傍に位置した状態
であることを特徴とする。さらに、熱膨脹係数が前記回
路基板に対して垂直方向に変化する前記樹脂組成物が備
えられていることが好ましい。また、前記半導体装置の
熱膨脹係数が前記回路基板の熱膨脹係数よりも大きい場
合には、前記樹脂組成物中の前記無機フィラーが前記回
路基板の近傍に位置した状態であること、および前記半
導体装置の熱膨脹係数が前記回路基板の熱膨脹係数より
も小さい場合には、前記樹脂組成物中の前記無機フィラ
ーが前記半導体装置の近傍に位置した状態であることが
好ましい。
The semiconductor device according to the present invention has a package wherein the semiconductor device is mounted on a circuit board, and a resin composition containing a resin and an inorganic filler is provided in a gap between the semiconductor device and the circuit board. The inorganic filler in the resin composition is located near a member having a small coefficient of thermal expansion. Further, it is preferable to provide the resin composition whose coefficient of thermal expansion changes in a direction perpendicular to the circuit board. Further, when the coefficient of thermal expansion of the semiconductor device is larger than the coefficient of thermal expansion of the circuit board, the inorganic filler in the resin composition is located in the vicinity of the circuit board; and When the coefficient of thermal expansion is smaller than the coefficient of thermal expansion of the circuit board, it is preferable that the inorganic filler in the resin composition is located near the semiconductor device.

【0021】このような構成にしたことにより、垂直方
向においては、前記樹脂組成物の垂直方向の熱膨張係数
の平均値と、前記半導体装置と前記回路基板との接続部
分の垂直方向の熱膨張係数の値とをほぼ同一に維持する
ことができ、平面方向においては、垂直方向に熱膨脹係
数が変化する前記樹脂組成物によって、前記半導体装置
側と前記回路基板側との熱膨脹係数の差を緩和すること
ができる。したがって、前記樹脂組成物の熱膨脹による
熱応力の発生を垂直方向および平面方向ともに効果的に
防止することが可能となり、前記半導体装置と前記回路
基板の熱膨脹係数が異なる場合においても、信頼性の高
い半導体装置の実装体を得ることができる。
With such a configuration, in the vertical direction, the average value of the thermal expansion coefficient of the resin composition in the vertical direction and the thermal expansion coefficient of the connection portion between the semiconductor device and the circuit board in the vertical direction are obtained. The coefficient value can be kept substantially the same, and in the plane direction, the difference in the coefficient of thermal expansion between the semiconductor device side and the circuit board side is reduced by the resin composition whose coefficient of thermal expansion changes in the vertical direction. can do. Therefore, it is possible to effectively prevent the occurrence of thermal stress due to the thermal expansion of the resin composition in both the vertical direction and the planar direction. Even when the semiconductor device and the circuit board have different thermal expansion coefficients, high reliability is obtained. A package of a semiconductor device can be obtained.

【0022】さらに、前記樹脂組成物の前記回路基板に
対する垂直方向の熱膨脹係数の平均値と、前記半導体装
置と前記回路基板との接続部分の前記回路基板に対する
垂直方向の熱膨脹係数の値とがほぼ一致するように、前
記樹脂と前記無機フィラーとの割合が調整された前記樹
脂組成物が備えられていることが好ましい。前記樹脂組
成物中の前記無機フィラーとしては、球状の無機フィラ
ーが用いられていることも好ましい。
Further, the average value of the thermal expansion coefficient of the resin composition in the direction perpendicular to the circuit board and the value of the thermal expansion coefficient of the connection portion between the semiconductor device and the circuit board in the direction perpendicular to the circuit board are substantially equal to each other. It is preferable to provide the resin composition in which the ratio between the resin and the inorganic filler is adjusted so as to match. It is also preferable that a spherical inorganic filler is used as the inorganic filler in the resin composition.

【0023】また、前記半導体装置が半田バンプを用い
て前記回路基板に実装されていること、前記半導体装置
が導電性接着剤を用いて前記回路基板に実装されている
こと、および前記半導体装置が突起電極と導電性接着剤
とを用いて前記回路基板に実装されていることも好まし
い。
The semiconductor device is mounted on the circuit board using solder bumps, the semiconductor device is mounted on the circuit board using a conductive adhesive, and the semiconductor device is mounted on the circuit board using a conductive adhesive. It is also preferable that the circuit board is mounted on the circuit board using a projecting electrode and a conductive adhesive.

【0024】[0024]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面に基づいて説明する。図1は、本発明の第一の
実施形態に係る半導体装置の実装方法についての工程図
を示している。図1において、1は半導体装置、2は端
子電極、3は導電性接着剤、4は回路基板、5は接続電
極、6は導電性接着剤による接合部、7は液状の樹脂組
成物、8は樹脂、9は無機フィラー、10は硬化後の樹
脂組成物である。以下、図1の工程図に基づいて、この
第一の実施形態に係る半導体装置の実装方法について説
明する。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a process chart of a method for mounting a semiconductor device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor device, 2 denotes a terminal electrode, 3 denotes a conductive adhesive, 4 denotes a circuit board, 5 denotes a connection electrode, 6 denotes a joint portion using a conductive adhesive, 7 denotes a liquid resin composition, and 8 denotes a liquid resin composition. Is a resin, 9 is an inorganic filler, and 10 is a cured resin composition. Hereinafter, a method for mounting the semiconductor device according to the first embodiment will be described with reference to the process chart of FIG.

【0025】まず、図1(a)に示すように、半導体装
置1の端子電極2にあらかじめ導電性接着剤3を形成す
る。この場合、導電性接着剤3は、端子電極2の上に直
接形成してもよいし、端子電極2にあらかじめ形成した
突起電極(バンプ)の上に形成してもよい。
First, as shown in FIG. 1A, a conductive adhesive 3 is formed on the terminal electrodes 2 of the semiconductor device 1 in advance. In this case, the conductive adhesive 3 may be formed directly on the terminal electrode 2 or may be formed on a bump electrode (bump) formed on the terminal electrode 2 in advance.

【0026】次に、図1(b)に示すように、この半導
体装置1をフェースダウン(下向き)にして回路基板4
(例えばガラエポ基板)の接続電極5の所定の位置に位
置合わせを行い、回路基板4の上に半導体装置1を搭載
する。これにより、半導体装置1の端子電極2と回路基
板4の接続電極5とが導電性接着剤による接合部6によ
って電気的に接続される。この場合、半導体装置1の熱
膨張係数は回路基板4の熱膨張係数よりも小さい。
Next, as shown in FIG. 1B, the semiconductor device 1 is turned face down (downward) and the circuit board 4 is turned down.
The semiconductor device 1 is mounted on the circuit board 4 by positioning the connection electrode 5 on a predetermined position (for example, a glass epoxy substrate). As a result, the terminal electrodes 2 of the semiconductor device 1 and the connection electrodes 5 of the circuit board 4 are electrically connected by the joints 6 made of the conductive adhesive. In this case, the thermal expansion coefficient of the semiconductor device 1 is smaller than the thermal expansion coefficient of the circuit board 4.

【0027】次に、図1(c)に示すように、半導体装
置1と回路基板4との間隙に液状の樹脂組成物7を充填
する。そして、図1(d)に示すように、回路基板4を
裏返して150℃程度の温度で加熱することにより液状
の樹脂組成物7を硬化させる。そうすると、液状の樹脂
組成物7中で、樹脂8(例えばエポキシ樹脂)と無機フ
ィラー9(例えばシリカ)との比重差によって無機フィ
ラー9が半導体装置1側に沈降した状態での硬化後の樹
脂組成物10を得ることができる。
Next, as shown in FIG. 1C, a gap between the semiconductor device 1 and the circuit board 4 is filled with a liquid resin composition 7. Then, as shown in FIG. 1D, the liquid resin composition 7 is cured by turning the circuit board 4 upside down and heating at a temperature of about 150 ° C. Then, in the liquid resin composition 7, the cured resin composition in a state where the inorganic filler 9 has settled to the semiconductor device 1 due to the specific gravity difference between the resin 8 (for example, epoxy resin) and the inorganic filler 9 (for example, silica) The object 10 can be obtained.

【0028】以上の工程により、図2に示すような半導
体装置1の実装体を得ることができる。このとき用いら
れる液状の樹脂組成物7には、少なくとも樹脂8と無機
フィラー9とが含有されている。またこの樹脂組成物7
としては、硬化後の樹脂組成物10の熱膨張係数が導電
性接着剤の接合部6の熱膨張係数に一致するように、樹
脂8と無機フィラー9との割合が調整されているものが
用いられる。このため、硬化後の樹脂組成物10中で無
機フィラー9が沈降した状態であっても、硬化後の樹脂
組成物10の平均した垂直方向の熱膨張係数は導電性接
着剤の接合部6の垂直方向の熱膨張係数と一致してい
る。
Through the above steps, a package of the semiconductor device 1 as shown in FIG. 2 can be obtained. The liquid resin composition 7 used at this time contains at least the resin 8 and the inorganic filler 9. The resin composition 7
A resin in which the ratio between the resin 8 and the inorganic filler 9 is adjusted such that the coefficient of thermal expansion of the cured resin composition 10 matches the coefficient of thermal expansion of the joint 6 of the conductive adhesive is used. Can be For this reason, even when the inorganic filler 9 is settled in the cured resin composition 10, the average thermal expansion coefficient of the cured resin composition 10 in the vertical direction is smaller than that of the joint 6 of the conductive adhesive. It matches the coefficient of thermal expansion in the vertical direction.

【0029】また、上記工程においては、無機フィラー
9を半導体装置1側に寄せた状態で硬化させたので、硬
化後の樹脂組成物10の平面方向の熱膨張係数は、熱膨
張係数の小さい半導体装置1側では小さく、熱膨張係数
の大きい回路基板4側では大きいといったように、硬化
後の樹脂組成物10中で垂直方向に熱膨張係数の傾斜を
有する。
In the above process, since the inorganic filler 9 is cured with the inorganic filler 9 being moved toward the semiconductor device 1, the cured resin composition 10 has a small thermal expansion coefficient in the plane direction. The resin composition 10 after curing has a gradient of the thermal expansion coefficient in the vertical direction, such as being small on the device 1 side and large on the circuit board 4 side having a large thermal expansion coefficient.

【0030】したがって、半導体装置1を高温で使用す
る場合においても、半導体装置1と回路基板4との間隙
に存在する硬化後の樹脂組成物10の熱膨張による垂直
方向および平面方向の熱応力の発生を防止することがで
きる。その結果、電気的な接続の信頼性の高い半導体装
置1の実装体を得ることができる。
Therefore, even when the semiconductor device 1 is used at a high temperature, the thermal stress in the vertical and planar directions due to the thermal expansion of the cured resin composition 10 existing in the gap between the semiconductor device 1 and the circuit board 4 is reduced. Generation can be prevented. As a result, a mounted body of the semiconductor device 1 with high electrical connection reliability can be obtained.

【0031】また、以上の構成にすることにより、液状
の樹脂組成物7を加熱硬化した後に常温に戻す際におい
ても、硬化後の樹脂組成物10の熱収縮による垂直方向
および平面方向の熱応力の発生を防止することができ
る。したがって、半導体装置1を回路基板4に実装する
際の電気的な接続の信頼性が向上する。
Further, with the above configuration, even when the liquid resin composition 7 is cured by heating and then returned to room temperature, the thermal stress in the vertical and planar directions due to the heat shrinkage of the cured resin composition 10 can be improved. Can be prevented from occurring. Therefore, the reliability of electrical connection when mounting the semiconductor device 1 on the circuit board 4 is improved.

【0032】図3は、本発明の第二の実施形態に係る半
導体装置の実装体を示している。図3において、1は半
導体装置、2は端子電極、4は回路基板、5は接続電
極、6は導電性接着剤による接合部、10は硬化後の樹
脂組成物、11は突起電極である。
FIG. 3 shows a semiconductor device package according to a second embodiment of the present invention. In FIG. 3, 1 is a semiconductor device, 2 is a terminal electrode, 4 is a circuit board, 5 is a connection electrode, 6 is a joint made of a conductive adhesive, 10 is a cured resin composition, and 11 is a bump electrode.

【0033】この第二の実施形態に係る半導体装置の実
装体は、半導体装置1の端子電極2に突起電極11を設
けた構成としている。その他の構成は、実質的に上記第
一の実施形態と同様である。突起電極11の材料として
は、Au等を用いる。この第二の実施形態に示したよう
に、端子電極2に突起電極11を設けた構成とすると、
上記第1の実施形態の効果に加えて、半導体装置1を回
路基板4に実装する際の導電性接着剤の広がりを規制す
ることができ、微細ピッチでの接合が可能となる。
The package of the semiconductor device according to the second embodiment has a configuration in which the protruding electrode 11 is provided on the terminal electrode 2 of the semiconductor device 1. Other configurations are substantially the same as those of the first embodiment. Au or the like is used as the material of the bump electrode 11. As shown in the second embodiment, when the terminal electrode 2 is provided with the protruding electrode 11,
In addition to the effects of the first embodiment, the spread of the conductive adhesive when the semiconductor device 1 is mounted on the circuit board 4 can be restricted, and bonding at a fine pitch becomes possible.

【0034】図4は、本発明の第三の実施形態に係る半
導体装置の実装体を示している。図4において、1は半
導体装置、2は端子電極、4は回路基板、5は接続電
極、10は硬化後の樹脂組成物、12は半田による接合
部である。
FIG. 4 shows a semiconductor device package according to a third embodiment of the present invention. In FIG. 4, 1 is a semiconductor device, 2 is a terminal electrode, 4 is a circuit board, 5 is a connection electrode, 10 is a cured resin composition, and 12 is a joint portion formed by soldering.

【0035】この第三の実施形態に係る半導体装置の実
装体は、半導体装置1の端子電極2を回路基板4の端子
電極5に半田による接合部12で実装した構成としてい
る。その他の構成は、実質敵に上記第一の実施形態と同
様である。
The mounting body of the semiconductor device according to the third embodiment has a configuration in which the terminal electrode 2 of the semiconductor device 1 is mounted on the terminal electrode 5 of the circuit board 4 at the joint 12 made of solder. Other configurations are substantially the same as those of the first embodiment.

【0036】この第三の実施形態に示したように、半田
による接合部12を用いて半導体装置1を回路基板4に
実装する構成とすると、上記第1の実施形態の効果に加
えて、半導体装置1を回路基板4に、より強固に実装す
ることができる。また、従来の半田による実装方法で
は、熱応力の問題で回路基板の材質が半導体装置の熱膨
張係数に近いもの(例えば、セラミック基板)に限定さ
れていたが、本実施形態によれば、あらゆる材質の回路
基板を用いることが可能となる。
As shown in the third embodiment, when the semiconductor device 1 is mounted on the circuit board 4 by using the bonding portion 12 made of solder, the semiconductor device 1 has the advantages of the first embodiment. The device 1 can be more firmly mounted on the circuit board 4. Further, in the conventional mounting method using solder, the material of the circuit board is limited to a material close to the coefficient of thermal expansion of the semiconductor device (for example, a ceramic substrate) due to a problem of thermal stress. A circuit board made of a material can be used.

【0037】また、以上の第一の実施形態、第二の実施
形態および第三の実施形態においては、半導体装置1の
熱膨脹係数よりも回路基板4の熱膨脹係数の方が大きい
場合を想定して、樹脂組成物中の無機フィラー9を半導
体装置1側に沈降させた構成について説明したが、本発
明はこれに限定されるものではない。半導体装置1の熱
膨脹係数よりも回路基板4の熱膨脹係数の方が小さい場
合(本実施形態と逆の関係)には、樹脂組成物中の無機
フィラー9を回路基板4側に沈降させた構成とすればよ
く、この構成は、液状の樹脂組成物の硬化を行う際に、
回路基板4を裏返さずに硬化させることによって容易に
得ることができる。
In the first, second and third embodiments described above, it is assumed that the circuit board 4 has a larger coefficient of thermal expansion than the semiconductor device 1. Although the configuration in which the inorganic filler 9 in the resin composition is settled on the semiconductor device 1 side has been described, the present invention is not limited to this. When the coefficient of thermal expansion of the circuit board 4 is smaller than the coefficient of thermal expansion of the semiconductor device 1 (reverse relationship to the present embodiment), the configuration is such that the inorganic filler 9 in the resin composition is settled on the circuit board 4 side. This configuration may be used when curing a liquid resin composition.
It can be easily obtained by curing the circuit board 4 without turning over.

【0038】[0038]

【発明の効果】本発明に係る半導体装置の実装方法によ
れば、半導体装置の実装体を生産する際に高温状態から
常温状態にする工程を行った場合においても、樹脂組成
物の熱収縮による垂直方向および平面方向の熱応力の発
生を防止することができる。したがって、半導体装置を
回路基板に信頼性高く実装することができる。
According to the method of mounting a semiconductor device according to the present invention, even when a step of changing from a high temperature state to a normal temperature state is performed during the production of a semiconductor device package, heat shrinkage of the resin composition occurs. The generation of thermal stress in the vertical direction and the plane direction can be prevented. Therefore, the semiconductor device can be mounted on the circuit board with high reliability.

【0039】また、本発明に係る半導体装置の実装体に
よれば、この半導体装置の実装体を高温状態で使用する
場合にあっても、樹脂組成物の熱膨張による垂直方向お
よび平面方向の熱応力の発生を防止することができる。
したがって、半導体装置の実装体は信頼性の高いものと
なる。
Further, according to the semiconductor device package of the present invention, even when the semiconductor device package is used in a high temperature state, the thermal expansion in the vertical direction and the planar direction due to the thermal expansion of the resin composition. Generation of stress can be prevented.
Therefore, the mounted body of the semiconductor device has high reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第一の実施形態に係る半導体装置の実
装方法を示す工程図
FIG. 1 is a process chart showing a method for mounting a semiconductor device according to a first embodiment of the present invention;

【図2】本発明の第一の実施形態に係る半導体装置の実
装体の要部断面図
FIG. 2 is a cross-sectional view of a main part of the mounted body of the semiconductor device according to the first embodiment of the present invention;

【図3】本発明の第二の実施形態に係る半導体装置の実
装体の要部断面図
FIG. 3 is an essential part cross-sectional view of a semiconductor device package according to a second embodiment of the present invention;

【図4】本発明の第三の実施形態に係る半導体装置の実
装体の要部断面図
FIG. 4 is an essential part cross-sectional view of a semiconductor device package according to a third embodiment of the present invention;

【図5】従来技術における半導体装置の実装体の要部断
面図
FIG. 5 is a cross-sectional view of a main part of a semiconductor device package according to the related art.

【符号の説明】[Explanation of symbols]

1 半導体装置 2 端子電極 3 導電性接着剤 4 回路基板 5 接続電極 6 導電性接着剤による接合部 7 液状の樹脂組成物 8 樹脂 9 無機フィラー 10 硬化後の樹脂組成物 11 突起電極 12,13 半田による接合部 14 封止樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Terminal electrode 3 Conductive adhesive 4 Circuit board 5 Connection electrode 6 Joining part by conductive adhesive 7 Liquid resin composition 8 Resin 9 Inorganic filler 10 Cured resin composition 11 Protrusion electrodes 12, 13 Solder Joint 14 by sealing resin

Claims (21)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体装置をフェースダウンで回路基板
に実装する半導体装置の実装方法であって、前記半導体
装置を前記回路基板に実装する工程と、前記半導体装置
と前記回路基板との間隙に樹脂と無機フィラーとを含む
液状の樹脂組成物を充填する工程と、前記無機フィラー
が熱膨脹係数の小さい部材の近傍に位置する状態で前記
樹脂組成物を硬化する工程とを有することを特徴とする
半導体装置の実装方法。
1. A method of mounting a semiconductor device on a circuit board face-down, comprising the steps of: mounting the semiconductor device on the circuit board; and forming a resin in a gap between the semiconductor device and the circuit board. A semiconductor, comprising: a step of filling a liquid resin composition containing a resin and an inorganic filler; and a step of curing the resin composition in a state where the inorganic filler is located near a member having a small coefficient of thermal expansion. How to mount the device.
【請求項2】 前記半導体装置の熱膨脹係数が前記回路
基板の熱膨脹係数よりも大きい場合には、前記無機フィ
ラーが前記回路基板の近傍に位置する状態で前記樹脂組
成物を硬化する請求項1記載の半導体装置の実装方法。
2. The method according to claim 1, wherein when the coefficient of thermal expansion of the semiconductor device is larger than the coefficient of thermal expansion of the circuit board, the resin composition is cured with the inorganic filler positioned near the circuit board. Semiconductor device mounting method.
【請求項3】 前記半導体装置の熱膨脹係数が前記回路
基板の熱膨脹係数よりも小さい場合には、前記無機フィ
ラーが前記半導体装置の近傍に位置する状態で前記樹脂
組成物を硬化する請求項1記載の半導体装置の実装方
法。
3. The method according to claim 1, wherein when the coefficient of thermal expansion of the semiconductor device is smaller than the coefficient of thermal expansion of the circuit board, the resin composition is cured in a state where the inorganic filler is located near the semiconductor device. Semiconductor device mounting method.
【請求項4】 前記無機フィラーの位置決めを行う方法
として、前記液状の樹脂組成物中の前記樹脂と前記無機
フィラーとの比重差を利用する請求項1,2または3記
載の半導体装置の実装方法。
4. The method of mounting a semiconductor device according to claim 1, wherein the method of positioning the inorganic filler uses a specific gravity difference between the resin and the inorganic filler in the liquid resin composition. .
【請求項5】 前記無機フィラーを前記半導体装置の近
傍に位置させる方法として、前記回路基板を裏返して前
記樹脂と前記無機フィラーとの比重差を利用する請求項
3記載の半導体装置の実装方法。
5. The method of mounting a semiconductor device according to claim 3, wherein the method of locating the inorganic filler near the semiconductor device utilizes a difference in specific gravity between the resin and the inorganic filler by turning over the circuit board.
【請求項6】 前記無機フィラーの位置決めを行う方法
として、前記液状の樹脂組成物中の前記樹脂の粘度が高
温状態で急激に下がる性質を利用する請求項1から5の
いずれか1項記載の半導体装置の実装方法。
6. The method according to claim 1, wherein the method of positioning the inorganic filler utilizes a property that the viscosity of the resin in the liquid resin composition drops rapidly at a high temperature. A method for mounting a semiconductor device.
【請求項7】 前記無機フィラーの位置決めと、前記液
状の樹脂組成物の硬化とを同一の工程で行う請求項6記
載の半導体装置の実装方法。
7. The method according to claim 6, wherein the positioning of the inorganic filler and the curing of the liquid resin composition are performed in the same step.
【請求項8】 前記半導体装置を半田バンプを用いて前
記回路基板に実装する請求項1から7のいずれか1項記
載の半導体装置の実装方法。
8. The method according to claim 1, wherein the semiconductor device is mounted on the circuit board using solder bumps.
【請求項9】 前記半導体装置を導電性接着剤を用いて
前記回路基板に実装する請求項1から7のいずれか1項
記載の半導体装置の実装方法。
9. The method of mounting a semiconductor device according to claim 1, wherein the semiconductor device is mounted on the circuit board using a conductive adhesive.
【請求項10】 前記半導体装置を突起電極と導電性接
着剤とを用いて前記回路基板に実装する請求項1から7
のいずれか1項記載の半導体装置の実装方法。
10. The semiconductor device is mounted on the circuit board using a bump electrode and a conductive adhesive.
A method for mounting a semiconductor device according to any one of the preceding claims.
【請求項11】 半導体装置が回路基板に実装され、前
記半導体装置と前記回路基板との間隙に樹脂と無機フィ
ラーとを含む樹脂組成物が備えられ、前記樹脂組成物中
の前記無機フィラーが熱膨脹係数の小さい部材の近傍に
位置した状態であることを特徴とする半導体装置の実装
体。
11. A semiconductor device is mounted on a circuit board, a resin composition containing a resin and an inorganic filler is provided in a gap between the semiconductor device and the circuit board, and the inorganic filler in the resin composition is thermally expanded. A mounted body of a semiconductor device, wherein the mounted body is located near a member having a small coefficient.
【請求項12】 熱膨脹係数が前記回路基板に対して垂
直方向に変化する前記樹脂組成物が備えられている請求
項11記載の半導体装置の実装体。
12. The semiconductor device according to claim 11, further comprising the resin composition having a coefficient of thermal expansion that changes in a direction perpendicular to the circuit board.
【請求項13】 前記半導体装置の熱膨脹係数が前記回
路基板の熱膨脹係数よりも大きい場合には、前記樹脂組
成物中の前記無機フィラーが前記回路基板の近傍に位置
した状態である請求項11または12記載の半導体装置
の実装体。
13. The semiconductor device according to claim 11, wherein when the coefficient of thermal expansion of the semiconductor device is larger than the coefficient of thermal expansion of the circuit board, the inorganic filler in the resin composition is located near the circuit board. 13. A mounted body of the semiconductor device according to 12.
【請求項14】 前記半導体装置の熱膨脹係数が前記回
路基板の熱膨脹係数よりも小さい場合には、前記樹脂組
成物中の前記無機フィラーが前記半導体装置の近傍に位
置した状態である請求項11または12記載の半導体装
置の実装体。
14. The semiconductor device according to claim 11, wherein when the coefficient of thermal expansion of the semiconductor device is smaller than the coefficient of thermal expansion of the circuit board, the inorganic filler in the resin composition is located near the semiconductor device. 13. A mounted body of the semiconductor device according to 12.
【請求項15】 前記樹脂組成物の前記回路基板に対す
る垂直方向の熱膨脹係数の平均値が、前記半導体装置と
前記回路基板との接続部分の前記回路基板に対する垂直
方向の熱膨脹係数の値とほぼ一致している請求項12,
13または14記載の半導体装置の実装体。
15. An average value of a coefficient of thermal expansion of the resin composition in a direction perpendicular to the circuit board is substantially equal to a value of a coefficient of thermal expansion of a connection portion between the semiconductor device and the circuit board in a direction perpendicular to the circuit board. Claim 12,
15. A package of the semiconductor device according to 13 or 14.
【請求項16】 前記樹脂組成物の前記回路基板に対す
る垂直方向の熱膨脹係数の平均値と、前記半導体装置と
前記回路基板との接続部分の前記回路基板に対する垂直
方向の熱膨脹係数の値とがほぼ一致するように、前記樹
脂と前記無機フィラーとの割合が調整された前記樹脂組
成物が備えられている請求項15記載の半導体装置の実
装体。
16. An average value of a thermal expansion coefficient of the resin composition in a direction perpendicular to the circuit board, and a value of a thermal expansion coefficient of a connection portion between the semiconductor device and the circuit board in a direction perpendicular to the circuit board are substantially equal to each other. The semiconductor device package according to claim 15, further comprising: the resin composition in which a ratio of the resin and the inorganic filler is adjusted to match.
【請求項17】 前記樹脂組成物中の前記無機フィラー
として、球状の無機フィラーを用いた請求項11から1
6のいずれか1項記載の半導体装置の実装体。
17. The method according to claim 11, wherein a spherical inorganic filler is used as the inorganic filler in the resin composition.
7. A mounted body of the semiconductor device according to claim 6.
【請求項18】 前記半導体装置が半田バンプを用いて
前記回路基板に実装されている請求項11から17のい
ずれか1項記載の半導体装置の実装体。
18. The semiconductor device according to claim 11, wherein the semiconductor device is mounted on the circuit board by using solder bumps.
【請求項19】 前記半導体装置が導電性接着剤を用い
て前記回路基板に実装されている請求項11から17の
いずれか1項記載の半導体装置の実装体。
19. The semiconductor device package according to claim 11, wherein said semiconductor device is mounted on said circuit board using a conductive adhesive.
【請求項20】 前記半導体装置が突起電極と導電性接
着剤とを用いて前記回路基板に実装されている請求項1
1から17のいずれか1項記載の半導体装置の実装体。
20. The semiconductor device according to claim 1, wherein the semiconductor device is mounted on the circuit board using a bump electrode and a conductive adhesive.
18. A mounted body of the semiconductor device according to any one of 1 to 17.
【請求項21】 熱膨脹係数の異なる前記半導体装置と
前記回路基板とが備えられている請求項11から20の
いずれか1項記載の半導体装置の実装体。
21. The semiconductor device package according to claim 11, further comprising the semiconductor device having different coefficients of thermal expansion and the circuit board.
JP7367496A 1996-03-28 1996-03-28 Semiconductor device mounting method and semiconductor device mounted body Expired - Lifetime JP2930186B2 (en)

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Application Number Priority Date Filing Date Title
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JP2930186B2 true JP2930186B2 (en) 1999-08-03

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JP4097379B2 (en) * 1999-01-29 2008-06-11 松下電器産業株式会社 Electronic component mounting method and apparatus
KR100502222B1 (en) 1999-01-29 2005-07-18 마츠시타 덴끼 산교 가부시키가이샤 Electronic parts mounting method and device therefor
JP4097378B2 (en) * 1999-01-29 2008-06-11 松下電器産業株式会社 Electronic component mounting method and apparatus
JP4459258B2 (en) * 1999-01-29 2010-04-28 パナソニック株式会社 Electronic component mounting method
JP4029255B2 (en) * 1999-02-18 2008-01-09 セイコーエプソン株式会社 Adhesive member
JP2001093938A (en) 1999-09-20 2001-04-06 Nec Kansai Ltd Semiconductor device and its manufacturing method
JP3598060B2 (en) * 1999-12-20 2004-12-08 松下電器産業株式会社 CIRCUIT COMPONENT MODULE, MANUFACTURING METHOD THEREOF, AND RADIO DEVICE
CN100370210C (en) * 2002-11-06 2008-02-20 徐惠群 Method for filling up slots between heat conductive parts as well as structure of part
JP5125309B2 (en) * 2007-08-20 2013-01-23 株式会社デンソー Manufacturing method of semiconductor device
JP5542470B2 (en) 2009-02-20 2014-07-09 パナソニック株式会社 Solder bump, semiconductor chip, semiconductor chip manufacturing method, conductive connection structure, and conductive connection structure manufacturing method
JP4686629B2 (en) * 2009-09-29 2011-05-25 株式会社東芝 Electronic component mounting method
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