JP2923970B2 - Motor control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor control circuit, and more particularly to a motor control circuit which counts a reference clock and resets a counter which is reset by a count-up output when a set count value is reached, according to the rotation of the motor. A so-called "speed discrimination" system that counts with a trigger pulse responding to the output rotation pulse (hereinafter, FG pulse) and outputs a fast signal or a slow signal according to the state of the counter and the FG pulse. The present invention relates to a motor control circuit.

2. Description of the Related Art In recent years, an example of this kind of speed discrimination type motor control circuit is, for example, an integrated circuit "HA1344" manufactured by Hitachi, Ltd.
0MP ”or the like. As is well known, this IC can control a three-phase brushless DC motor simply by connecting a crystal oscillator, a resistor and a capacitor as external components.

FIG. 5 is a block diagram showing the speed detection circuit of the prior art, wherein 1 is a 1/2 frequency divider, 2 is a trigger pulse generator, 3
Is an RS flip-flop, 3a and 3b are NAND gates, 4 is a counter, and 5 is a discrete output circuit. 1/2 frequency divider 1
Is the FG output according to the rotation of the DC motor (not shown).
A pulse is input and a 1 / 2FG signal that has been frequency-divided by 1/2 and a 1 / 2FGB signal that is the inverted output of the 1/2 frequency-divided signal are output. Both outputs are input to the discrimination output circuit 5, and the non-inverted output is output by the trigger pulse generator 2 in response to its rising edge, and a trigger pulse which becomes low level is output. This trigger pulse is transmitted to an RS flip-flop (hereinafter, “RS-FF”) 3
The reset input of RS-FF3 receives the count-up signal of the counter 4. Both the non-inverted output and the inverted output of RS-FF3 are input to the discrimination output circuit 5, and the counter 4 receives the counter reset signal which is the inverted output of RS-FF3, and the inverted output becomes low level by the trigger pulse. When the counter operates and reaches a reference count number, a reset pulse is output, and the inverted output of the RS-FF3 goes high, resetting the counter and entering a standby state waiting for the next trigger pulse. Discrete output circuit 5
1 / 2FG signal, 1 / 2FGB signal and RS-F which are the outputs of frequency divider 1
A count signal, which is a non-inverted output of F3, and a counter reset signal, which is an inverted output, are input, and a fast signal is output when the motor rotation speed is fast and a slow signal is output when the motor speed is slow according to the respective time widths.

In the conventional example of FIG. 5, when a motor (not shown) is rotating at a reference speed, as shown in FIG.
The 2FG signal and the counter reset signal are opposite to each other.
Therefore, the discrimination output circuit 5 does not output a fast signal indicating that the motor is rotating at a speed higher than the reference speed or a slow signal indicating that the motor is rotating at a speed lower than the reference speed. Locked to.

Problems to be Solved by the Invention However, in the above configuration, if the rotation speed of the motor becomes twice the reference speed for some reason, as shown in FIG. Two FG pulses are input during a period until the count value reaches “2048”. Then, as shown by and in FIG. 6B, a timing at which the trigger pulse and the reset pulse overlap appears. On the other hand, the discrete output circuit 5
Outputs a slow signal only while both the 1 / 2FG signal and the counter reset signal are at a high level. Therefore, in the double speed rotation state shown in FIG.
After that, the fast signal and the slow signal are mutually output at regular intervals. In this state, the fast signal and the slow signal are canceled each other, and as a result, the locked state is obtained as in the case of the reference speed.

Such a phenomenon of “double speed lock” similarly occurs even when the reference speed is three times or more.

When such "double speed lock" occurs, the motor no longer converges to the reference or rated speed. Therefore, in the related art, it is necessary to provide a loading circuit for detecting the "double speed locked" state, thereby performing a complicated control such as once releasing the control and restarting the control.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a so-called speed discrimination type motor control circuit which does not cause an undesirable "double speed lock".

Means for Solving the Problems In order to solve the above-mentioned conventional problems, a motor control circuit of the present invention includes a frequency divider that divides an FG pulse of a frequency generator output according to rotation of a motor; A trigger pulse generator that generates a trigger pulse with an FG pulse divided signal obtained by dividing a pulse by the frequency divider and a reference clock, and starts counting the reference clock from the time of generation of the trigger pulse. A counter that outputs a count-up signal when the count reaches a set count value, is reset when the count-up signal is output, a period of one cycle of the trigger pulse, and the counter starts counting the reference clock. And comparing the count value of the counter with the set count time until the count value of the counter reaches the set count value of the counter, When the time of one cycle is shorter than the set count time, a fast signal indicating that the rotation speed of the motor has rotated faster than the set rotation speed is output, and the time of one cycle of the trigger pulse is output. A discrimination output circuit that outputs a slow signal indicating that the motor has rotated slower than a set rotation number when the count time is longer than the set count time; and the counter counts the reference clock when the trigger pulse is input. During the operation, if a count-up signal has not yet been output, a high-speed detection circuit that determines that the motor is in a high-speed rotation state and outputs a high-speed detection output, and each signal line through which the fast signal and the slow signal are transmitted Is connected to an input terminal, and the output of the NOR gate is input, and the fast signal or the slow signal is output. The counter value of the lock detection circuit counter that counts the input time by the reference clock is compared with the set count of the lock detection circuit counter, and the counter value of the lock detection circuit counter is set to the lock detection circuit counter. A lock detection circuit that outputs a lock detection output indicating that the motor is in the rotational speed locked state when the set count is not reached, and the discrimination when there is no high-speed detection output and there is no lock detection output. When only the same signal as the slow signal of the output circuit is output, when there is no high-speed detection output and there is the lock detection output, it is the same as when neither the fast signal nor the slow signal of the discrete output circuit is output. When no signal is output to the device, the high-speed detection output is provided, and the lock detection output is not provided, the Only the same signal as the first signal of the screw output circuit is output, and when the high speed detection output is present and the lock detection output is also present, only the same signal as the first signal of the discrimination output circuit is output. And an output control circuit.

A frequency divider that divides an FG pulse of the frequency generator output according to the rotation of the motor; and a FG pulse divided signal obtained by dividing the FG pulse by the divider and a reference clock. A trigger pulse generator for generating a first trigger pulse responsive to the rising edge of the FG pulse divided signal and a second trigger pulse responsive to the falling edge of the FG pulse divided signal; A first counter which starts counting a reference clock, outputs a first reset pulse when the count reaches a set count value, and is reset when the first reset pulse is output; and when the second trigger pulse is generated. Starts the count of the reference clock, and outputs a second reset pulse when the count reaches a set count value, and resets when the second reset pulse is output. When both the first counter reset signal of the first counter and the second counter reset signal of the second counter are at a high level, the rotation speed of the motor has been slower than the set rotation speed. When the first counter reset signal of the first counter and the second counter reset signal of the second counter are both at a low level, the rotation speed of the motor is faster than the set rotation speed. When the first counter reset signal of the first counter is at a high level and the second counter reset signal of the second counter is at a low level, the slow signal also outputs the fast signal. No signal is output, and the first counter reset signal of the first counter is at a low level, and the second counter of the second counter is When the reset signal is at a high level, a discrete output circuit that does not output the slow signal or the fast signal, and the first counter counts the reference clock when the first trigger pulse is input. In the middle,
If the first reset pulse has not yet been output, a high-speed detection circuit that determines that the motor is in a high-speed rotation state and outputs a high-speed detection output; A NOR gate, a counter value of a lock detection circuit counter that receives an output of the NOR gate and counts a time when the first signal or the slow signal is output by a reference clock, and a counter value of the lock detection circuit counter. A lock that outputs a lock detection output indicating that the motor is in a rotation lock state when the set count is compared and the counter value of the lock detection circuit counter does not reach the set count of the lock detection circuit counter. A detection circuit, and when there is no high-speed detection output and no lock detection output, the discrimination output When only the same signal as the slow signal of the road is output, there is no high-speed detection output, and when there is the lock detection output, the same as the case where neither the fast signal nor the slow signal of the discrete output circuit is output. When no signal is output, the high-speed detection output is present and the lock detection output is not present, only the same signal as the fast signal of the discrete output circuit is output, and the high-speed detection output is present and the lock is output. An output control circuit for outputting only the same signal as the fast signal of the discrete output circuit when there is also a detection output.

Operation In the above configuration, an FG pulse having a period or frequency corresponding to the rotation speed of the motor is output, the FG pulse is divided by 1/2, and a trigger pulse is output in response to the rising pulse of the 1 / 2FG signal. You. The trigger pulse resets a counter that receives the reference clock as its count input. The counter uses a fixed number of reference clocks, for example, 2 ¹¹
= 2048, the count is reset by the count-up signal. Then, a fast signal or a slow signal is output from the discrimination output circuit according to the 1 / 2FG signal and the state of the counter. For example, if the 1 / 2FG signal is low and the counter is in the counter state, a fast signal is output, and if the 1 / 2FG signal is high and the counter is not in the count state, a slow signal is output.

When the next 1 / 2FG signal is input while the counter is operating, the high-speed detection circuit detects that the motor is rotating at or above the reference speed. That is, the counter is reset when "2048" has been counted, but the time until reaching the set count value is selected so as to just match when rotating at the reference speed. In other words, a certain time is required until the counter counts up. However, the higher the rotation speed of the motor, the higher the frequency of the FG pulse and the shorter the period. Therefore, the period of the trigger pulse responding to the FG pulse is also shortened, and the period from the input of the previous trigger pulse to the input of the next trigger pulse is also shorter than when rotating at the reference speed. . Therefore, the high-speed detection circuit detects that the motor is in the high-speed rotation state, for example, if the counter has not yet counted up when the trigger pulse is input, that is, if it is still in the counting operation.

When the high-speed detection circuit detects the high-speed rotation state, only the fast signal output from the discrimination output circuit at that time is output, and no slow signal is output.

In other words, in the high-speed rotation state, only the fast signal is output regardless of the output of the discrimination circuit, and the motor eventually reaches the rated speed. At this time, when the speed nears the rated speed, the reference clock is counted by the fast signal or the slow signal output from the discrimination output circuit, and the output of the lock detection circuit determines whether or not the lock state is reached according to whether or not the set count value is reached. By properly outputting the fast signal and the slow signal output from the discrimination circuit, the motor converges to the rated speed.

Embodiment Hereinafter, a motor control circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.
Is 1/2 frequency divider, 12 is trigger pulse generator, 16 is RS-FF, 1
7, 18 are NAND gates, 21 is a counter, 24 is a discrete output circuit, 25 is a high-speed detection circuit, 30 is a NOR gate, 35 is a lock detection circuit, 60 is RS-FF, 61 and 62 are NAND gates, 65 is Output circuit. The 1/2 frequency divider 1 receives an FG pulse output according to the rotation of a DC motor (not shown),
The frequency divider 10 divides the frequency of the FG pulse and outputs a non-inverted output and an inverted output of the 1 / 2FG signal. Further, a trigger pulse is output to the trigger pulse generator 12 in response to the non-inverted output of the 1 / 2FG signal.

The 1/2 frequency divider 10 and the trigger pulse generator 12 have three D flip-flops (hereinafter, "D-FF") 11, 13, and 14, as shown in FIG. And a two-terminal output inverter 15. FG pulse is divided by 1/2 frequency divider 10
And the inverted output is provided as its own data input D, and a 1 / 2FG signal is obtained. A reference clock CLK is applied to clock inputs CL of the D-FFs 13 and 14 of the trigger pulse generator 12. D
The non-inverted output Q of -FF11 is applied to the data input D of D-FF13. The non-inverted outputs Q of the D-FFs 13 and 14 are commonly connected to the input terminal of the inverter 15. The inverted output of D-FF13 is
It is provided to the data input D of D-FF14.

Accordingly, the output of the inverter 15 is output every time the 1 / 2FG signal rises, and becomes a trigger pulse as shown in FIGS. 3 (a) to 3 (d).

The trigger pulse is supplied to one input of the NAND gate 17 constituting the RS-FF 16 and the high-speed detection circuit 25. NAND gate 17
Is connected to the output of the NAND gate 18, and the output of the NAND gate 17 is connected to one input of the NAND gate 18. The other input of the NAND gate 18 is connected to a reset pulse from the counter 21, that is, an output terminal of a count-up signal. Therefore, the trigger pulse causes the NAND gate 18
, The inverted output of RS-FF16 goes high, the counter 21 is reset, and the counter 21 starts counting using the reference clock CLK (FIG. 2) as a count input.

In the circuit diagram of FIG. 2, this RS-FF16 is configured.
The NAND gates 17 and 18 are constituted by three-terminal output inverters 19 and 20.

The counter 21 is a counter whose count value is set to 2 ¹¹ = 2048. The counter 21, as shown in FIG.
It is configured by cascade connection of 11 D-FFs 22a to 22k.
The reference clock CLK is applied to the clock input CL of the first stage D-FF 22a, and the non-inverted output Q of this D-FF 22a
Is given to the clock input of the next stage D-FF,
The non-inverted output Q of the FF is supplied to the clock input of the third stage D-FF, and the non-inverted output Q is sequentially input to the clock in the same manner.
Connect to CL. The count-up signal from the counter 21 is supplied to the reset input of the counter 21 as a reset pulse shown in FIG.

Further, the output of the aforementioned RS-FF16, that is, the counter reset signal and its inverted signal, the output of the 1/2 frequency divider 10,
That is, the 1 / 2FG signal and its inverted signal are supplied to the discrimination output circuit 24. By connecting each output in common, it is configured as a wired type.

In the discrete output circuit 24, a counter reset signal,
A 1 / 2FG signal outputs a fast signal F or a slow signal S according to their inverted signals. When both the counter reset signal and the 1 / 2FG signal are at the high level, the slow signal S is output. When both the counter reset signal and the 1 / 2FG signal are at low level, the fast signal F is output. Further, when the counter reset signal and the 1 / 2FG signal are at the low level and the high level or vice versa, neither the fast signal F nor the slow signal S is output from the discrimination output circuit 24.

The fast signal is output when the motor is rotating at a rotation speed equal to or higher than the reference speed, and acts as a deceleration signal.
On the other hand, the slow signal is output when the motor is rotating below the reference speed, and acts as an acceleration signal. Therefore, the first signal and the slow signal can be controlled so as to converge the rotation speed to the reference or rated speed by controlling the voltage applied to the motor and the like.

The high-speed detection circuit 25, as shown in FIG.
FFs 26 and 27 and an inverter 28 are provided. A trigger pulse generator is connected to the clock input CL of D-FF26.
A trigger pulse from 12 is given, and an inverted output of the counter reset signal is given to data input D from RS-FF16. The non-inverted outputs Q of the D-FFs 26 and 27 are commonly connected to the input terminal of the inverter 28. The inverted output of D-FF26 is
It is provided to the data input D of D-FF27. Therefore, a high-speed detection output is output only when a trigger pulse is input when the counter reset signal is at a low level. Therefore,
This is a circuit for detecting that the motor (not shown) is rotating at a rotation speed twice or more the reference speed.

The NOR gate 30 in FIG. 1 has a wired configuration by connecting the output of the fast signal F and the output of the slow signal S from the discrete output circuit 24 in common via inverters 31 and 32 in FIG. It is configured as an input of the inverter 33.

As shown in FIG. 2, the lock detection circuit 35 supplies the output of the fast signal F and the output of the slow signal S from the discrete output circuit 24 to the NOR gate 30, and the output from the NOR gate 30 is six D signals. FFs 36a to 36f are provided to the reset inputs R of the D-FFs 36a to 36f of the counter 80 constituted by cascade connection, and two D-FFs 45, 46 and inverters 47, 4
The trigger pulse generation circuit 85 having the configuration of 8 or 49 is provided. This is a counter in which the count value ^{26 of the} counter 80 is set to 64. The count-up output of the counter 80 is provided to the inverter 38 of the RS-FF 81 via the inverter 37. On the other hand, the inverter 39 of the RS-FF 81 is obtained from the NOR gate 30 via the inverter 34. The reset signal output of the RS-FF 81, that is, the output of the inverter 38, outputs a low output if the output width of the fast signal F or the slow signal S from the discrete output circuit 24 is shorter than the set width of the counter 81. At this time, the width
It is determined by 21 and the count value of the counter 81. Therefore, the output becomes low when the reference is ± 64/2048 = ± 3.125% or less.

Further, the reset signal output of the RS-FF81 is provided to a trigger pulse generating circuit 84 having a configuration of two D-FFs 40 and 41 and an inverter 42, and this output is further provided to an input of the inverter 43 of the RS-FF82. . One inverter 44
The inverter 47 included in the trigger pulse generation circuit 85
Provides a pulse corresponding to the rise of the fast signal F or the slow signal S.

RS-FF82 reset signal output and trigger pulse generation circuit
A pulse output corresponding to the fall of the fast signal F or the slow signal S is commonly connected from an inverter 49 included in 85 and given to the inverter 51. In addition, the inverter 4
The outputs of 9 and 51 are commonly connected and applied to the inverter 50.

Further, the output of the inverter 50 is given to the input of the inverter 52 of the RS-FF 83, and the output of the inverter 51 is given to the input of the inverter 53. Therefore, the output width of the fast signal F or the slow signal S from the discrete output circuit 24 is ± 3.12 of the reference in the set signal output of the RS-FF83.
If it is within 5%, a high level is output as the locked state. Further, this signal is applied to a trigger pulse generating circuit 86 having a configuration of two D-FFs 54 and 55 and an inverter 56. Therefore, the lock detection output is output only when the lock state is set. Next, a high-speed detection output is given to the NAND gate 61 as a set input of the RS-FF 60, and a lock detection output is given to the NAND gate 62 as a reset input,
Output control signals include reset signal output, NAND
Obtained from gate 62. At this time, the output control signal is at a high level when in the locked state, and is at a low level when in the high-speed state, that is, when it is twice or more the reference rotational speed.

Further, the first signal F is output from the discrete output circuit 24.
And the slow signal S is supplied to the output control circuit 65. The output control circuit 65 is supplied with a low level by the above-described output control signal if the state is a high speed state,
The FF is forcibly set to the high level, the slow signal SS is forcibly set to the low level, and only the deceleration signal acts, so that the motor is decelerated. When the motor reaches 3.125% of the reference speed, the output control signal goes high and the fast signal
FF becomes the same as the fast signal F outputted from the discrimination output circuit 24, and the slow signal SS becomes the same as the slow signal S outputted from the discrimination output circuit 24, so that the rotation speed converges to the reference or rated speed. Control.

In the circuit diagram of FIG. 2, the NAND gates 61 and 62 constituting the RS-FF 60 are constituted by inverters 63 and 64, respectively. The output control circuit 65 is a gate circuit configured by six inverters 66 to 71.

In the operation, first, a case where a DC motor (not shown) is rotating at a reference speed or less will be described with reference to FIG. When the frequency of the FG pulse when the reference speed f, the frequency of the FG pulses being output at that time and f _FG, in in such a low speed state and f _FG <f.
At this time, after the counter 21 is reset by the trigger pulse, the counter 21 waits for “204
8 ”. That is, at low speed, F
Since the frequency f _{FG of the} G pulse becomes smaller and the period of the trigger pulse corresponding thereto becomes longer, the counter 21 becomes 1 /
It counts up before the fall of 2FG signal. Therefore, in the low-speed rotation state shown in FIG.
The counter reset signal output from FF16 is
21 is at the low level during the period from the reset by the trigger pulse until counting up, and remains at the high level during the remaining period. Accordingly, there is a period during which both the 1 / 2FG signal and the counter reset signal are at the high level, and the discrimination output circuit 24 outputs the slow signal S.

Since there is no period during which both the 1 / 2FG signal and the counter reset signal are at low level, the first signal F
Is not output, and the output control signal is initially set to a high level so that the output control circuit 65
Similarly, the slow signal SS = S is output and the fast signal FF = F is not output.

Next, an operation when the motor is rotating at the reference speed will be described with reference to FIG.

When rotating at the reference speed, the frequency f _{FG of the} FG pulse output at that time matches the frequency f of the FG pulse at the reference speed. Therefore, the falling timing of the 1 / 2FG signal coincides with the count-up timing of the counter 21. Therefore, in the reference or rated speed state shown in FIG. 3 (b), the 1 / 2FG signal and the counter reset signal have high and low levels inverted from each other. Accordingly, there is no period during which both the 1 / 2FG signal and the counter reset signal are at the high level or the low level, and neither the slow signal S nor the fast signal F is output from the discrete output circuit 24.

The output control signal is determined by the lock detection output a.
Since the signal is at the high level, the fast signal FF = F and the slow signal SS = S of the discrimination output circuit 24 and the output control circuit 65 are not output.

Next, with reference to FIG. 3 (c), an operation when the motor is rotating faster than the reference speed and slower than twice the reference speed will be described. At this time, the frequency f _FG of the output FG pulse is
For the frequency f of the G pulse, f <f _FG <2f. When the speed is faster than the reference speed, the period of the FG pulse becomes shorter. Therefore, the counter 21 has a falling edge of 1 / 2FG before counting up “2048”.

Accordingly, as shown in FIG. 3C, a cycle occurs in which both the 1 / 2FG signal and the counter reset signal are at low level, and the fast signal F is output from the discrete output circuit 24. At this time, since there is no period in which both the 1 / 2FG signal and the counter reset signal are at the high level, the slow signal S is not output from the discrimination output circuit 24.

Since the output control signal is at a high level, the output control circuit 65 similarly outputs the fast signal FF and does not output the slow signal SS.

Finally, with reference to FIG. 3 (d), an operation when the motor is rotating at a rotation speed twice or more the reference speed will be described. The frequency f _{FG of the} FG pulse output at this time
Is greater than 2f. Therefore, the cycle of the trigger pulse is further shortened. On the other hand, in such a high-speed state, as described above, the fast signal F and the slow signal S are alternately output from the discrete output circuit 24.
When the high-speed detection output from the high-speed detection circuit 25 is output from the high-speed detection circuit 25, the output control signal becomes low level. Therefore, the fast signal FF from the output control circuit 65 becomes high level, and the slow signal SS becomes low level and is not output. For this reason,
When the rotation speed of the motor is more than the reference or twice or more,
For example, even when the power is tripled, the fast signal FF is output from the output control circuit 65, so that the "double speed lock" unlike the related art does not occur.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram showing a second embodiment of the present invention. In the figure, 10 is a 1/2 frequency divider, 12 is a trigger pulse generator, 16, 60, and 90 are RS-FFs, 24 is a discrete output circuit, 25 is a high-speed detection circuit, 35 is a lock detection circuit, 65 Is an output control circuit, which has the same configuration as that of FIG.

The difference from the configuration of FIG. 1 is that a first trigger pulse responding to the rising edge of the 1 / 2FG signal and a second trigger pulse responding to the falling edge are used to correspond to the first counter 21 and the second counter, respectively. Count 93, this first
And second counter reset signal discrete output circuit
24, a fast signal F or a slow signal S is output.

With the above configuration, when the discrimination output circuit 24 is at a high level based on the first and second counter reset signals, the slow signal S is output. Also, the first
When both the reset signal and the second counter reset signal are at the low level, the fast signal F is output. Further, when the first and second counter reset signals are low level and high level, or vice versa, the discrete output circuit
From 24, neither the fast signal F nor the slow signal S is output.

The configurations and operations of the high-speed detection circuit 25, the lock detection circuit 35, and the output control circuit 65 are the same as in the first embodiment, and a description thereof will be omitted.

Further, in the above-described embodiment, the double speed detection circuit is used as an example of the high speed detection circuit by using the reset signal of the counter in order to avoid “double speed lock”.

However, the motor speed detected by the high-speed detection circuit may be in a range from the reference or the rated speed to 1 to 2 times, and may be set to an arbitrary count value until the counter reaches the set count value.

Also, ± 3.12 as an example of the lock width of the lock detection circuit
5%. However, the lock width of the lock detection circuit may be set in a range smaller than the detection speed of the above-described high-speed detection circuit.

Furthermore, although the present invention has been described as being applied to a control circuit for a DC motor, it goes without saying that the present invention can be similarly applied to an AC motor.

As described above, the motor control circuit of the present invention detects that the motor is rotating at a reference speed or more when the next 1 / 2FG signal is input while the counter is operating.
When a trigger pulse is input in response to the rising edge of the 1 / 2FG signal, the high-speed detection circuit that determines whether the motor is rotating at high speed based on whether the counter is operating and the fact that the motor is rotating at the reference speed To detect, a lock detection circuit that counts a reference clock by a fast signal or a slow signal and determines that a lock state has been reached when a set count value is reached, and outputs only a fast signal with a detection output of the high-speed detection circuit, By outputting a fast signal or a slow signal at the detection output of the lock detection circuit, locking in a multiple rotation state of twice or three times or more of the reference speed does not occur. Without control, stable speed control at reference or rated speed is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a specific circuit diagram of the block diagram shown in FIG. 1, and FIG. 3 (a) shows a motor rotating below a reference speed. FIG. 3B is a timing chart showing the state when the motor is rotating at the reference speed, and FIG.
FIG. 3C is a timing chart showing a state where the motor is rotating in a range from the reference speed to twice the reference speed, and FIG. 3D is a diagram in which the motor rotates from the reference speed to twice or more the reference speed. FIG. 4 is a block diagram of the second embodiment, FIG. 5 is a block diagram of a conventional motor control circuit, and FIGS. 6 (a) and (b) are diagrams of a conventional motor control circuit. FIG. 4 is a timing chart illustrating states when the motor is rotating at a reference speed and twice the reference speed in the motor control circuit. 10… 1/2 frequency divider, 2, 12… Trigger pulse generator,
3, 16, 60, 90 ... RS-FF, 4, 21, 93 ... counter,
5, 24: Discrete output circuit, 25: High-speed detection circuit,
35 …… Lock detection circuit, 65 …… Output control circuit, 17, 18,
61, 62, 91, 92 ... NAND gate, 30 ... NOR gate.

Claims (2)

(57) [Claims] 1. A frequency divider for dividing an FG pulse of a frequency generator output according to rotation of a motor, and an FG pulse divided signal obtained by dividing the FG pulse by the divider. A trigger pulse generator for generating a trigger pulse with a reference clock, starting counting of the reference clock from the time of generation of the trigger pulse, and outputting a count-up signal when the count reaches a set count value; A counter that is reset when an up signal is output; a period of one cycle of the trigger pulse; and a setting until the counter starts counting the reference clock and the count value of the counter reaches a set count value of the counter. If the time of one cycle of the trigger pulse is shorter than the set count time compared with the count time, the rotation of the motor is started. The motor outputs a fast signal indicating that the number of rotations is faster than the set number of revolutions, and when the time of one cycle of the trigger pulse is longer than the set count time, the motor has rotated slower than the set number of revolutions. A discrimination output circuit that outputs a slow signal indicating that the counter is counting the reference clock when the trigger pulse is input, and a high-speed rotation state if the count-up signal has not been output yet. A high-speed detection circuit that outputs a high-speed detection output by judging that: a NOR gate in which each signal line for transmitting the fast signal and the slow signal is connected to an input terminal; and an output of the NOR gate is input. , A lock detection circuit counter that counts the time at which the first signal or the slow signal is output with a reference clock. The counter value is compared with the set count of the lock detection circuit counter.If the counter value of the lock detection circuit counter does not reach the set count of the lock detection circuit counter, the motor is locked in the rotation speed locked state. A lock detection circuit that outputs a lock detection output indicating that there is no high-speed detection output, and when there is no lock detection output, only the same signal as the slow signal of the discrete output circuit is output; When there is no detection output and there is the lock detection output, no signal is output as in the case where neither the fast signal nor the slow signal of the discrete output circuit is output, and the high speed detection output is present, When there is no lock detection output, only the same signal as the fast signal of the discrete output circuit is output, Detection output is there, when there is also the lock detection output is a motor control circuit, characterized in that only the same signal as the first signal of the discriminator output circuit and an output control circuit which is to be outputted. 2. A frequency divider that divides an FG pulse of a frequency generator output according to rotation of a motor, and an FG pulse divided signal obtained by dividing the FG pulse by the divider. A trigger pulse generator for generating a first trigger pulse responsive to a rising edge of the FG pulse divided signal and a second trigger pulse responsive to a falling edge of the FG pulse divided signal, using a reference clock; and generating the first trigger pulse. A first counter that starts counting the reference clock from time, outputs a first reset pulse when the count reaches a set count value, and is reset when the first reset pulse is output; and the second trigger pulse. Starts the counting of the reference clock from the occurrence of, and outputs a second reset pulse when the count reaches a set count value. A second counter to be reset; and when the first counter reset signal of the first counter and the second counter reset signal of the second counter are both at a high level, the rotation speed of the motor has rotated slower than a set rotation speed. When the first counter reset signal of the first counter and the second counter reset signal of the second counter are both at a low level, the rotation speed of the motor is faster than the set rotation speed. When the first counter reset signal of the first counter is at a high level and the second counter reset signal of the second counter is at a low level, the slow signal also outputs the fast signal. No signal is output, and the first counter reset signal of the first counter is at a low level and the second counter of the second counter is When the 2 counter reset signal is at a high level, a discrete output circuit that does not output either the slow signal or the fast signal, and the first counter counts the reference clock when the first trigger pulse is input. If the first reset pulse has not yet been output, the high speed detection circuit that determines that the motor is in the high speed rotation state and outputs the high speed detection output, and the signal lines through which the fast signal and the slow signal are transmitted are input. A NOR gate connected to a terminal, a counter value of a counter for a lock detection circuit that receives an output of the NOR gate and counts a time when the fast signal or the slow signal is output by a reference clock, and The count value of the lock detection circuit counter is compared with the set count of the circuit A lock detection circuit that outputs a lock detection output indicating that the motor is in a rotational speed locked state when the set count of the lock detection circuit counter has not been reached, and when there is no high-speed detection output and there is no lock detection output. Outputs only the same signal as the slow signal of the discrete output circuit, and outputs the fast signal and the slow signal of the discrete output circuit when there is no high-speed detection output and there is the lock detection output. No signal is output in the same manner as when the signal is not detected, and when the high-speed detection output is present and the lock detection output is not present, only the same signal as the fast signal of the discrete output circuit is output, and the high-speed detection is performed. When the output is present and the lock detection output is also present, only the same signal as the fast signal of the discrete output circuit is output. Motor control circuit, characterized in that an output control circuit to so that.