JP2912512B2 - Amplifier phase compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase compensation circuit for improving a phase characteristic in an amplifier circuit.

[0002]

2. Description of the Related Art A conventionally known two-stage connected amplifier circuit uses a phase compensation circuit as shown in FIG. 2 to improve the phase characteristics.

That is, in the circuit of FIG. 2, V _OUT / V
_In order to improve the phase characteristic of _IN , a fixed resistor R _C and a capacitance C _C are connected in series, so that the zero point Z in the phase characteristic of V _OUT / V _IN

[0004]

(Equation 1)

Here, g _m1 produces a zero point which is approximately expressed as the transconductance of the transistor M ₁ , and the pole P formed by the output terminal capacitance C _L and g _m1 .

[0006]

(Equation 2)

The ratio was set appropriately.

[0008]

[SUMMARY OF THE INVENTION However, if the transfer conductance g _m1 of the transistor M ₁ shown in FIG. 2 is varied (e.g., due to the output current I _L flowing through the transistor M ₁ varies g _m1 Fluctuates)
Has a drawback in that it becomes impossible to maintain the above-mentioned zero point and pole values in a predetermined proportional relationship, so that it becomes difficult to improve the phase characteristics.

[0009] Therefore an object of the present invention In view of the above points, it is possible to improve the phase characteristics of the irrespective V _OUT / V _IN to fluctuation of the output current I _L, to provide a phase compensation circuit of the amplifier It is in.

[0010]

According to the present invention, there is provided an amplifier comprising two amplification stages.
A resistor R _C is provided between the output of the first amplification stage and the output of the second amplification stage.
And a capacitor C _C connected in series, and performing phase compensation of input / output characteristics by the R _C and the C _C , wherein a transfer conductance g _m of a signal amplification transistor included in the second amplification stage is included. Means for detecting the value of R _c using the detected value to control the zero point of the phase characteristic using the value of R _c as a parameter so that the phase characteristic fluctuating depending on the change in g _m. And means for tracking to the pole of the amplifier, thereby facilitating the phase compensation of the amplifier.

[0011]

According to the above construction of the present invention, the transfer conductance g _m of the second-stage signal amplifying transistor (M _{1 in the} embodiment) is detected, and the value of g _m is controlled by controlling the value of the resistor R _C. When allowed to track the value of 1 / R _C, g _m
And the zero of the phase characteristic using 1 / _RC as a parameter is placed in a predetermined proportional relationship.

As a result, the output current (in the embodiment, I
G _m (g _{m1 in the} embodiment) due to fluctuation of _L )
, The value of the zero can be placed in a proportional relationship with respect to the value of the pole depending on g _m ,
Phase compensation is facilitated.

[0013]

Embodiments of the present invention will be described below in detail.

Embodiment 1 FIG. 1 shows a phase compensation circuit according to a first embodiment of the present invention. In the figure, M ₁ is a amplifying MOS transistor for amplifying the output voltage of the amplifier stage A of the first stage until V _OUT (first MOS transistor). I _B is a bias current source and supplies a constant current to the first MOS transistor M _1.

Further, the same gate-source voltage V _{GS1 as} that of the first MOS transistor M ₁ is applied to the second MOS transistor M ₂ , and outputs a current I ₁ .

Third and sixth MOS transistors M
_3, the current mirror circuit formed by the M ₆ (mirror ratio 1: 1), also flows the same amount of current as the I ₁ to the MOS transistors M _4, M ₅ of the fourth and fifth. Therefore, the MOS transistors M ₂ , M ₄ , M ₅
Of the same size, the MOS transistor M
A voltage of magnitude V _GS1 is generated between the source and the drain of ₄ and M ₅ .

Therefore, a voltage of the same magnitude as V _GS1 is applied between the gate and the source of the MOS transistor M _C , so that the resistance R _C1 between the source and the drain of the MOS transistor M _C becomes

[0018]

(Equation 3)

## EQU1 ##

[0020] Here, K ': gain factor of the MOS transistors W _C and L _C: MOS transistor M _C each size V _T of: whereas the threshold voltage of the MOS transistor, the first MOS transistor M ₁ transconductance g _m1 Is

[0021]

(Equation 4)

Therefore, the zero point Z generated in the phase characteristic in the process from V _IN to V _OUT is:

[0023]

(Equation 5)

## EQU1 ## For the pole P, using the output terminal capacitance C _L and the above g _m1 ,

[0025]

(Equation 6)

Approximately expressed as Then, the relationship between the zero point Z and the pole P is

[0027]

(Equation 7)

As is clear from the above, a proportional relationship is obtained based on the constant of the above equation (7).

[0029] It is important to note is that the value of the P / Z is independent of the output current I _L. That is, by the magnitude of the output current I _L is varied, the first MO
Of the S transistor M ₁

[0030]

[Outside 1]

Even if the values fluctuate, the phase characteristics can be improved by selecting appropriate values for the transistor sizes W ₁ , L ₁ , W _C , L _C and the capacitances C _L , C _C.

Embodiment 2 FIG. 3 shows a phase compensation circuit according to a second embodiment of the present invention. This figure shows that the P-type MOS transistor shown in FIG.
Type MOS transistor and power supply V _DD
And _VSS are interchanged, and can have the same function as that of FIG.

Embodiment 3 FIG. 4 shows a phase compensation circuit according to a third embodiment of the present invention. In this figure, the same function as described above is achieved by controlling the resistance value of the variable resistor R _VC using a separate g _m detection circuit GDET different from the conventional one.

Embodiment 4 FIG. 5 shows a phase compensation circuit according to a fourth embodiment of the present invention. The circuit shown in the figure is for compensating the phase of the class AB amplifier, and A in the figure represents the first stage amplifier,
LS is a level shift circuit, GS _p and GS _n are g _m
4 shows a detection sensor.

As shown in FIG. 6, the level shift circuit LS has a DC level adjusting circuit for adjusting the DC output voltage of the first amplifier stage to the DC input voltage of the transistor _Mn1 of the second stage. It is.

In this embodiment, the zero point and the pole on the phase characteristic are respectively

[0037]

(Equation 8)

[0038]

(Equation 9)

## EQU2 ## Where each parameter is
It is as shown below.

[0040]

(Equation 10)

[0041]

[Equation 11]

[0042]

(Equation 12)

[0043]

(Equation 13)

In this embodiment, the transistors M _p1 , M _n1 ,
By adjusting the sizes of M _pc and M _nc and the values of C _C and C _L , Z and P can be placed in a proportional relationship.

In particular, regarding the P-type transistors M _p1 and M _pc

[0046]

[Equation 14]

Further, regarding the N-type transistors M _n1 and M _nc

[0048]

(Equation 15)

[0049]

(Equation 16)

[0050]

[0051]

[Equation 17]

Can be expressed as

[0053]

(Equation 18)

The constant can be made proportional by the following constant:

[0055]

According to as discussed above the present invention, even in variation of a g _m due to the output current varies with respect to the value of the pole is dependent on the g _m, the zero point value Can be placed in a proportional relation, so that even if the output current changes, appropriate phase compensation can always be performed.

[Brief description of the drawings]

FIG. 1 is a phase compensation circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventionally known phase compensation circuit of an amplifier.

FIG. 3 is a phase compensation circuit diagram according to a second embodiment of the present invention.

FIG. 4 is a phase compensation circuit diagram according to a third embodiment of the present invention.

FIG. 5 is a phase compensation circuit according to a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration example of a level shift circuit illustrated in FIG. 5;

[Explanation of symbols]

M ₁ ~M _6, M _C MOS transistor I _L output current I _B the bias current V _IN Input voltage V _OUT Output Voltage

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03F 1/34 H03F 1/32

Claims (1)

(57) [Claims] 1. An amplifier comprising two amplification stages,
A resistor R _C is provided between the output of the first amplification stage and the output of the second amplification stage.
And a capacitor C _C connected in series, and performing phase compensation of input / output characteristics by the R _C and the C _C , wherein a transfer conductance g _m in a signal amplification transistor included in the second amplification stage is provided. By controlling the value of R _C using the detected value,
The zero point of the phase characteristics that the value of R _C and parameters, the phase compensation circuit of the amplifier, characterized by comprising a means for tracking the poles of the phase characteristic which varies depending on the change of the g _m.