JPH08307224A - Operational amplifier circuit - Google Patents

Abstract

PURPOSE: To provide an operational amplifier circuit in which an output stage is in push-pull operation and a stability function of an output stage current is provided. CONSTITUTION: A 1st differential amplifier circuit 1 having n-channel differential MOS TR pairs Q1, Q3 and a 2nd differential amplifier circuit 2 having p-channel differential MOS TR pairs Q2, Q4 are provided to an input stage. A complementary output circuit 5 is configured by a p-channel MOS TR Q15 and an n- channel MOS TR Q16 whose gates are controlled by an output of the circuits 1, 2. A current of the output stage MOS TRs Q15, Q16 is detected respectively by 1st and 2nd current detection circuits 6, 7. A reference current source circuit 8 providing a common reference current to current mirror circuits 3, 4 providing an active load current of the differential amplifier circuits 1, 2 is controlled by the detected current to apply negative feedback to suppress fluctuation in a through-current of the complementary output circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier circuit having a complementary output circuit that performs a push-pull operation by a p-channel output stage MOS transistor and an n-channel output stage MOS transistor.

[0002]

2. Description of the Related Art In many cases, an operational amplifier circuit based on a CMOS process has a CMO at the input stage, as shown in FIG.
An S differential circuit is used, and the output stage is a single end type having a constant current load. This kind of operational amplifier circuit, if the load connected to the output end is a low impedance load,
There is a problem with the drive capacity. This is because the supply current is limited by the constant current load. In order to provide a sufficient driving capability for a low impedance load, it is necessary to make the impedance of the constant current load sufficiently small so that a large current can be supplied, and accordingly, the output stage MOS transistor also has a sufficiently large current capacity. It is necessary to do something.

On the other hand, as an operational amplifier circuit advantageous for driving a low impedance load, a circuit in which p-channel and n-channel are reversed from the operational amplifier circuit configuration of FIG. 3 is prepared, and as shown in FIG. It is conceivable to arrange them on the power supply VDD side and the ground VSS side to form a complementary circuit. With such a circuit, it is possible to drive the load by the push-pull operation of the p-channel MOS transistor and the n-channel MOS transistor in the output stage.

[0004]

However, in the complementary circuit in which only two single-ended operational amplifier circuits are simply combined as shown in FIG. 4, a p-channel MO of the output stage is used.
It does not have the function of stabilizing the current of the S transistor and the n-channel MOS transistor. Because p channel M
This is because, under a bias condition in which the OS transistor and the n-channel MOS transistor are turned on at the same time and the through current flows, the output potential does not change even if the through current increases, and there is no feedback function for suppressing the increase of the through current. Therefore, there arises a problem that the through-current increases to cause destruction. On the contrary, when the currents of the output stage MOS transistors decrease at the same time, the output stage is cut off.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide an operational amplifier circuit having a push-pull operation in the output stage and having a function of stabilizing the output stage current.

[0006]

An operational amplifier circuit according to the present invention includes a first input stage differential amplifier circuit having an active load formed by an n-channel differential MOS transistor pair and a p-channel first current mirror circuit. , P channel differential M
A second input stage differential amplifier circuit connected in parallel with the first input stage differential amplifier circuit having an active load by an OS transistor pair and an n-channel second current mirror circuit; and the first input stage differential circuit The gate is controlled by the output of the amplifier circuit, the gate is controlled by the output of the p-channel output stage MOS transistor whose drain is connected to the signal output terminal, and the output of the second input stage differential amplifier circuit, and the drain is the signal output terminal. N-channel output stage MO connected to
Complementary output circuit having S-transistor, and p-channel current detection MOS to which the same gate-source bias as the p-channel output stage MOS transistor is applied
A first current detection circuit that uses a transistor to obtain a detection current proportional to the current of the p-channel output-stage MOS transistor; and an n-channel that is given the same gate-source bias as the n-channel output-stage MOS transistor. A second current detection circuit that obtains a detection current proportional to the current of the n-channel output-stage MOS transistor using a current detection MOS transistor, and is controlled by the outputs of the first and second current detection circuits, respectively. Current source M
A reference current source circuit that has an OS transistor and obtains a reference current proportional to the sum of the detection currents of the first and second current detection circuits as a common reference current of the first and second current mirror circuits. It is characterized by that.

In the present invention, preferably, in the first current detecting circuit, the ratio of the channel width of the p-channel current detecting MOS transistor to the channel length is the channel width and the channel length of the p-channel output stage MOS transistor. Is set to 1 / N (where N> 1) to obtain a detection current of 1 / N of the collector current of the p-channel output stage MOS transistor, and the second current detection circuit , The ratio of the channel width and the channel length of the n-channel current detection MOS transistor is set to 1 / N of the ratio of the channel width and the channel length of the n-channel output stage MOS transistor, and the n-channel output stage M
It is characterized in that a detection current of 1 / N of the collector current of the OS transistor is obtained.

[0008]

In the operational amplifier circuit according to the present invention, the signal input stage is made a complementary circuit by the first and second input stage differential amplifier circuits, and at the same time, the output stage is also a p-channel output stage MOS transistor and an n-channel output stage MOS transistor. It is a complementary circuit. The first and second input stage differential amplifier circuits are provided with active loads by the first and second current mirror circuits, respectively. In order to stabilize the current in the output stage, the p-channel MOS transistor
The first and second current mirrors are provided with first and second current detection circuits for detecting the current of the channel MOS transistor, and a reference current source circuit that obtains a reference current proportional to the sum of the detected currents. The circuit is configured as a common reference current source circuit.

As a result, in the operational amplifier circuit according to the present invention, when the shoot-through current in the output stage is about to change, the common reference current of the first and second current mirror circuits is controlled so that the shoot-through current increases, for example. If so, the reference current acts on the first and second input stage differential amplifier circuits in the direction in which the respective active loads are turned on deeper, whereby the output stage p-channel MOS transistor and the n-channel MOS transistor are both turned off. The gate is biased. That is, the feedback for suppressing the increase of the output stage through current is involved, the output current is stabilized, and the breakdown due to the runaway or the like is surely prevented. The difference between the output currents is not negatively fed back by the above-described current detection and reference current control, so that the amplification factor of the operational amplifier circuit is not affected.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an operational amplifier circuit according to an embodiment of the present invention. The input stage is provided with a constant current source I2 as a common source, and a first difference using an n-channel differential MOS transistor pair Q1 and Q3 whose gates serve as an inverting input terminal IN2 and a non-inverting input terminal IN1. Dynamic amplification circuit 1
Similarly, a constant current source I1 is provided in the common source, and each gate has an inverting input terminal IN2 and a non-inverting input terminal I1.
N channel p-channel differential MOS transistor pair Q
The second differential amplifier circuit 2 using Q2 and Q2 is connected in parallel and arranged.

On the drain side of the MOS transistor Q3 which is the output terminal N1 of the first differential amplifier circuit 1, the MOS transistor Q5 of the first current mirror circuit 3 constituted by p-channel MOS transistors Q7 and Q5 is active. It is inserted as a load. Similarly, on the drain side of the MOS transistor Q4 which is the output terminal N2 of the second differential amplifier circuit 2, n-channel MOS transistors Q8 and Q6 are provided.
MOS of the second current mirror circuit 4 constituted by
Transistor Q6 is inserted as an active load.

A p-channel output-stage MOS transistor Q15 whose gate is controlled by the output terminal N1 of the first differential amplifier circuit 1 and n whose gate is controlled by the output terminal N2 of the second differential amplifier circuit 2. The output stage MOS transistor Q16 of the channel is arranged on the power supply VDD side and the ground VSS side, respectively, and the drains are commonly connected to the signal output terminal OUT to form the complementary output circuit 5.

A common reference current source circuit 8 is provided for the first and second current mirror circuits 3 and 4. The reference current source circuit 8 has an n-channel MOS transistor Q9 on the side of the first current mirror circuit 3 whose conductivity is controlled according to the amount of current of the p-channel output stage MOS transistor Q15, and an n-channel output stage. MOS transistor Q1
P-channel MOS transistor Q1 on the side of the second current mirror circuit 4 whose conductivity is controlled according to the amount of current
0 and resistors R1 and R2 inserted in series with them.

First and second current detection circuits 6 and 7 are provided to detect the currents of the output stage MOS transistors Q15 and Q16 of the complementary output circuit 5. In the first current detection circuit 6, the gate is driven in common with the output stage MOS transistor Q15, and the source is the power supply VDD.
And a p-channel current detection MOS transistor Q11 which is connected to the same and is supplied with the same gate-source bias as the MOS transistor Q15. Similarly, the second current detection circuit 7 has an n-channel current detection MOS transistor Q12 to which the same gate-source bias as the output stage MOS transistor Q16 is applied.

The ratio of the channel width W11 to the channel length L11 of the current detecting MOS transistor Q11 is such that the following equation 1 is satisfied with respect to the ratio of the channel width W15 to the channel length L15 of the output stage MOS transistor Q15. Is set. However, N is a number larger than 1.

[0016]

[Equation 1] W11 / L11 = (W15 / L15) / N

Similarly, a current detection MOS transistor Q
The device dimension is set so that the ratio of the channel width W12 and the channel length L12 of 12 satisfies the following formula 2 with respect to the ratio of the channel width W16 and the channel length L16 of the output stage MOS transistor Q16.

[0018]

[Equation 2] W12 / L12 = (W16 / L16) / N

One current detection MOS transistor Q1
The drain of 1 is connected to the ground VSS via the resistor R3 serving as a load and the p-channel MOS transistor Q13. Similarly, the drain of the other current detection MOS transistor Q12 is also connected to the power supply VDD through the resistor R4 and the n-channel MOS transistor Q14. The gates of these MOS transistors Q13 and Q14 are controlled by the potential of the intermediate potential point N3 by resistors R5 and R6 that divide the voltage between the power supply VDD and the ground VSS.

The above resistor R3 and MOS transistor Q1
3 and the resistor R4 and the MOS transistor Q14 are respectively connected to the current detecting MOS transistor Q1.
1 and Q12 are current-voltage conversion circuits for converting the detected currents into voltage values, and output nodes N4, N
5 is a common reference current source circuit 8 for the current mirror circuits 3 and 4.
Connected to the gates of the MOS transistors Q9 and Q10.

The operation of stabilizing the output current of the operational amplifier circuit configured as described above will be described below. P of the complementary output circuit 5
Channel MOS transistor Q15 and n-channel MOS
The collector currents of the transistor Q16 are the first and the first, respectively.
It is detected by the second current detection circuits 6 and 7. The ratio of the channel width and the channel length of the current detection MOS transistors Q11 and Q12 is determined by the output stage MOS transistor Q1.
5 and Q16 are set to 1 / N as described above, the output stage MOS transistor Q15,
Current detection is performed with a detection current that is 1 / N of the collector current of Q16.

The reference current from the reference current source circuit 8 is variably controlled so as to be proportional to the sum of the detection currents from the first and second current detection circuits 6 and 7, and this is controlled by the first and second current mirrors. The circuits 1 and 2 are provided by the circuits 3 and 4, respectively.
Is given as an active load current of the differential amplifier circuits 1 and 2. Therefore, for example, when the through current in the complementary output circuit 4 increases, the currents of the active load MOS transistors Q5 and Q6 in the first and second differential amplifier circuits 1 and 2 correspondingly increase. That is, the potential at one output terminal N1 increases and the potential at the other output terminal N2 decreases. As a result, the gates of both the output stage MOS transistors Q15 and Q16 are biased in the OFF direction, and negative feedback is applied in the direction of reducing the through current.

The above negative feedback operation will be described more specifically. The following assumptions are made to simplify the explanation. First R5
= R6, and VDD / 2 is obtained at the node N3. Further, R1 = R2 = R3 = R4, p-channel MOS transistors Q10 and Q13 have the same size, and n-channel MOS transistors Q9 and Q14 have the same size. Constant current sources I2 of the first and second differential amplifier circuits 1 and 2
I1 is I1 = I2.

The relationship between the voltage and current of the main parts of the first and second current detection circuits 6 and 7 and the reference current source circuit 8 is shown in FIG. When the currents detected by the first and second current detection circuits 6 and 7 are I11 and I12 as shown in the figure, these currents cause a voltage VR3 across the resistor R3 and a gate-source between the MOS transistor Q13. Voltage VT13, similarly voltage VR4 across the resistor R4, MOS transistor Q14
A voltage VT14 is generated between the gate and source of the.

Therefore, a voltage of the following expression 3 is applied between the gates of the MOS transistors Q9 and Q10 of the reference current source circuit 8.

[0026]

[Equation 3] VR3 + VT13 + VT14 + VR4

Further, the gate-source voltage of the MOS transistor Q9 of the reference current source circuit 8 is VT9, the gate-source voltage of the MOS transistor Q10 is VT10, and the resistor R.
If the voltages across R1 and R2 are VR1 and VR2, respectively,
The following equation 4 is obtained in relation to the equation 3.

[0028]

[Formula 4] VT9 + VR1 + VR2 + VT10 = VR3 + VT13 + V
T14 + VR4

From the relationship of the element dimensions described above, VT13
= VT10 and VT14 = VT9, the equation 4 is the following equation 5
Can be rewritten as

[0030]

[Equation 5] VR1 + VR2 = VR3 + VR4

When the currents of the MOS transistors Q9 and Q10 of the reference current source circuit 8 are I9 and I10, the relationship of the following Expression 6 can be obtained from Expression 5.

[0032]

[Equation 6] R1 · I9 + R2 · I10 = R3 · I11 + R4 · I12

By the way, since the currents I9 and I10 have no other branch paths, I9 = I10, and as described above, R1 =
When R2 = R3 = R4, the following Equation 7 is obtained from Equation 6.

[0034]

[Equation 7] I9 = I10 = (I10 + I12) / 2

From the above, the common reference current I9 = I10 of the first and second current mirror circuits 3 and 4 is
The value becomes proportional to the sum of the detection currents I11 and I12 by the current detection circuits 6 and 7. The detected currents I11 and I12 are proportional to the collector currents of the output-stage MOS transistors Q15 and Q16, respectively. In other words, the common reference current I9 = I10 is proportional to the through current of the output stage.

In this way, since the reference current controlled according to the through current of the complementary output circuit 5 is given as the active load current of the first and second differential amplifier circuits 1 and 2, the through current increases. In that case, the first and second differential amplifier circuits 1,
The two MOS transistors Q5 and Q6 both work in a direction to be turned on deeply, and negative feedback is applied so as to suppress the through current of the complementary output circuit 5. Since the first and second differential amplifier circuits 1 and 2 are set so that a constant current flows by the constant current sources I2 and I1, respectively, complementary output signals are generated so that a constant active load current will eventually flow through them. The through current of the circuit 5 will be controlled.

For example, if the output potential of this operational amplifier circuit is approximately the midpoint potential of the power supply VDD, the detected current is I11.
= I12. In addition, the first and second differential amplifier circuits 1 and 2
The currents IQ5 and IQ6 of the active load transistors Q5 and Q6 of the current mirror circuit 5 are respectively IQ5 = I
Since 9, IQ6 = I10 and I9 = I10, one of the transistors Q3 of each differential transistor pair is
The currents IQ3 and IQ4 of Q4 are given by the following equation 8.

[0038]

[Equation 8] IQ3 = I11 = I12 = IQ4

That is, the detected currents I11 and I12 are equal to the currents IQ3 and IQ4 of the first-stage differential amplifier circuits 1 and 2, in other words, the currents of the output-stage MOS transistors Q15 and Q16 are stable at N times these values. It has been realized.

As is readily apparent from the above description, the first and second current detection circuits 6 and 7 and the reference voltage source circuit 8
Are MOS transistors Q15 and Q of the complementary output circuit 5.
Since there is no non-feedback action with respect to the difference component of 16 currents, there is no influence on the amplification factor for the differential input signal. For example, when the potential of one input terminal IN1 rises with respect to the other input terminal IN2, the first differential amplifier circuit 1 outputs the output terminal N1.
As a result, 1 acts to turn on the output stage MOS transistor Q15, and in the second differential amplifier circuit 2, the output terminal N2 acts to turn on the output MOS transistor Q16 by lowering the potential. , The differential amplification of the output stage push-pull operation is performed such that the potential of the signal output terminal OUT rises.

[0041]

As described above, according to the present invention, the output stage is configured as a complementary circuit to detect the current in the output stage and suppress the fluctuation of the through current of the output stage in the differential amplifier circuit in the first stage. By performing such feedback, the operational amplifier circuit for push-pull operation can have a function of stabilizing the output stage current.

[Brief description of drawings]

FIG. 1 shows an operational amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the current control operation of the embodiment.

FIG. 3 shows a conventional operational amplifier circuit.

FIG. 4 shows an operational amplifier circuit provided with the circuit of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st input stage differential amplifier circuit, 2 ... 1st input stage differential amplifier circuit, 3 ... 1st current mirror circuit, 4 ... 2nd current mirror circuit, 5 ... Complementary type output circuit, 6 ... 1 current detection circuit, 7 ... 2nd current detection circuit, 8 ... reference current source circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H03K 17/687 9184-5K H03K 17/687 F 19/0948 19/094 B

Claims (2)

[Claims] 1. A first input stage differential amplifier circuit having an active load by an n-channel differential MOS transistor pair and a p-channel first current mirror circuit, a p-channel differential MOS transistor pair and an n-channel differential MOS transistor pair. A second input stage differential amplifier circuit, which has an active load by a second current mirror circuit, is connected in parallel with the first input stage differential amplifier circuit, and a gate is formed by an output of the first input stage differential amplifier circuit. An n-channel gate whose gate is controlled by a p-channel output stage MOS transistor whose drain is controlled and whose drain is connected to the signal output end, and whose output is controlled by the output of the second input stage differential amplifier circuit A complementary output circuit having an output stage MOS transistor, and the same gate-source bias as the p-channel output stage MOS transistor A first current detection circuit for obtaining a detection current proportional to the current of the p-channel output stage MOS transistor by using a given p-channel current detection MOS transistor; and a gate having the same gate as the n-channel output stage MOS transistor. A second current detection circuit that obtains a detection current proportional to the current of the n-channel output stage MOS transistor by using an n-channel current detection MOS transistor to which a source-to-source bias is applied; and the first and second currents. A current source MOS transistor controlled by the output of the detection circuit,
An operational amplifier circuit comprising: a reference current source circuit that obtains a reference current that is proportional to the sum of the currents detected by the first and second current detection circuits as a common reference current of the second current mirror circuit. 2. In the first current detection circuit, the ratio of the channel width and the channel length of the p-channel current detection MOS transistor is 1 of the ratio of the channel width and the channel length of the p-channel output stage MOS transistor. / N (however, N
> 1) to obtain a detection current of 1 / N of the collector current of the p-channel output stage MOS transistor, wherein the second current detection circuit is the n-channel current detection MOS transistor. Is set to 1 / N of the ratio of the channel width to the channel length of the n-channel output stage MOS transistor, and the ratio of 1 / N of the collector current of the n-channel output stage MOS transistor is set.
2. The operational amplifier circuit according to claim 1, wherein a detection current of N is obtained.