JP2950140B2 - MUSE decoder motion compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a band-compressed MUSE.
The present invention relates to a MUSE decoder that demodulates a signal into an original wideband high-definition television signal and reproduces the signal, and more particularly to a motion correction processing circuit in the MUSE decoder.

[0002]

2. Description of the Related Art MUSE (Multiple Sub-Nyquist Sampling) for applying a sub-Nyquist sample that goes around the original high-definition television signal in four fields as a method of band-compressing a wideband high-definition television signal to a practical level for transmission.
Encoding) method.

The MUSE system is a system developed by NHK (Japan Broadcasting Corporation), and various documents (for example, Yuichi Ninomiya, “MUSE-High-Vision Transmission System”, The Institute of Electronics, Information and Communication Engineers, December 1, 1990) ), Detailed description is omitted.

In the MUSE system, a luminance signal (“Y signal”
In order to transmit a high-definition television signal (referred to as a “baseband signal”) having a bandwidth of up to about 22 MHz with a color signal (referred to as a “C signal”) of about 22 MHz in one channel of satellite broadcasting having a bandwidth of 27 MHz, Bandwidth compression processing is performed up to a width of about 8 MHz. The MUSE decoder demodulates the band-compressed signal (hereinafter, referred to as “MUSE signal”) into an original baseband signal.

FIG. 8 is a block diagram showing a part of a conventional MUSE decoding process. The input terminal 1 is supplied with a MUSE signal. The selector 2 is a selector for interpolating a still image signal between frames, and outputs a signal (interframe interpolation signal) one frame before and a signal of the current frame by three.
Interpolation is performed by alternately switching with a 2 MHz sampling clock.

The signal to be interpolated includes the signal one frame before delayed by the two field memories 3 and 4 and the motion vector signal 11 detected by the control signal detector 10.
, The Y signal portion is subjected to motion correction processing by the motion correction processing section 5, and the output of the motion correction processing section 5 is supplied to a contact on one side of the selector 45. Further, the C signal portion is not subjected to the motion correction processing and is supplied to the other contact point of the selector 45.

The MUSE signal is a TCI (Time Compressed)
9), the selector 45 in FIG. 8 switches the C signal 49 and the Y signal 50 between the X point and the Y point. The TCI is a general term for a time division multiplexing method in which both the Y signal and the C signal in one line or only the C signal is time-compressed and multiplexed.

[0008] The motion correction processing in the MUSE decoder has been proposed, for example, in Japanese Patent Application Laid-Open No. Sho 59-221090. According to the publication, in the motion correction processing, position information obtained by adding movement information of a sample position based on a predetermined sample position relationship between adjacent frames to motion information (referred to as “motion vector”) detected on the encoder side is added to position information. Based on this, the interpolation position of the sample value to be interpolated with a delay is corrected.

According to the above-mentioned document "MUSE-HDTV transmission system" by Ninomiya, p. 120, the motion vector is detected on the encoder side, and the obtained motion vector is transmitted as a control signal. Uses 7 bits of the 32 bits of the control signal, and
The bits are assigned to the horizontal vector and the 3 bits to the vertical vector, so that a motion vector in the range of +7 to -8 clocks in the horizontal direction and +3 to -4 lines in the vertical direction (see Tables 1 and 2) is transmitted.

[0010] Further, it is described that no motion correction processing is performed on the C signal (p. 51 of the same document). For this reason,
As shown in FIG. 8, the signal for frame interpolation is switched by the selector 45 between the Y signal portion and the C signal portion.

As shown in FIG. 8, the conventional MUSE decoder has a configuration in which a motion correction processing section 5 for Y signal and a selector 45 for switching between Y signal section and C signal section are built in the field memory (broken line 6c in the figure). In many cases).

The motion correction processing for performing a motion vector correction uniformly over the entire screen is performed by increasing or decreasing the buffer amount (for example, from +3 to
−4 line correction corresponds to an increase or decrease in the buffer amount), and therefore, by memory address control (for example, controlling the offset between the write start address and the read start address of the memory corresponding to the motion vector) This can be realized by increasing or decreasing the buffer amount.

In the block indicated by the broken line 6c, the increase / decrease of the buffer amount of the Y signal must be controlled separately from the C signal in correspondence with the motion vector from the control signal detecting section 10 at the time of motion compensation. Usually, two tables for the Y signal and the C signal are separately provided. The field memory 3 is constituted by a FIFO type memory since there is no need to consider the motion correction.

The signal interpolated by the selector 2 in FIG. 8 has the signal form shown in FIG. 10 and is output from the terminal 12 as a still picture signal.

On the other hand, the signal interpolated by the selector 2 is decimated by the selector 46 to a state before the interpolation by the frame, and then interpolated by the field interpolator 8 to be interpolated by the field. Is output from the terminal 13.

The field interpolation processing of the moving image portion is performed by a two-dimensional low-pass filter as described in the above-mentioned document "MUSE-Hi-Vision transmission system", pp. 71-72. For example, the spread of taps of about 5 lines × 9 pixels is preferable.

FIG. 11 shows an example of a field interpolation process constituted by a two-dimensional low-pass filter. This filter acts as a spatial interpolation filter, and the input signal input to the terminal 14 is delayed by the line memories 47 and 21 for every one line for the Y signal and every two lines for the C signal. In the C signal, two color difference signals (RY, B-
Since the RY signal and the BY signal are repeated for each line for Y), the delay circuit 47 of 2H (two horizontal scanning periods) is used.
Is provided.

The signal after the delay is one line delay of the Y signal and two lines of the C signal, two lines of the Y signal and four lines of the C signal, three lines of the Y signal and six lines of the C signal. , The Y signal and the C signal are delayed by 4 lines and the C signal by 8 lines, respectively, as shown in FIG.
), The signals are switched by selectors 23, 24, 25 and 26, respectively, and five signals 27, 28, 29, 30 and 31 are obtained.

For the five signals selected and output by the selectors 23 to 26, the signal 29 is converted to a horizontal low-pass filter (L
PF) 34, the signals 28 and 30 and the signals 27 and 31 are added by adders 33 and 32, respectively, and input to horizontal low-pass filters 35 and 36.

The output signals of the three horizontal low-pass filters 34 to 36 are mixed by an adder 37 and output from a terminal 38 as a moving picture signal (field interpolation signal).

[0021]

As described above, in the MUSE decoder, since the motion compensation processing is performed only on the Y signal, the signal for frame interpolation is obtained by performing the motion compensation processing on the Y signal section and the C signal section. And those that have not been motion compensated.

If the field memory incorporates a motion correction process for the Y signal and a selector for switching between the Y signal portion and the C signal portion as in the conventional example, it is not possible to configure the memory only by address control. It was not possible, and the circuit configuration was complicated.

Further, in the conventional example shown in FIG.
When the block indicated by c is composed of one memory, it is necessary to switch the buffer amounts of the Y signal and the C signal at the time of motion compensation. Therefore, the two tables for the Y signal and the C signal are separately stored. Need to have a simple FIF
An O (first in first out) type memory structure could not be obtained.

On the other hand, since the field memory 3 does not need to consider the motion compensation, it can be constituted by a simple FIFO type memory.

For this reason, in the MUSE decoder,
The configuration of the field memory 3 differs from that of the field memory for constructing the block indicated by the broken line 6c. As a result, a problem arises in that two types of memories having different configurations are required.

Accordingly, the present invention provides a MUS signal for demodulating and reproducing a MUSE signal into an original wideband high-definition television signal.
It is an object of the present invention to solve the above problems in the E decoder, simplify the configuration of the field memory, and suppress an increase in the circuit scale accompanying the simplification.

[0027]

In order to achieve the above object, a MUSE decoder according to the present invention comprises a MUS decoder which is band-compressed by sub-samples that go around in a cycle of 4 fields.
In a MUSE decoder that demodulates and reproduces an E signal into an original broadband high-definition television signal, a motion correction processing unit performs motion correction on both the Y signal portion and the C signal portion, and performs a motion correction on the C signal portion. The circuit that performs the inverse correction for the correction position is shared with the video / video signal playback processing circuit .
And has the following configuration .

In the MUSE decoder of the present invention, the video / video signal reproduction processing circuit and the circuit for performing reverse correction (referred to as "reverse correction circuit") share a line delay network, and the reverse correction circuit includes a plurality of line-by-line correction circuits. A first selector for selecting any one of the delay outputs based on the vertical motion correction information, a circuit for performing reverse correction in the horizontal direction based on the horizontal motion correction information, and a circuit for performing reverse correction in the horizontal direction at one input terminal. And a second selector which is connected to the other input terminal and outputs a zero-delay output of a plurality of outputs of the line-by-line delay circuit, and switches and outputs these two inputs at a predetermined frequency. Be prepared.

According to another aspect of the present invention, there is provided a MUSE decoder in which a motion correction processing unit performs only vertical motion correction on a color (C) signal portion.

In a preferred aspect of another aspect of the present invention, the video / video signal reproduction processing circuit and the inverse correction circuit share a line delay network, and the inverse correction circuit includes a plurality of line units of the line delay network. A first selector for selecting one of the delay outputs based on the vertical motion correction information, an output terminal of the first selector connected to one input terminal, and a zero terminal of a line delay network connected to the other input terminal. A selector connected to an output corresponding to the delay, and switching and outputting these two inputs at a predetermined frequency.

[0031]

According to the present invention, based on the above configuration, the memory configuration of the motion correction processing section is simplified, the increase in the circuit scale is suppressed, and two field memories can be configured with the same configuration.

Further, according to the present invention, an increase in the circuit scale can be suppressed by a circuit configuration in which the reproduction processing circuit of the video moving image signal and the inverse correction circuit share the line delay circuit. Then, the reverse correction circuit switches and outputs the current frame in which the C signal portion is not reverse-corrected and the signal in which the motion correction processing is not performed by the reverse correction by a selector, and outputs the output of the reverse correction circuit to the interpolated signal. The signal is replaced with a C signal portion and output as a still image signal.

According to another aspect of the present invention, the configuration of the inverse correction circuit is simplified by the motion correction processing section performing only vertical motion correction on the C signal section.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

[0035]

Embodiment 1 FIGS. 1 to 5 show a first embodiment of the present invention.
This will be described with reference to Tables 1 to 3.

As described above, the signal for frame interpolation is obtained by subjecting the signal of the previous frame to a motion correction process. In the conventional example, the motion correction process is performed only on the Y signal portion. However, in the present embodiment, the motion correction process is performed on both the Y signal portion and the C signal portion, and the C that has been motion-corrected by the field interpolation portion is used. The inverse correction of the signal section is performed.

FIG. 1 is a block diagram showing the configuration of this embodiment. As shown in the figure, the configuration of the present embodiment is different from the prior art in that the Y / C signal switching selector 45 for the inter-frame interpolation signal does not exist and the Y of the inter-frame interpolation signal does not exist.
A significant difference from the conventional example shown in FIG. 8 is that a Y / C signal switching selector 9 for switching between the signal section and the C signal output from the field interpolation processing section 8 has been added.

In this embodiment, since the buffer amounts of the Y signal portion and the C signal portion are the same, the block indicated by the broken line 6a is
If address control is performed in consideration of the motion vectors shown in Tables 1 and 2, a FIFO type memory can be configured.

FIG. 2 shows a signal form after the frame is interpolated by the selector 2 in FIG. As shown in FIG. 2, since the previous frame data is all motion-compensated, the C signal portion and the Y signal portion have the same form. In FIG. 2, the point ○ indicates the data of the current frame, and the point x indicates the frame data of one frame before the motion corrected.

In the MUSE decoder processing, in the case of the still image signal of the C signal portion, the data of the X points of the C signal portion shown in FIG. 2 needs to be the data of the previous frame that has not been motion-compensated. It is necessary to correct the interpolation position of the data in the direction opposite to the motion correction. The inverse correction amount may be the value shown in Table 1 in the horizontal direction and the value shown in Table 2 in the vertical direction since the inverse correction amount may be temporally opposite to the motion correction amount.

By the way, as described in the conventional example, the field interpolation for a moving image has a configuration of a two-dimensional low-pass filter as shown in FIG. 11, and the C signal is delayed every two lines.

If the delay for each two lines in the two-dimensional low-pass filter is divided for each line as shown in FIG. 3, data B to I with a delay of 1 to 8 lines for each line of the input signal can be obtained. In this embodiment, this B-
Using the signal component of I, the C signal that has been motion-corrected in the vertical direction is inversely corrected.

In FIG. 1, the signal input to the field interpolation section 8 is a signal which is not thinned out unlike the conventional example (FIG. 8) in order to not erase the data interpolated between frames.

The field interpolation processing section 8 will be described with reference to FIG.

The signal input to the terminal 14 is applied to the C signal portion by the 1H (1 horizontal scanning period) line memory 15.
Data B to I delayed by 1 to 8 lines are obtained for each line. C
For the signal portion, the inverse correction of the vertical motion correction performed in the motion correction processing block 6a is performed by the control signal detection portion 10
Is performed by selecting one of the data B to I by switching the selector 16 based on the vertical motion vector signal from.

Table 3 shows the vertical motion vector and the selector 16
Indicates the correspondence of the data to be selected. The selector 16 is shown in Table 3
When the motion correction processing block 6a performs vertical motion correction of, for example, +3 lines, the selector 16 selectively outputs the signal B delayed by -3 lines from the center position E.

Next, the horizontal motion correction reverse correction processing unit 17 performs horizontal reverse correction on the signal output from the selector 16. The inverse correction processing unit 17 for horizontal motion correction performs inverse correction in units of pixels shown in Table 1 based on the horizontal motion vector signal from the control signal detection unit 10.

C of the signal subjected to the inverse vertical and horizontal correction
The signal section takes the form of FIG. FIG. 4 shows a signal form of an output of the horizontal motion correction inverse correction processing unit 17 of FIG. In the figure, the point 前 represents the previous frame data returned to a state where the motion correction processing has not been performed by the inverse correction circuit, and the point を represents the current frame data subjected to the inverse correction.

In the signal form of FIG. 4, since the data of the current frame is inversely corrected, it cannot be used as a still picture signal in the C signal section. The data of the current frame that has not been subjected to the motion correction processing is input from the input terminal 1 to the field interpolation processing unit 8 via the selector 2 and subjected to reverse correction.

Therefore, in the field interpolation processing section 8 shown in FIG. 3, the data E located at the center position in time is input to the contact on one side of the selector 18 as the data of the current frame, and the horizontal motion correction and the inverse correction are performed. The output of the processing unit 17 is input to the contact on the other side of the selector 18, and the selector 18 outputs 32 MHz.
The signal is switched and output at the sampling clock of z.

The data obtained in this way has the form shown in FIG. 5, and the data after interpolation between frames shown in FIG.
The signal part becomes the same as the still image signal. In FIG. 5, the point .largecircle. Represents the current frame data obtained from the point E which is temporally central in FIG. 3, and the point .DELTA. Represents the previous frame data which has been set to a state where no motion processing has been performed by the inverse correction. Figure 4
△ points are supported.

On the other hand, in the field interpolation of the moving picture in FIG. 3, the data A for the C signal is thinned out by the selector 20 and the data C, E, G and I are thinned out by the selector 22.
For the Y signal, the data A is decimated by the selector 20 to return to the signal state before frame interpolation, and then the field is interpolated by a two-dimensional low-pass filter. The basic configuration of the two-dimensional low-pass filter is the same as that of the above-described conventional example, and a description thereof will be omitted.

In FIG. 1, a field interpolation processing unit 8
Is replaced by the C signal portion of the signal after frame interpolation by the selector 9 and is output from the terminal 12 as a still image signal.

Therefore, according to the above-described first embodiment of the present invention, the delay amount of the interpolating signal is made the same for the Y signal and the C signal, and the C signal is subjected to reverse correction (return processing for motion correction). ) Can be shared with the field interpolation unit, so that an increase in circuit size can be suppressed, and the two field memories 3 and 4 can be configured with the same FIFO type memory. For this reason,
In this embodiment, the circuit configuration of the memory is simplified and the cost is reduced as compared with the conventional example requiring two memories having different configurations.

[0055]

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS.

FIG. 6 shows an MU according to the second embodiment of the present invention.
FIG. 7 is a block diagram showing an SE decoding process, and FIG. 7 is a block diagram of a field interpolation unit of the MUSE decoder according to the second embodiment of the present invention.

In FIG. 6, the signal for inter-frame interpolation is obtained by subjecting the signal of the previous frame to motion correction processing.
The vertical motion correction is performed on both the signal portion and the C signal portion, and the output signal of the vertical motion correction processing portion 43 is subjected to the horizontal motion correction by the horizontal motion correction processing portion 44 for the Y signal portion.
A signal portion that is not subjected to horizontal motion correction processing is used as a signal for inter-frame interpolation.

The selector 45 switches between the Y signal and the C signal as in the conventional example.

In the configuration of this embodiment, the block indicated by the broken line 6b can be constituted by a FIFO type memory if address control is performed in consideration of the vertical motion correction amount shown in Table 2.

In the present embodiment, unlike the first embodiment, it is only necessary to perform the inverse correction of only the vertical motion correction on the signal after inter-frame interpolation. The reverse correction of the vertical motion correction is performed using the circuit of the field interpolation processing unit 8 as in the first embodiment.

In this embodiment, the field interpolation processing unit 8
As shown in FIG. 7, the horizontal motion correction inverse correction processing unit 1 shown in FIG.
7 is different from the configuration of the first embodiment. The output of the selector 16 for selecting one of the signals B to I and performing the vertical motion correction and the output of the point E are connected to the contacts of the selector 18 respectively. Other circuit configurations are the same as in the first embodiment.

In this embodiment, the field interpolation processing section 8
Since the horizontal motion correction processing is performed only on the Y signal in the preceding stage, the horizontal inverse correction on the C signal is not performed. Note that the inverse correction to the vertical motion correction is the first correction.
The description is omitted because it is the same as the embodiment.

Therefore, also in the second embodiment of the present invention, the delay amount of the interpolating signal is made the same for the Y signal and the C signal, and the C signal is inversely corrected (return processing for vertical motion correction). ) Can be shared with the field interpolation processing unit, so that an increase in circuit scale can be suppressed, and the two field memories can be configured with the same FIFO type memory.

Although the present invention has been described with reference to various embodiments, the present invention is not limited to the above-described embodiments, but includes various embodiments according to the principle of the present invention.

Table 1 is a correspondence table showing horizontal motion vectors and the corresponding inverse correction amounts, and Table 2 is a correspondence table showing vertical motion vectors and the corresponding inverse correction amounts.
Table 3 is a correspondence table showing vertical motion vectors and data selected by the selector 16.

[0066]

[Table 1]

[0067]

[Table 2]

[0068]

[Table 3]

[0069]

As described above, the present invention provides a MUSE
Since the motion compensation processing of the decoder is performed for both the Y signal part and the C signal part, and the inverse correction circuit for the correction position of the motion compensation of the C signal part is shared with the circuit of the video moving picture signal reproduction processing, the motion compensation processing is performed. It is possible to configure a field memory in a block with a simple FIFO type memory, simplify the memory configuration, suppress an increase in circuit scale, and achieve cost reduction.

Further, according to the present invention, since the field interpolation circuit for video and the inverse correction circuit share a line delay circuit, an increase in circuit scale can be suppressed. Then, the reverse correction circuit switches and outputs the current frame in which the C signal portion is not reverse-corrected and the signal in which the motion correction processing is not performed by the reverse correction by a selector, and outputs the output of the reverse correction circuit to the interpolated signal. The signal is replaced with a C signal portion and output as a still image signal.

According to another aspect of the present invention, the C signal portion is configured to perform only the vertical motion correction processing, so that the horizontal motion correction circuit in the reverse correction circuit is not required, and The circuit configuration is simplified. Also, the MUSE decoder according to another aspect of the present invention has the effects of simplifying the memory configuration in the motion correction processing block, suppressing an increase in circuit scale, and achieving cost reduction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a signal form according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a field interpolation process according to the first embodiment of this invention.

FIG. 4 is a schematic diagram showing a signal form of a C signal area according to the first embodiment of the present invention.

FIG. 5 is a schematic diagram showing a signal form of a C signal area according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a second embodiment of the present invention.

FIG. 7 is a block diagram showing a field interpolation process according to a second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional MUSE decoder.

FIG. 9 is a schematic diagram showing a signal form of a MUSE signal.

FIG. 10 is a schematic diagram showing a signal form after frame interpolation.

FIG. 11 is a block diagram showing field interpolation processing in a conventional MUSE decoder.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... MUSE signal input terminal 2 ... Inter-frame interpolation selector 3, 4 ... Field memory 5 ... Motion correction processing part 6a, 6b, 6c ... Processing block corresponding in field memory 7 ... Inter-frame interpolation signal 8 ... Field Interpolation processing unit 9 Y / C signal switching selector 10 Control signal detection unit 11 Motion vector signal 12 Still image signal output terminal 13 Moving image signal output terminal 14 Input terminal 15 C signal 1H line memory 16 C signal reverse correction selector 17 ... horizontal motion correction reverse correction processing section 18 ... selector 19 ... C still image output terminal 20 ... movie thinning selector 21 ... Y signal 1H line memory 22 ... C moving image thinning selector 23,24,25 , 26 ... Y / C signal switching selector 27, 28, 29, 30, 31 ... two-dimensional filter data 32, 33 ... Arithmetic devices 34, 35, 36 Horizontal low-pass filter 37 Adder 38 Moving image output terminal 39 Current frame data 40 Previous frame data 41 subjected to motion correction processing 41 Previous frame data not subjected to motion correction processing 42 Current reverse corrected Frame data 43 ... Vertical motion correction processing unit 44 ... Horizontal motion correction processing unit 45 ... Y / C signal switching selector 46 ... Moving picture thinning selector 47 ... C signal 2H line memory 48 ... Synchronization signal 49 ... C signal 50 ... Y signal A ... Input data to the field interpolation unit B ... Data of one line delay of data A C ... Data of two lines delay of data A D ... Data of three lines delay of data A E ... Data of four lines delay of data A F: Data of data A delayed by 5 lines G: Data of data A delayed by 6 lines H: Data of data A delayed by 7 lines I: Data X 8 lines delayed data X point: point where C signal starts in one line of MUSE signal Y point ... point where Y signal starts in one line of MUSE signal

Claims (3)

(57) [Claims] 1. A MUSE decoder for demodulating and reproducing an MUSE signal band-compressed by sub-samples looping in a cycle of four fields into an original wide-band high-definition television signal, wherein a motion correction processing unit includes a luminance signal unit. And a circuit that performs motion correction on both the color signal portion and performs reverse correction on the correction position of the motion-corrected color signal portion (referred to as “reverse correction circuit”
) , A video / video signal reproduction processing circuit and a line delay circuit
Shared for a road network , wherein the inverse correction circuit is a line unit of the line delay network.
One of the multiple delayed outputs of
And a circuit for performing reverse correction in the horizontal direction based on horizontal motion correction information
And one input terminal of the output of the circuit for performing the inverse correction in the horizontal direction.
Is connected to another input terminal of the line delay network.
An output equivalent to zero delay is connected and these two inputs are
MUSE decoder and characterized in that it comprises a second selector for outputting switching at a constant frequency, the. 2. A sub-sun which makes a cycle with a period of 4 fields
MUSE signal band-compressed by pull
MUSE that demodulates and reproduces high quality television signals
In the decoder, a circuit in which a motion correction processing section performs motion correction on both the luminance signal section and the color signal section, and performs inverse correction on a correction position of the motion-corrected color signal section.
(Referred to as "reverse correction circuit") for the video / video signal reproduction processing circuit and the line delay network, and the motion correction processing section performs only vertical motion correction on the color signal. MUSE decoder. 3. A subsump that makes a cycle with a period of 4 fields.
The MUSE signal band-compressed by the
MUSE data that is demodulated and reproduced into high-definition television signals
In the coder, the motion correction processing unit is provided for both the luminance signal portion and the color signal portion.
To perform motion compensation and correct the position of the motion-compensated color signal section.
Circuit that performs reverse correction on the
), A video / video signal reproduction processing circuit and a line delay circuit
Share the road network, the inverse correction circuit, said line
A first selector for selecting one of a plurality of delay outputs per line of the delay network based on vertical motion correction information; an input terminal connected to an output of the first selector; the output of the zero delay equivalent of the line delay network is connected to, it comprises a selector for outputting switching these two inputs at a predetermined frequency, wherein the for the motion compensation processing unit is a color signal vertical
MUS characterized by performing only direction motion correction
E decoder.