JP2865770B2 - Manufacturing method of electronic circuit device - Google Patents
Manufacturing method of electronic circuit deviceInfo
- Publication number
- JP2865770B2 JP2865770B2 JP2036033A JP3603390A JP2865770B2 JP 2865770 B2 JP2865770 B2 JP 2865770B2 JP 2036033 A JP2036033 A JP 2036033A JP 3603390 A JP3603390 A JP 3603390A JP 2865770 B2 JP2865770 B2 JP 2865770B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- atmosphere
- manufacturing
- solder
- electronic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000463 material Substances 0.000 claims description 43
- 239000012298 atmosphere Substances 0.000 claims description 29
- 238000005219 brazing Methods 0.000 claims description 29
- 238000005304 joining Methods 0.000 claims description 24
- 230000004907 flux Effects 0.000 claims description 19
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 238000004140 cleaning Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 7
- 230000008018 melting Effects 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 2
- 229910052745 lead Inorganic materials 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims 3
- 229910052709 silver Inorganic materials 0.000 claims 1
- 229910052717 sulfur Inorganic materials 0.000 claims 1
- 239000000919 ceramic Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 5
- 230000004927 fusion Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000000356 contaminant Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000010405 reoxidation reaction Methods 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4864—Cleaning, e.g. removing of solder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、２つの異なる材料あるいは部材をろう付し
た電子回路装置の製造方法において、フラックスレスで
接合した電子回路装置の製造方法に関する。Description: BACKGROUND OF THE INVENTION The present invention relates to a method for manufacturing an electronic circuit device in which two different materials or members are brazed, and which is bonded without flux.
従来、イオンビームを用いたフラックスレス接合方法
については、ジェイ・バキューム・サイエンス・テクノ
ロジー,20（３）,3月号,1982年、第359頁から第363頁
（J.Vac.Sci.Techonol.,20（３）,March.1982,pp359−3
63）において論じられている。Conventionally, a fluxless joining method using an ion beam is described in J Vacuum Science Technology, 20 (3), March, 1982, pp. 359 to 363 (J. Vac. Sci. Techonol. , 20 (3), March. 1982, pp359-3.
63).
また、通常、ろう材を用いて２つの異なる材料あるい
は部材を接合する場合、フラックスが用いられている。
フラックスを用いることにより、材料あるいは部材およ
びろう材の表面の酸化皮膜を除去し、再酸化を防止して
表面の清浄さを保ち、ろう材の材料あるいは部材へのぬ
れを促進させることができる。しかし、従来、フラック
スを用いて接合を行った場合、第１図に示すように、フ
ラックスの気化によるボイド５が発生し接合強度が低下
するという問題があった。Usually, when two different materials or members are joined using a brazing material, a flux is used.
By using the flux, the oxide film on the surface of the material or member and the brazing material is removed, reoxidation is prevented, the surface is kept clean, and the wetting of the brazing material to the material or member can be promoted. However, conventionally, when joining is performed using a flux, as shown in FIG. 1, there has been a problem that voids 5 are generated due to vaporization of the flux and the joining strength is reduced.
フラックスレスにより部材を接合する場合、スパッタ
クリーニング後ろう材表面に酸化皮膜が成長するのを防
止するために、部材等の位置合わせを非酸化性雰囲気中
で行っていた。When joining members by fluxless, the members and the like are aligned in a non-oxidizing atmosphere in order to prevent an oxide film from growing on the surface of the brazing material after sputter cleaning.
上記従来技術は、以下の点について配慮されておら
ず、信頼性の高い接合部形成ができない事、およびフラ
ックスの洗浄作業による環境汚染（オゾン層の破壊）と
いう問題があった。The above prior art does not take the following points into consideration, and has a problem that a highly reliable bonding portion cannot be formed, and there is a problem of environmental pollution (destruction of an ozone layer) due to a flux cleaning operation.
（１）接合中に、フラックスの気化によるボイドが発生
し、接合信頼性を低下させる。(1) During bonding, voids are generated due to evaporation of the flux, and the bonding reliability is reduced.
（２）フラックスを、フレオンおよび塩素系有機溶剤で
洗浄する工程が必要である。また、フラックス残渣を完
全に洗浄することが難しい。(2) A step of cleaning the flux with freon and a chlorine-based organic solvent is required. Further, it is difficult to completely remove the flux residue.
上記従来技術は、非酸化性雰囲気中で位置合わせ及び
加熱を行っていたので、設備が複雑かつ大型になるとい
う問題があった。また、非酸化性雰囲気中での位置合わ
せは非常に困難であった。In the above-mentioned prior art, since alignment and heating were performed in a non-oxidizing atmosphere, there was a problem that equipment became complicated and large. In addition, alignment in a non-oxidizing atmosphere was very difficult.
本発明の目的は、フラックスレスで接合を行うことに
ある。It is an object of the present invention to perform fluxless bonding.
本発明の他の目的は、作業性を良くするため、材料あ
るいは部材およびろう材を大気中で位置合わせ等の作業
を行い、これをフラックスレス接合することにある。Another object of the present invention is to perform a work such as positioning of a material or a member and a brazing material in the atmosphere in order to improve workability, and to perform fluxless joining of the work.
上記目的を達成するために、本発明は、部品と回路基
板をフラックスレスではんだ接合する電子回路装置の製
造方法において、部品または回路基板に接合されたはん
だ表面の酸化膜を除去する工程と、次いで上記部品及び
回路基板を大気中にて位置合わせする工程と、位置合わ
せした部品及び回路基板間のはんだを非酸化性雰囲気内
にて加熱溶融する工程を備え、部品及び回路基板を接合
することを特徴とするものである。In order to achieve the above object, the present invention provides a method for manufacturing an electronic circuit device in which a component and a circuit board are solder-bonded in a fluxless manner, in which a step of removing an oxide film on a solder surface joined to the component or the circuit board, Next, the method includes a step of aligning the component and the circuit board in the atmosphere, and a step of heating and melting the solder between the aligned component and the circuit board in a non-oxidizing atmosphere to join the component and the circuit board. It is characterized by the following.
上記他の目的を達成するために、大気中での保持時間
とろう材の再酸化，再汚染との関係から、大気中で作業
可能な時間を求めたものである。In order to achieve the above and other objects, the workable time in the air was determined from the relationship between the holding time in the air and the reoxidation and recontamination of the brazing material.
第２図（ａ）に示すように、ろう材の表面には、厚い
酸化層および有機物汚染層６が存在する。そのため、ス
パッタクリーニングしないで、H2／N2，N2等の非酸化性
雰囲気中で加熱溶融接合した場合、第２図（ｂ），
（ｃ）に示すように、ぬれ，溶融はんだの表面張力によ
るフィレット形成，球帯化およびセルフアライメントが
不十分である。As shown in FIG. 2A, a thick oxide layer and an organic contaminant layer 6 exist on the surface of the brazing material. Therefore, in the case where the heat fusion bonding is performed in a non-oxidizing atmosphere such as H 2 / N 2 or N 2 without sputter cleaning, FIG.
As shown in (c), wetting, fillet formation due to the surface tension of the molten solder, spheroidization, and self-alignment are insufficient.
上記の問題点を解決するために、第３図に示すような
手段を採用した。第３図（ａ）は初期のろう材表面状
態、第３図（ｂ）はスパッタクリーニング後の表面状
態、第３図（ｃ）は大気中での再酸化状態、第３図
（ｄ）は加熱溶融した時の表面状態、第３図（ｅ）は溶
融接合後の表面状態を示している。第３図（ａ）から
（ｂ）に示すように、ろう材表面の酸化層および有機物
汚染層６を除去する。その後、大気中で作業をした後、
非酸化性雰囲気中でフラックスレス接合を行うものであ
る。スパッタクリーニング後、大気中を経過させても、
ろう材表面に生成する再酸化層，再汚染層は、第３図
（ｃ）に示すように、クリーニング前の初期の状態と比
較して非常に薄い。そこで、第３図（ｄ）に示すよう
に、非酸化性雰囲気中で加熱溶融した際、ろう材が膨張
して薄い酸化皮膜が破れ表面が再酸化しないので、新生
な露出面が現れる。この状態で接合すると、メタライズ
等の被接合材に新生面がぬれ始め、全体にスムーズにぬ
れ拡がり、第３図（ｅ）に示すように、良好な接合が得
られる。In order to solve the above problems, means as shown in FIG. 3 is employed. FIG. 3 (a) is the initial brazing material surface state, FIG. 3 (b) is the surface state after sputter cleaning, FIG. 3 (c) is the re-oxidized state in air, and FIG. 3 (d) is FIG. 3 (e) shows the surface state after heat fusion, and the surface state after fusion bonding. As shown in FIGS. 3A and 3B, the oxidized layer and the organic contaminant layer 6 on the surface of the brazing material are removed. Then, after working in the atmosphere,
Fluxless bonding is performed in a non-oxidizing atmosphere. After sputter cleaning, even in the air,
As shown in FIG. 3 (c), the reoxidized layer and the recontaminated layer formed on the brazing material surface are much thinner than the initial state before cleaning. Thus, as shown in FIG. 3 (d), when heated and melted in a non-oxidizing atmosphere, the brazing material expands, the thin oxide film is broken, and the surface is not reoxidized, so that a new exposed surface appears. When joined in this state, the new surface starts to be wet on the material to be joined, such as metallized, and spreads smoothly throughout the entire surface, and as shown in FIG. 3 (e), good joining is obtained.
原子あるいはイオンで、被接合材およびろう材をスパ
ッタクリーニングすることにより、表面の酸化層および
汚染層を除去することができる。By sputter cleaning the material to be joined and the brazing material with atoms or ions, an oxide layer and a contaminated layer on the surface can be removed.
また、非酸化性雰囲気中でろう材を加熱溶融させるこ
とにより、再酸化を防止して表面の清浄さを保ち、ろう
材のぬれ性を良好な状態に保つことができる。Further, by heating and melting the brazing material in a non-oxidizing atmosphere, reoxidation can be prevented, the surface can be kept clean, and the wettability of the brazing material can be maintained in a good state.
大気中で位置合わせ作業を行うことができるので、容
易な作業及び簡単な設備で位置合わせ作業を行うことが
できる。Since the positioning operation can be performed in the atmosphere, the positioning operation can be performed with simple operation and simple equipment.
大気中で、ろう材が再酸化，再汚染しても、フラック
スレス接合可能な限界の経過時間を求めることにより、
その時間内で大気中作業後、非酸化性雰囲気炉中で接合
を行うことにより、フラックスレス接合を可能にしてい
る。By calculating the maximum elapsed time for fluxless joining, even if the brazing material is reoxidized and recontaminated in the atmosphere,
After working in the air within that time, the bonding is performed in a non-oxidizing atmosphere furnace to enable fluxless bonding.
以下、本発明の実施例を第４図，第５図により説明す
る。An embodiment of the present invention will be described below with reference to FIGS.
第４図は、本発明の第１の実施例を示したものであ
る。半導体集積回路１を、セラミック基板３の作成工程
においてタングステンやモリブデンを焼付けその上にN
i,Auを順次めっきを施して形成したメタライゼーション
パッド８に、Pb5Snはんだ９を用いて接合したものであ
る。第４図（ａ）に示すように、Pb5Snはんだ9,メタラ
イゼーションパッド８ともに、Ar原子７によりスパッタ
クリーニングし、酸化層および有機物汚染層を除去す
る。次に、第４図（ｂ）に示すように、大気中で30分以
内で位置合わせた後、H2／N2（H2：N2＝1:3）炉中で加
熱溶融し接合を行い、フラックスレスで第４図（ｃ）に
示すような良好な接合部を得ることができた。本実施例
の全体像を第４図（ｄ）に示している。同様に、大気中
で１時間,2時間,5時間,8時間暴露後、H2／N2炉中で加熱
接合を行った結果、５時間までは良好な接続を示した
が、８時間では接合はするが、形状が球帯形状からはず
れることがわかった。この程度の時間が接合限界と推定
される。FIG. 4 shows a first embodiment of the present invention. The semiconductor integrated circuit 1 is baked with tungsten or molybdenum in the process of forming the ceramic substrate 3 and N
i, Au are bonded to a metallization pad 8 formed by sequentially plating using a Pb5Sn solder 9. As shown in FIG. 4 (a), both the Pb5Sn solder 9 and the metallization pad 8 are sputter cleaned with Ar atoms 7 to remove the oxide layer and the organic contaminant layer. Next, as shown in FIG. 4 (b), after aligning within 30 minutes in the air, H 2 / N 2 (H 2: N 2 = 1: 3) The heat-melting bonding in oven As a result, a good joint as shown in FIG. 4 (c) could be obtained without flux. FIG. 4D shows an overall image of the present embodiment. Similarly, after 1 hour, 2 hours, 5 hours, and 8 hours of exposure in the air, and performing heat bonding in an H 2 / N 2 furnace, a good connection was shown up to 5 hours. Although joining was performed, it was found that the shape deviated from the spherical band shape. It is estimated that this time is the welding limit.
次に、本発明の第２の実施例を第５図に示す。AlNキ
ャップ11をセラミック基板３に、Sn37Pb10を用いて接合
する封止構造体を示したものである。第５図（ａ）に示
すように、AlNキャップ11,セラミック基板３に供給され
ているSn37Pbはんだ10の表面をスパッタクリーニング
し、酸化層，汚染層を除去する。次に、第５図（ｂ）に
示すように、大気中で30分以内で位置合わせた後、H2／
N2炉中で加熱溶融し、フラックスレス接合を行うことに
より、第５図（ｃ）に示すような良好な接合部を得るこ
とができる。同様に、大気中暴露時間を変えて接合した
結果、第４図の例と同じ傾向を示した。被接合材へのろ
う材の供給も同様にフラックスレスで行う。Next, FIG. 5 shows a second embodiment of the present invention. 1 shows a sealing structure in which an AlN cap 11 is bonded to a ceramic substrate 3 using Sn37Pb10. As shown in FIG. 5A, the surface of the Sn37Pb solder 10 supplied to the AlN cap 11 and the ceramic substrate 3 is subjected to sputter cleaning to remove an oxide layer and a contamination layer. Next, as shown in FIG. 5 (b), after positioning in the air within 30 minutes, H 2 /
By performing heatless fusion in an N 2 furnace and performing fluxless bonding, a good bonded portion as shown in FIG. 5 (c) can be obtained. Similarly, as a result of joining by changing the exposure time in the atmosphere, the same tendency as in the example of FIG. 4 was shown. The supply of the brazing material to the materials to be joined is also performed without flux.
同様にして、PbとSnとからなる他のろう材、SnとAg,A
uとSn,AuとGeおよびAuとSiからなる他のろう材について
もフラックスレスで接合できる。Similarly, another brazing material composed of Pb and Sn, Sn and Ag, A
Other brazing materials consisting of u and Sn, Au and Ge, and Au and Si can be joined without flux.
上記の結果のように、大きな熱容量をもつ被接合材の
フラックスレス接合と接合時の位置合わせ作業を容易か
つ簡単な設備で行うためには、大気中での作業と従来か
ら使用されている非酸化性雰囲気炉とにより、加熱溶融
できることが重要である。そこで、これを可能とするた
め、ろう材の許容酸化皮膜の観点から酸化特性を調べた
のが、第６図である。その酸化に対する大気中暴露時間
の限界は、大気中暴露時間と酸化膜厚との関係から定量
的に求めることができ、第4,5図で示した結果とほぼ一
致する約６時間以上である。また、Pb5Snの100℃と150
℃の結果より温度上昇に伴い酸化膜厚の成長速度が大き
くなるため、高温環境では大気中暴露時間を短くする必
要がある。As shown in the above results, in order to perform fluxless joining of materials to be joined having a large heat capacity and alignment work at the time of joining with easy and simple equipment, work in the air and non-conventional non-working methods are required. It is important that an oxidizing atmosphere furnace can be heated and melted. In order to make this possible, FIG. 6 shows an examination of the oxidation characteristics from the viewpoint of an allowable oxide film of the brazing material. The limit of the air exposure time for the oxidation can be quantitatively determined from the relationship between the air exposure time and the oxide film thickness, and is about 6 hours or more, which is almost consistent with the results shown in Figs. . In addition, Pb5Sn at 100 ° C and 150 ° C
Since the growth rate of the oxide film thickness increases as the temperature rises from the result of ° C., it is necessary to shorten the exposure time in the atmosphere in a high temperature environment.
スパッタクリーニング後の、この酸化膜厚で接合する
には、さらに以下の特性を満足しなければならなかっ
た。各種のろう材に対して、接合として必要な特性は、
ぬれ性が良好なこと、ボイドが少ないこと、接合形状が
溶融はんだの表面張力に従った形状になること、位置合
わせずれを溶融接合時に修正するセルフアライメントが
起こること、および信頼性（Ｔ∞，高温放置強度）が良
好なことである。本発明を用いた接合（H2／N2雰囲気）
と従来法（スパッタクリーニング無，フラックス有無）
を用いた接合について、これらの特性を比較したのが第
１表である。In order to join with this oxide film thickness after the sputter cleaning, the following characteristics had to be further satisfied. The properties required for joining various brazing materials are:
Good wettability, few voids, joining shape follows the surface tension of molten solder, self-alignment to correct misalignment during fusion joining, and reliability (T∞, High temperature standing strength). Junction using the present invention (H 2 / N 2 atmosphere)
And conventional method (without sputter cleaning, with or without flux)
Table 1 shows a comparison of these characteristics with respect to the bonding using.
本発明を用いた接合は、ぬれ性，接合形状およびセル
フアライメント性において、従来法のフラックス有での
接合と同程度の優れた特性を示している。ボイドに関し
ては、発生が少なくフラックスレスの効果が表われてい
る。また、温度サイクル寿命についても、従来法のフラ
ックス有の場合よりもさらに優れた特性をもっている。
これに対して、フラックスを用いない従来の方法では、
いずれの特性も悪い。さらに、Ar,He,N2雰囲気炉，フレ
オンベーパー炉でも同様な傾向を示す。但し、この場合
は、酸素濃度を約10ppm以下に押さえる必要がある。 The joining using the present invention shows the same excellent properties in the wettability, the joining shape and the self-alignment property as the joining with the flux of the conventional method. With regard to voids, the occurrence is small and the effect of fluxlessness is exhibited. Also, the temperature cycle life is more excellent than that of the conventional method having a flux.
On the other hand, in the conventional method using no flux,
Both properties are bad. Further, the same tendency is observed in an Ar, He, N 2 atmosphere furnace and a freon vapor furnace. However, in this case, it is necessary to keep the oxygen concentration at about 10 ppm or less.
以上の特性の比較より、本発明を用いた接合は、従来
法より優れており、すべての特性を満足する。From the comparison of the above characteristics, the bonding using the present invention is superior to the conventional method and satisfies all the characteristics.
本発明は、他の電子回路，部品，例えば、LSIパッケ
ージ等のはんだ接続に適用し同様な結果が得られてい
る。The present invention has been applied to other electronic circuits and components, for example, solder connections of LSI packages and the like, and similar results have been obtained.
本発明によれば、２つの異なる材料あるいは部材をろ
う材で接合する場合に、接合に必要な特性をすべて満足
できるので、フラックスレス接合で大気中での位置合わ
せ作業で、かつ熱容量の大きな被接合材も接合すること
ができるという効果がある。これにより、益々増加する
電子回路装置を組立てる際、容易な作業，簡単な設備に
より無公害で、信頼性の向上が図れる。ADVANTAGE OF THE INVENTION According to this invention, when joining two different materials or members with a brazing material, since all the characteristics required for joining can be satisfied, the positioning operation in the air by the fluxless joining and the coating having a large heat capacity are performed. There is an effect that the joining material can also be joined. Thereby, when assembling an electronic circuit device which is increasing more and more, it is possible to improve reliability without pollution by simple operation and simple equipment.
第１図は従来のフラックスを用いた接合の１例を示した
断面図、第２図はろう材表面をスパッタクリーニングし
ないで、フラックスレス接合を行った１例を示した断面
図、第３図はろう材表面をスパッタクリーニング後、フ
ラックスレス接合を行った１例を示した断面図、第４図
は本発明の第１の実施例を半導体集積回路とセラミック
基板との接合を示した断面図、第５図は本発明の第２の
実施例の封止構造体における接合を示した断面図、第６
図は各種ろう材のスパッタクリーニング後の大気中暴露
時間と酸化膜厚との関係を示した図である。 １……半導体集積回路、２……はんだ、３……セラミッ
ク基板、４……フラックス、５……ボイド、６……酸化
層及び有機物汚染層、７……Ar原子、８……メタライゼ
ーションパッドW/Hi/Au、９……Pb5Snはんだ、10……Sn
37Pbはんだ、11……AlNキャップ。FIG. 1 is a cross-sectional view showing one example of conventional bonding using a flux, FIG. 2 is a cross-sectional view showing one example of performing fluxless bonding without sputter cleaning the surface of a brazing material, and FIG. FIG. 4 is a cross-sectional view showing an example in which fluxless bonding is performed after the surface of the brazing material is sputter-cleaned. FIG. 4 is a cross-sectional view showing the bonding between the semiconductor integrated circuit and the ceramic substrate according to the first embodiment of the present invention. FIG. 5 is a sectional view showing the bonding in the sealing structure according to the second embodiment of the present invention.
The figure shows the relationship between the exposure time in air after sputter cleaning of various brazing materials and the oxide film thickness. DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Solder, 3 ... Ceramic substrate, 4 ... Flux, 5 ... Void, 6 ... Oxide layer and organic contaminant layer, 7 ... Ar atom, 8 ... Metallization pad W / Hi / Au, 9 ... Pb5Sn solder, 10 ... Sn
37Pb solder, 11 ... AlN cap.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 林田 哲哉 東京都青梅市今井2326番地 株式会社日 立製作所デバイス開発センタ内 (72)発明者 白井 貢 神奈川県秦野市堀山下１番地 株式会社 日立製作所神奈川工場内 (56)参考文献 特開 昭61−5598（ＪＰ，Ａ) 特開 昭56−128670（ＪＰ，Ａ) 特開 昭57−94467（ＪＰ，Ａ) 特開 昭58−27327（ＪＰ，Ａ) 特開 平６−246478（ＪＰ，Ａ) 特開 平２−190489（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311 H01L 21/60 301 H05K 1/18 H05K 3/34 B23K 1/20──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Tetsuya Hayashida 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. Inside the factory (56) References JP-A-61-5598 (JP, A) JP-A-56-128670 (JP, A) JP-A-57-94467 (JP, A) JP-A-58-27327 (JP, A) JP-A-6-246478 (JP, A) JP-A-2-190489 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60 311 H01L 21/60 301 H05K 1/18 H05K 3/34 B23K 1/20
Claims (9)
接合する電子回路装置の製造方法において、被接合材お
よびろう材の表面の汚染層，酸化層を、原子あるいはイ
オンでスパッタクリーニング除去後、大気中で位置合わ
せ作業し、非酸化性雰囲気中でろう材を加熱溶融するこ
とにより、フラックスレスで接合したことを特徴とする
電子回路装置の製造方法。In a method of manufacturing an electronic circuit device for joining two different materials or members with a brazing material, a contaminated layer and an oxide layer on the surface of the material to be joined and the brazing material are removed by sputter cleaning with atoms or ions. A method of manufacturing an electronic circuit device, comprising: performing a positioning operation in the atmosphere; and heating and melting a brazing material in a non-oxidizing atmosphere to perform a fluxless joining.
i,またはこれらの組合せからなることを特徴とする請求
項１記載の電子回路装置の製造方法。2. The brazing material is composed of Pb and Sn, Sn and Ag, Au and Ge, Au and S.
2. The method for manufacturing an electronic circuit device according to claim 1, comprising i or a combination thereof.
層，酸化層のスパッタクリーニング後の大気中暴露時間
が、６時間以内であることを特徴とする請求項１記載の
電子回路装置の製造方法。3. The electronic circuit device according to claim 1, wherein the exposure time in the atmosphere after sputter cleaning of the contaminated layer and the oxide layer on the surfaces of the material to be joined and the brazing material is within 6 hours. Production method.
とを特徴とする請求項１記載の電子回路装置の製造方
法。4. The method according to claim 1, wherein the atmosphere is florinate vapor.
であることを特徴とする請求項１記載の電子回路装置の
製造方法。5. The method according to claim 1, wherein said atmosphere is an inert atmosphere such as N 2 , Ar, He.
であることを特徴とする請求項１記載の電子回路装置の
製造方法。6. The method according to claim 1, wherein the atmosphere is an active atmosphere such as H 2 / N 2 or H 2 .
接合する電子回路装置の製造方法において、 部品または回路基板に接合されたはんだ表面の酸化膜を
除去する工程と、 次いで上記部品及び回路基板を大気中にて位置合わせす
る工程と、 位置合わせした部品及び回路基板間のはんだを非酸化性
雰囲気内にて加熱溶融する工程を備え、部品及び回路基
板を接合することを特徴とする電子回路装置の製造方
法。7. A method of manufacturing an electronic circuit device for soldering a component and a circuit board by soldering without flux, comprising: removing an oxide film on a solder surface joined to the component or the circuit board; An electronic circuit device comprising: a step of aligning in the air; and a step of heating and melting the solder between the aligned component and the circuit board in a non-oxidizing atmosphere, and joining the component and the circuit board. Manufacturing method.
スではんだ接合する電子回路装置の製造方法において、 半導体集積回路に接合されたはんだ表面及び回路基板の
パッドの表面の酸化膜を除去する工程と、 次いで上記半導体集積回路に接合されたはんだ及び回路
基板のパッドを大気中にて位置合わせする工程と、 位置合わせした半導体集積回路及び回路基板のパッド間
のはんだを非酸化性雰囲気内にて加熱溶融する工程を備
え、半導体集積回路及び回路基板を接合することを特徴
とする電子回路装置の製造方法。8. A method of manufacturing an electronic circuit device for soldering a semiconductor integrated circuit and a circuit board in a fluxless manner, the method comprising: removing an oxide film from a solder surface bonded to the semiconductor integrated circuit and a surface of a pad of the circuit board. Next, a step of aligning the solder bonded to the semiconductor integrated circuit and the pad of the circuit board in the air, and heating the solder between the aligned semiconductor integrated circuit and the pad of the circuit board in a non-oxidizing atmosphere. A method for manufacturing an electronic circuit device, comprising a step of melting and bonding a semiconductor integrated circuit and a circuit board.
置封止構造体の製造方法において、 キャップ及び回路基板に接合されたはんだ表面の酸化膜
を除去する工程と、 次いで上記キャップに接合されたはんだ及び回路基板を
大気中にて位置合わせする工程と、 位置合わせしたキャップ及び回路基板間のはんだを非酸
化性雰囲気内にて加熱溶融する工程を備え、キャップ及
び回路基板を接合することを特徴とする電子回路装置封
止構造体の製造方法。9. A method for manufacturing an electronic circuit device sealing structure for sealing a circuit board with a cap, comprising: a step of removing an oxide film on a solder surface bonded to the cap and the circuit board; The method includes the steps of aligning the solder and the circuit board in the atmosphere, and heating and melting the solder between the aligned cap and the circuit board in a non-oxidizing atmosphere, and joining the cap and the circuit board. A method for producing an electronic circuit device sealing structure, which is characterized in that:
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2036033A JP2865770B2 (en) | 1990-02-19 | 1990-02-19 | Manufacturing method of electronic circuit device |
| US07/890,255 US5341980A (en) | 1990-02-19 | 1992-05-29 | Method of fabricating electronic circuit device and apparatus for performing the same method |
| US08/578,054 US5816473A (en) | 1990-02-19 | 1995-12-22 | Method of fabricating electronic circuit device and apparatus for performing the same method |
| US08/753,018 US5878943A (en) | 1990-02-19 | 1996-11-19 | Method of fabricating an electronic circuit device and apparatus for performing the method |
| US09/160,288 US6227436B1 (en) | 1990-02-19 | 1998-09-25 | Method of fabricating an electronic circuit device and apparatus for performing the method |
| US09/585,391 US6471115B1 (en) | 1990-02-19 | 2000-06-02 | Process for manufacturing electronic circuit devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2036033A JP2865770B2 (en) | 1990-02-19 | 1990-02-19 | Manufacturing method of electronic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03241755A JPH03241755A (en) | 1991-10-28 |
| JP2865770B2 true JP2865770B2 (en) | 1999-03-08 |
Family
ID=12458404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2036033A Expired - Lifetime JP2865770B2 (en) | 1990-02-19 | 1990-02-19 | Manufacturing method of electronic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2865770B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6471115B1 (en) * | 1990-02-19 | 2002-10-29 | Hitachi, Ltd. | Process for manufacturing electronic circuit devices |
| JPH06333987A (en) * | 1993-05-18 | 1994-12-02 | Hitachi Ltd | Electric circuit junction device and electric circuit junction method |
| JPH06246478A (en) * | 1993-03-02 | 1994-09-06 | Techno Oote:Kk | Brazing device and brazing method by ion washing |
| JPH0758149A (en) * | 1993-08-11 | 1995-03-03 | Nec Corp | Method for mounting chip part |
| JP2000049450A (en) * | 1998-05-25 | 2000-02-18 | Matsushita Electric Ind Co Ltd | Soldering of electronic component |
| JP2004071611A (en) | 2002-08-01 | 2004-03-04 | Matsushita Electric Ind Co Ltd | Device and method of mounting electronic part |
| JP5210496B2 (en) * | 2006-03-27 | 2013-06-12 | 神港精機株式会社 | Manufacturing method of semiconductor device |
| JP6663649B2 (en) * | 2015-04-14 | 2020-03-13 | 東レエンジニアリング株式会社 | Semiconductor chip mounting method and semiconductor device |
-
1990
- 1990-02-19 JP JP2036033A patent/JP2865770B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03241755A (en) | 1991-10-28 |
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