JP2842013B2 - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JP2842013B2 JP2842013B2 JP4040317A JP4031792A JP2842013B2 JP 2842013 B2 JP2842013 B2 JP 2842013B2 JP 4040317 A JP4040317 A JP 4040317A JP 4031792 A JP4031792 A JP 4031792A JP 2842013 B2 JP2842013 B2 JP 2842013B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- circuit device
- ceramic
- metal substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路装置に関
し、特に金属基板を用いた混成集積回路の構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a structure of a hybrid integrated circuit using a metal substrate.
【０００２】[0002]
【従来の技術】従来の金属基板を用いた混成集積回路
は、図４に示すように金属基板１をベースと、この金属
基板１上にエポキシあるいはポリイミドなどの樹脂から
なる絶縁層２を介して銅箔を貼付し、次にフォトリソグ
ラフィ法を用いて導体パターン３を形成する。次にハン
ダペースト６をスクリーン印刷により供給し、セラミッ
クチップコンデンサ４、ミニモールドトランジスタ５等
の電子部品を搭載し、リフロー法により基板側電極と電
子部品の電極をハンダ接続する。次に外部リード７を基
板側の端子ランドにハンダ付けを行って完成させる。2. Description of the Related Art A conventional hybrid integrated circuit using a metal substrate has a metal substrate 1 as a base and an insulating layer 2 made of a resin such as epoxy or polyimide on the metal substrate 1 as shown in FIG. A copper foil is attached, and then a conductor pattern 3 is formed by using a photolithography method. Next, the solder paste 6 is supplied by screen printing, and electronic components such as the ceramic chip capacitor 4 and the mini-mold transistor 5 are mounted. The board-side electrode and the electrode of the electronic component are soldered by a reflow method. Next, the external leads 7 are completed by soldering to the terminal lands on the substrate side.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の金属基
板を用いた混成集積回路装置では、チップ抵抗やチップ
セラミックコンデンサ４などのセラミック製のチップ部
品をアルミニウム金属基板１上に搭載する場合、セラミ
ックとアルミニウムの熱膨張係数がそれぞれ６．４×１
０-6／℃；２２．９×１０-6／℃と異なるため、部品の
サイズが大きくなると熱膨張差に起因するストレスによ
り、ハンダ接続部６にクラック等が発生し、接続の信頼
性が低下するという問題点があった。In the above-described hybrid integrated circuit device using a metal substrate, when a ceramic chip component such as a chip resistor and a chip ceramic capacitor 4 is mounted on an aluminum metal substrate 1, a ceramic And aluminum have a coefficient of thermal expansion of 6.4 × 1 each
0 −6 / ° C .; 22.9 × 10 −6 / ° C. Therefore, when the size of the parts increases, cracks or the like occur in the solder connection portion 6 due to the stress caused by the difference in thermal expansion, and the reliability of the connection increases. There was a problem that it decreased.
【０００４】[0004]
【課題を解決するための手段】本願発明の要旨は、金属
基板上に絶縁膜を介して形成された導体パターンと、該
導体パターンに接続されるセラミック製の構成部品とを
備えた混成集積回路装置において、前記セラミック製の
構成部品の表面に設けられた電極と前記導体パターンと
を接続し、かつ前記構成部品の下部に部品を実装可能な
形状のリード端子を有することである。SUMMARY OF THE INVENTION The gist of the present invention is to provide a hybrid integrated circuit having a conductor pattern formed on a metal substrate via an insulating film, and a ceramic component connected to the conductor pattern. In the apparatus, an electrode provided on the surface of the ceramic component is connected to the conductor pattern, and a lead terminal having a shape capable of mounting the component is provided below the component.
【０００５】[0005]
【発明の作用】セラミック製構成部品が導体パターンに
固定される際にセラミックと金属の熱膨張係数差に起因
してストレスが発生しても、リード端子がストレスを吸
収し、固定部に過大な応力は発生しない。When the ceramic component is fixed to the conductor pattern and stress is generated due to the difference in thermal expansion coefficient between the ceramic and the metal, the lead terminal absorbs the stress and the fixing portion becomes excessively large. No stress occurs.
【０００６】[0006]
【実施例】次に本発明について図面を参照し説明する。
図１は本発明の一実施例の金属基板を用いた混成集積回
路装置を示す断面図である。アルミニウムからなる１．
５ｍｍの厚さの金属基板１上に厚さ約１００μmの樹脂
絶縁層２を形成し、更に厚さ１８μmの銅箔を貼付け
る。次に、銅箔をフォトリソグラフィ技術を用いてパタ
ーン形成し、導体パターン３を形成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
FIG. 1 is a sectional view showing a hybrid integrated circuit device using a metal substrate according to one embodiment of the present invention. 1. made of aluminum
A resin insulating layer 2 having a thickness of about 100 μm is formed on a metal substrate 1 having a thickness of 5 mm, and a copper foil having a thickness of 18 μm is attached. Next, a conductive pattern 3 is formed by patterning a copper foil using photolithography technology.
【０００７】図２の斜視図２示すように、あらかじめ大
型サイズのセラミックチップコンデンサ４は電極にリー
ド端子７をハンダ接続しておく。As shown in a perspective view 2 of FIG. 2, a lead terminal 7 is soldered to an electrode of a large-sized ceramic chip capacitor 4 in advance.
【０００８】次にハンダペースト６をスクリーン印刷法
により基板１上のハンダ付ランドに供給し、前記チップ
コンデンサ４及びミニモールドトランジスタ５を搭載
し、リフロー法によりハンダ接続する。最後に外部リー
ド７をハンダ接続して完成する。Next, a solder paste 6 is supplied to a land with solder on the substrate 1 by a screen printing method, the chip capacitor 4 and the mini-mold transistor 5 are mounted, and solder connection is performed by a reflow method. Finally, the external leads 7 are connected by soldering to complete.
【０００９】図３は本発明の第２実施例の要部を示す断
面図である。第２実施例は大型セラミックコンデンサ４
に取り付けるリード端子７の高さを、ミニモールドトラ
ンジスタや小型チップ部品の高さより０．５〜１．０ｍ
ｍ以上高く設定することにより、大型セラミックコンデ
ンサ下部にも部品を実装することができるようにしたも
のである。その結果、実装密度が向上し、小形化が可能
となる。FIG. 3 is a sectional view showing a main part of a second embodiment of the present invention. The second embodiment is a large ceramic capacitor 4
The height of the lead terminal 7 to be mounted on the device is 0.5 to 1.0 m higher than the height of the mini-mold transistor or small chip component.
By setting the height higher than m, components can be mounted also under the large ceramic capacitor. As a result, the mounting density is improved and the size can be reduced.
【００１０】[0010]
【発明の効果】以上説明したように本発明は、大型のセ
ラミックチップコンデンサを金属基板に搭載する場合、
あらかじめ大型セラミックコンデンサに表面実装が可能
なリード端子を接続しておき、これを搭載することによ
り、セラミックコンデンサと金属基板の熱膨張差による
ストレスをリード端子が吸収するので、ハンダ接続部の
信頼性が飛躍的に向上し、さらに、リード端子の高さを
ミニモールドトランジスタや小型チップ部品の高さより
０．５〜１．０ｍｍ以上高く設定することにより、大型
セラミックコンデンサ下部にも部品を実装することがで
きるので、実装密度が向上し、小型化が可能となる効果
を有する。As described above, according to the present invention, when a large ceramic chip capacitor is mounted on a metal substrate,
By connecting the lead terminals that can be surface-mounted to a large ceramic capacitor in advance and mounting them, the lead terminals absorb the stress due to the difference in thermal expansion between the ceramic capacitor and the metal substrate. The height of the lead terminals is set to 0.5 to 1.0 mm or more higher than the height of mini-mold transistors and small chip components, so that components can be mounted under large ceramic capacitors. Therefore, there is an effect that the mounting density is improved and the size can be reduced.
【００１１】例えばセラミックチップコンデンサのサイ
ズが１２．５ｍｍ×１０ｍｍ×３ｍｍの大きさの場合、
温度サイクル（−５５℃〜＋１２５℃）試験で比較する
と、従来のコンデンサを直接金属基板に搭載した構造で
は、１６０サイクルで約３０％不良が発生したのに対
し、本発明の構造では不良の発生は認められなかった。For example, when the size of the ceramic chip capacitor is 12.5 mm × 10 mm × 3 mm,
Comparing with the temperature cycle (−55 ° C. to + 125 ° C.) test, the structure in which the conventional capacitor was directly mounted on the metal substrate caused about 30% failure in 160 cycles, whereas the structure of the present invention caused failure. Was not found.
【図１】第１実施例を示す断面図である。FIG. 1 is a sectional view showing a first embodiment.
【図２】第１実施例のセラミックチップコンデンサの斜
視図である。FIG. 2 is a perspective view of the ceramic chip capacitor of the first embodiment.
【図３】第２実施例の断面図である。FIG. 3 is a sectional view of a second embodiment.
【図４】従来例の断面図である。FIG. 4 is a sectional view of a conventional example.
１ 金属基板 ２ 絶縁層 ３ 導体パターン ４ セラミックチップコンデンサ ５ ミニモールドトランジスタ ６ ハンダ ７ 外部リード ８ リード端子 DESCRIPTION OF SYMBOLS 1 Metal substrate 2 Insulating layer 3 Conductor pattern 4 Ceramic chip capacitor 5 Mini mold transistor 6 Solder 7 External lead 8 Lead terminal
Claims (1)
体パターンと、該導体パターンに接続されるセラミック
製の構成部品とを備えた混成集積回路装置において、前
記セラミック製の構成部品の表面に設けられた電極と前
記導体パターンとを接続し、かつ前記構成部品の下部に
部品を実装可能な形状のリード端子を有することを特徴
とする混成集積回路装置。1. A hybrid integrated circuit device provided with a conductive pattern formed through an insulating film on a metal substrate and a ceramic component to be connected to the conductor pattern, before
The electrodes provided on the surface of the ceramic component and the front
Connecting the serial conductor pattern, and the lower part of the component
A hybrid integrated circuit device having lead terminals of a shape capable of mounting components .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4040317A JP2842013B2 (en) | 1992-01-30 | 1992-01-30 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4040317A JP2842013B2 (en) | 1992-01-30 | 1992-01-30 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05218291A JPH05218291A (en) | 1993-08-27 |
| JP2842013B2 true JP2842013B2 (en) | 1998-12-24 |
Family
ID=12577238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4040317A Expired - Lifetime JP2842013B2 (en) | 1992-01-30 | 1992-01-30 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2842013B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4060445B2 (en) * | 1998-06-18 | 2008-03-12 | 三菱電機株式会社 | Array antenna feeder |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01103163A (en) * | 1987-10-15 | 1989-04-20 | Toshiba Corp | Semiconductor rectifier |
-
1992
- 1992-01-30 JP JP4040317A patent/JP2842013B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01103163A (en) * | 1987-10-15 | 1989-04-20 | Toshiba Corp | Semiconductor rectifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05218291A (en) | 1993-08-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2842013B2 (en) | Hybrid integrated circuit device | |
| JPS6153852B2 (en) | ||
| JPH0458189B2 (en) | ||
| JPH11163510A (en) | Mounting structure for electronic component | |
| JPS5994493A (en) | Circuit substrate device with electronic part | |
| JPH0231794Y2 (en) | ||
| JP2917537B2 (en) | Mounting method of IC package for surface mounting | |
| JPS60140786A (en) | Mounting structure for chip type electronic part | |
| JP3174975B2 (en) | Electronic component mounting equipment | |
| JPH03116797A (en) | Thick film surface package circuit | |
| JPS60143618A (en) | Electronic part | |
| JPH118459A (en) | Mounting structure for surface-mounted component on printed wiring board | |
| JPH1140918A (en) | Ceramics element, component-mounting board and wiring board | |
| JPH01244693A (en) | Hybrid integrated circuit | |
| JPH09199669A (en) | Printed wiring board module | |
| JPH1022412A (en) | Ball grid array circuit board | |
| JPH0870063A (en) | Hybrid integrated circuit and circuit device containing the same | |
| JPH0756908B2 (en) | Electronic circuit device | |
| JPH0730056A (en) | Multichip module-mounted printed board | |
| JP2002158427A (en) | Printed wiring board, component mounting board and electronic apparatus | |
| JPH07235628A (en) | Mounting method of electronic device and semiconductor integrated circuit device | |
| JPH11243114A (en) | Mounting system for surface-mounting component | |
| JPS6123391A (en) | Device for mounting chip circuit part | |
| JPS62136096A (en) | Chip mounting substrate | |
| JPH0289395A (en) | Manufacture of electronic circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980310 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980922 |