JP2723936B2 - Semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an n.sup. ⁺ -I.sup.n ⁺ protection diode to which a space charge limited current formed on a semi-insulating GaAs (gallium arsenide) substrate is applied. Related to the manufacturing technology of GaAsMESFET (Me
The present invention relates to a protection diode manufacturing technique suitable for absorbing electrostatic surge current of a tal-semiconductor-field-effect-transistor.

[Conventional technology]

The n ⁺ -i-n ⁺ diode, as shown in FIG.
By providing a pair of n ^{+ -type} diffusion regions 2 and 3 on the main surface of the semi-insulating GaAs substrate 1 and providing diode electrodes 5 and 6 on the n ^{+ -type} diffusion regions 2 and 3 not covered by the insulating film 4 Manufactured.
That is, the semi-insulating GaAs substrate 1 has a specific resistance of 10 ⁷ to 10 ⁸
Ω · cm and high-resistance semi-insulator [intrinsic semiconductor:
i] is used. As a result, the n ^{+ type} diffusion regions 2, 3 and n ⁺
The energy band diagram of the intrinsic semiconductor region (i region) 7 between the shaped diffusion regions 2 and 3 is as shown in FIG. In the energy band diagram, a portion shown by a dotted line is a Fermi level (FL), 8 is a conduction band, and 9 is a valence band. Then, the interface between the n ⁺ -type region (n ⁺⁾ and the i-region potential barrier a is formed. This potential barrier a is approximately
0.6 eV. Note that the transition region is called a space charge limiting region b. The current (I) -voltage (V) characteristics of this diode are as shown in FIG.
V _R and V _R.

In such an n ⁺ -in ⁺ diode, when a predetermined voltage is applied to the n ^{+ -type} diffusion regions 2 and 3, a current flows from the semi-insulating portion to the space charge limiting region b. This phenomenon is equivalent to back-to-back type protection diode connected to n ⁺ -p ⁺ diode made in metallurgical back to back in the form, therefore, the structure of the n ⁺ -i-n ⁺ type, GaAs substrate It is known that a protective diode can be easily formed thereon (disclosed in JP-A-61-292965).

[Problems to be solved by the invention]

An n ⁺ -i-n ⁺ diode can be formed at the same time when an n ^{+ -type} diffusion region is formed when a FET is formed on a GaAs substrate.
There is no need to provide a shaped diffusion region, and the feature is that it is simple.

However, it has been clarified by the present inventors that this diode does not have a large surge absorbing power (surge absorbing power) for the following reasons. That, n ⁺ -i-n ⁺ diode can not contact area facing the n ⁺ type diffusion region and the i region made large due to the shallow diffusion layer depth of the n ⁺ -type diffusion region. Therefore, the passage cross-sectional area of the through surge current cannot be widened, and the surge absorbing ability is not as high as that of the pn metallurgical junction type diode.

Further, the inventors have found that the height of the potential barrier of the n ⁺ -i-n ⁺ diode is easily varied. That is, the potential barrier slightly changes depending on the growth conditions of the semi-insulating GaAs substrate.
For this reason, the characteristics of the n ⁺ -i-n ⁺ diode are likely to fluctuate.

An object of the present invention is to provide an n ⁺ −i−n ⁺ diode having a high surge absorbing power.

Another object of the present invention is to provide n ⁺ −i−n ⁺
An object of the present invention is to provide a semiconductor device having a diode.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, the n ⁺ -i-n ⁺ diode of the present invention has a pair of n ^{+ -type} diffusion regions provided on the main surface of a semi-insulating intrinsic GaAs substrate.
n ⁺ -i-n ⁺ with constitute a back-to-back type of diodes composed of, for i region between the n ⁺ -type diffusion region and the n ⁺ type diffusion region is irradiated with electron rays trap level Is provided. The trap level is 0.2 to 0.3 eV below the conduction band in the energy band.
It is located in. Therefore, if this trap level is filled with electrons, the potential barrier height with the n ^{+ type} diffusion region is 0.1 to 0.2.
eV, which is much lower than about 0.6 eV without this level.

[Action]

According to the above-described means, in the n ⁺ -i-n ⁺ diode of the present invention, the trap level is formed in the i region by the irradiation of the electron beam. This trap level is located 0.2 to 0.3 eV below the conduction band in the energy band. For this reason, if the trap level is filled with electrons, the potential barrier height with the n ^{+ -type} diffusion region becomes 0.1 to 0.2 eV, which is sufficiently lower than 0.6 eV without this level. Therefore, when a surge current (electrons) flows through the i-region, first, the initial electrons are trapped by the trap levels in the i-region. Then, as a result of filling the trap level with electrons, the energy level in the i-region approaches the energy level in the n ^{+ -type} diffusion region. As described above, once the energy level of the i region is close to the n ^{+ type} diffusion region, the surge current that flows next decreases the potential barrier from about 0.6 eV to about 0.1 to 0.2 eV, so that the n
^{The + -type} diffusion region flows into the n ^{+ -type} diffusion region, and the surge absorbing power increases.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a Ga with a protection diode according to an embodiment of the present invention.
FIG. 2 is an energy band diagram showing the outline of the n ⁺ −i−n ⁺ diode in the AsMESFET, FIG. 3 is an energy band diagram showing a state in which a surge current flows, and FIG. FIG. 5 is a graph showing current-voltage characteristics before flowing, FIG. 5 is a graph showing current-voltage characteristics when a surge current flows, and FIG.
FIG. 7 is a schematic plan view showing the outline of T, FIG. 7 is an equivalent circuit diagram, and FIGS. 8 to 11 are cross-sectional views in respective manufacturing steps of an n ⁺ −i−n ⁺ diode. Sectional view showing a state in which ion implantation is performed on a main surface of a semi-insulating GaAs substrate,
FIG. 9 is a cross-sectional view showing a semi-insulating GaAs substrate subjected to a diffusion treatment, and FIG. 10 is a semi-insulating GaAs partially irradiated with an electron beam.
FIG. 11 is a cross-sectional view showing a semi-insulating GaAs substrate on which a diode electrode is formed.

In this embodiment, an example in which the present invention is applied to a GaAs MESFET with a protection diode will be described. This protection diode Ga
The AsMESFET has a gate (G), a source (S), and a drain (D) as shown in the equivalent circuit of FIG.
It has a structure in which a back-to-back diode (protection diode) 10 is inserted between the gate and source of the SFET. Ga
The AsMESFET takes advantage of the physical property that GaAs has a higher electron mobility than Si, and reduces the gate length of the device to 1 μm or less to enable high-speed operation.
For this reason, the electrostatic breakdown strength decreases. Therefore, in order to increase the electrostatic breakdown strength, a high-performance protection diode is provided between the gate and the source.

In the GaAs MESFET chip (semiconductor element) 20, electrode patterns such as a source, a drain, and a gate are as shown in FIG. That is, a pair of source electrode 21 and drain electrode 22 having a rectangular pattern are provided on the main surface of the rectangular chip 20. Also, this source electrode
An elongated gate electrode 23 extends between the drain electrode 21 and the drain electrode 22. The portion of the gate electrode 23 that is separated from the source electrode 21 and the drain electrode 22 becomes wider and becomes a wire bonding portion.
Make up 24. The source electrode 21 and the drain electrode 22 are also provided with wire bonding portions 25 and 26.

On the other hand, on the left side of the chip 20 protection diode 10, i.e. composed n ⁺ -i-n ⁺ diode 10 with n ⁺ -i-n ⁺ is provided. The n ⁺ -i-n ⁺ diode 10 is formed by a pair of n ^{+ -type} diffusion regions 2, 3 and an intrinsic semiconductor region (i-region) 7 between the n ^{+ -type} diffusion regions 2, 3, as shown by a dotted line. It is configured. The intrinsic semiconductor region 7 also serves as a trap region 27 formed by electron beam irradiation as shown by a two-dot chain line. Further, the n ^{+ type} diffusion regions 2, 3
Above are provided diode electrodes 5 and 6, respectively. One diode electrode 5 extends on the surface of the chip 20, and the extended wiring portion 28 is electrically connected to the source electrode 21. In addition, the other diode electrode 6
The wiring section 29 is electrically connected to the gate electrode 23.

Next, the structure of the n ⁺ −i−n ⁺ diode 10 will be described in detail. That is, FIG. 1 shows an n ⁺ -i-n ⁺ diode.
FIG. 10 is a cross-sectional view showing the structure of No. 10. n ⁺ −i−n ⁺ diode 10
Is formed by providing a pair of n ^{+ -type} diffusion regions 2 and 3 on the surface of an intrinsic semi-insulating GaAs substrate 1. Semi-insulating G
aAs substrate 1 has an intrinsic (int) in which the specific resistance ρ is 10 ⁷ to 10 ⁸ Ω · cm.
rinsic) semiconductor. Further, the n ^{+ type} diffusion region
A few are extrinsic with donors
It is a semiconductor.

As shown in FIG. 8, the n ^{+ -type} diffusion regions 2 and 3 are selectively formed on the main surface of the semi-insulating GaAs substrate 1 to a thickness of about 5,000 mm.
After the O ₂ film 31 is provided, Si ions 32 are implanted using the SiO ₂ film 31 as a mask, and annealing is performed, thereby forming the structure as shown in FIG. The implantation of the Si ions 32 is performed at 150 KeV and a dose of 3 × 10 ¹³ cm ⁻² . The implanted Si ions 32 are placed in an atmosphere containing As at 800 ° C.
Activated by annealing for 0 minutes. The activated Si ions 32 diffuse to a depth of 0.1 to 0.2 μm to form n ^{+ -type} diffusion regions 2 and 3. The n ^{+ -type} diffusion regions 2 and 3 have a sheet resistance of 100 to 150 Ω / □. Further, l between the n ⁺ -type diffusion region 2 and the n ⁺ -type diffusion region 3 has a number of [mu] m.

By implanting Si ions 32 into the intrinsic semi-insulating GaAs substrate 1 at a predetermined distance in this manner, the n ⁺ -i-n ⁺ diode 10 having the semi-insulating GaAs substrate 1 as an i (intrinsic) portion.
Is formed.

On the other hand, in this embodiment, as shown in FIG. 1, the trap region 27 is located in the i region 7 between the pair of n ^{+ -type} diffusion regions 2 and 3.
(Regions indicated by dots) are provided, and a trap level (electron trap level) 33 is formed as shown in the energy band diagram of FIG. This trap level
Numeral 33 denotes a corresponding n ^{+ type} diffusion region 2, as shown in FIG.
It is formed by irradiating the portion of the intrinsic semiconductor region 7 between the three with the electron beam 34. The electron beam irradiation is performed, for example, at a driving energy of 0.7 to 2 MeV and a dose of 1 × 10 ¹² to 1 × 10 ¹⁶ cm.
^-2 . As a result, the depth of the n ⁺
A trap region 27 which is approximately twice as large as the diffusion regions 2 and 3 is formed. As shown in the energy band diagram of FIG. 2, the trap level 33 of the trap region 27 is located at a position of heV below the conduction band 8, for example, 0.2 to 0.3 eV. In the energy band diagram, the portion indicated by the dotted line is the Fermi level (FL), 8 is the conduction band, and 9 is the conduction band.
Is the valence band. Then, the interface between the n ⁺ -type region (n ⁺⁾ and the i-region potential barrier a is formed. This potential barrier a
Is about 0.6 eV because the bandgap of GaAs is 1.42 eV at 300 K, and the conduction band 8 is about 1 eV above the Fermi level in n ^{+ type} GaAs. The transition region is called a space charge limiting region b. Since the electron beam irradiation is specified and applied to the i region 7 for forming a diode, it does not affect other regions.

On the n ^{+ -type} diffusion regions 2, 3, diode electrodes 5, 6 are formed of an AuGe (gold / germanium) alloy, as shown in FIG. Thereby, the protection diode 11 is formed.

Next, the operation of the n ⁺ −i−n ⁺ diode 10 will be described. In the n ⁺ -in ⁺ diode 10, a trap region 27 having a trap level 33 is provided in the intrinsic semiconductor region (i region) 7 between the n ^{+ -type} diffusion regions 2 and 3. Therefore, the following effects can be obtained. The energy band diagram of the n ⁺ -i-n ⁺ diode having the conventional structure is as follows.
As described above, the result is as shown in FIG. in this case,
The height of the energy barrier does not change before and after the surge current flows, and is about 0.6 eV. Therefore, the IV characteristic of the conventional diode is unchanged as shown in FIG.

On the other hand, in the energy band diagram of the n ⁺ −i−n ⁺ diode 10 of the present invention, the trap level 33 exists in the i region 7. As shown in FIG. 2, the trap level 33 exists in the i region 7 until immediately before the surge current flows, but the energy barrier is a, that is, about 0.6 eV, as in the case of the conventional structure. is there. Therefore, the IV characteristic at the moment when the surge current starts to flow is as shown in FIG. 4, which is the same as the conventional case shown in FIG. That is, the n ⁺ −i−n ⁺ diode 10 of the present invention has the same withstand voltage as the conventional one except when a surge current flows, and the MESFET to which the protection diode 10 is connected is no worse than the conventional one. No effect.

On the other hand, once the surge current starts to flow, the electrons 35 are captured by the trap levels 33 in the i-region 7, and the energy band diagram becomes as shown in FIG. 3, and the potential barrier d drops to about 0.1 to 0.2 eV. The I-V characteristic corresponding to this state, as shown in FIG. 5, compared with the I-V characteristic of a state before the start flow of the surge current, the diode breakdown voltage _{V R '(V R'<} V R), - V _R ′ (−
V _R ′> −V _R ), which makes it easier for the subsequent surge current to pass through the n ⁺ −i−n ⁺ portion. Thus, according to the structure of the present invention, the n ^{+ type} diffusion region 2,
N ⁺ −i−n ⁺ diode 1 having a small opposing area between 3 and i region 7
Even if it is 0, a diode having a good surge absorbing power can be obtained.

According to such an embodiment, the following effects can be obtained.

(1) n ⁺ -i-n ⁺ diode of the present invention, an intrinsic semiconductor region have a trapping region having a trap level, a surge current flows, the intrinsic semiconductor region n ⁺
The potential barrier for the diffusion region is about 0.6 eV to 0.1 to 0.2 eV
Therefore, the following surge current flows easily, and the effect of increasing the surge absorbing power as in the case of the pn junction diode is obtained.

(2) According to the above (1), the n ⁺ -i-n ⁺ diode of the present invention has an effect of improving the electrostatic breakdown resistance of the MESFET since the surge absorbing power is increased.

(3) According to the present invention, since a trap level is formed by electron beam irradiation with good controllability, a desired trap level can be formed with good reproducibility even when the potential barrier of the semi-insulating GaAs substrate fluctuates. The effect that can be obtained is obtained.

(4) According to the above (3), according to the present invention, a trap level can be formed with good reproducibility, so that the effect of stabilizing the characteristics of the n ⁺ -i-n ⁺ diode can be obtained.

(5) According to the above (4), according to the present invention, a trap level can be formed with good reproducibility, so that the effect of improving the yield can be obtained.

(6) According to (1) to (5), according to the present invention,
The synergistic effect that an n ⁺ -in ⁺ diode excellent in surge absorption can be provided, and an inexpensive GaAs MESFET with a protection diode having a large resistance to electrostatic breakdown can be provided.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. For example, even if a semiconductor other than GaAs is used as the intrinsic semiconductor substrate, the same effect as in the above embodiment can be obtained. In this case, it is necessary to devise a circuit because Si can easily flow electrons even in an intrinsic semiconductor state.

In the above embodiment, the trap level 33 is formed by electron beam irradiation. However, the trap level 33 may be formed by plasma irradiation or neutron beam irradiation.

In the above description, the invention made mainly by the inventor has been described with the application field of the protection diode as the background of the application.
Although the description has been given of the case where the present invention is applied to the manufacturing technology of the GaAs MESFET, the present invention is not limited to this, and can be applied to the manufacturing technology of the GaAs IC and the like.

The present invention is applicable to the manufacture of a semiconductor device incorporating at least an n ⁺ -in ⁺ diode.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

Since the n ⁺ -i-n ⁺ diode of the present invention has an electron trap level provided by electron beam irradiation in the intrinsic semiconductor region serving as a semi-insulating high-resistance region, the surge current causes the n ⁺ -i ⁺ When flowing through the −n ⁺ portion, the trap level is filled with electrons, so that the n ⁺
The height of the potential barrier for the shaped diffusion region is reduced. Therefore, according to the present invention, the surge current penetration margin is increased,
The performance of the protection diode against electrostatic breakdown can be improved.

[Brief description of the drawings]

FIG. 1 shows a GaAs with a protection diode according to an embodiment of the present invention.
FIG. 2 is an energy band diagram showing the outline of the n ⁺ −i−n ⁺ diode in the MESFET, FIG. 3 is an energy band diagram showing a state in which a surge current flows, and FIG. FIG. 5 is a graph showing a current-voltage characteristic before flowing, FIG. 5 is a graph showing a current-voltage characteristic when a surge current flows, FIG. 6 is a schematic plan view showing an outline of the FET, and FIG. Similarly, FIG. 8 shows a semi-insulating property in the production of n ⁺ −i−n ⁺ diode.
FIG. 9 is a cross-sectional view showing a state in which ions are implanted into the main surface of the GaAs substrate. FIG. 9 is a cross-sectional view showing a semi-insulating GaAs substrate which has also been subjected to diffusion processing. FIG. FIG. 11 is a cross-sectional view showing a semi-insulating GaAs substrate on which a diode electrode is formed, FIG. 12 is a cross-sectional view showing an outline of a conventional n ⁺ −i−n ⁺ diode, FIG. 13 is an energy band diagram, and FIG. 14 is a graph showing current-voltage characteristics. 1 ... semi-insulating GaAs substrate, 2,3 ... n ^{+ type} diffusion region, 4 ...
... Insulating film, 5,6 ... Diode electrode, 7 ... Intrinsic semiconductor region (i-region), 8 ... Conduction band, 9 ... Full band, 10 ...
... n ⁺ -in ⁺ diode (protective diode), 20 ... chip, 21 ... source electrode, 22 ... drain electrode, 23 ...
Gate electrode, 24 ... Wire bonding part, 25,26 ...
Wire bonding portion, 27 ...... trapping region, 28 ...... wiring portion 29 ...... wiring portion 31 ...... SiO ₂ film, 32 ...... Si ions,
33 ... trap level, 34 ... electron beam, 35 ... electron.

Claims (3)

(57) [Claims] An intrinsic semiconductor substrate and a pair of impurity diffusion regions provided on a main surface of the intrinsic semiconductor substrate, wherein the pair of impurity diffusion regions and the intrinsic semiconductor region between the impurity diffusion regions are back-to-back. Wherein the intrinsic semiconductor region is provided with a trap level. 2. A semi-insulating GaAs substrate, a pair of n ^{+ -type} diffusion regions provided on a main surface of the substrate, and a surface layer of an intrinsic semiconductor region between the pair of n ^{+ -type} diffusion regions. 2. The semiconductor device according to claim 1, comprising a trap level. 3. The semiconductor device according to claim 2, wherein a trap level of said intrinsic semiconductor region is formed by electron beam irradiation and is about 0.1 to 0.2 eV.